6. Field-Effect · PDF file Field-Effect Transistor The field-effect transistor (FET) is a...

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Transcript of 6. Field-Effect · PDF file Field-Effect Transistor The field-effect transistor (FET) is a...

  • Field-Effect Transistor

    Outline:  Introduction to three types of FET:

    6. Field-Effect Transistor

     Constructions, Characteristics & Transfer curves of: JFET & MOSFET

    JFET MOSFET & CMOS MESFET

  • Field-Effect Transistor

    The field-effect transistor (FET) is a three- terminal device used for a variety of applications that match, to a large extent, those of the BJTs.

    Introduction

     The primary difference between the two types of transistor is the fact that: The BJT is a current-controlled device, whereas the FET is a voltage-controlled device.

  • Field-Effect Transistor

    For BJT, the IC is a direct function of IB ;

    In both cases, output current is controlled by an input parameter.

    For FET, ID will be a function of the VGS .

     The term field effect: For the FET, an electric field is established by the charges present, which controls the conduction path of the output circuit without direct contact between the controlling and controlled quantities.

  • Field-Effect Transistor

     The BJT is a bipolar device, which means that the conduction level is a function of two charge carriers, electrons & holes. The FET is a unipolar device, depending solely on either electrons or holes.

     One of the most important characteristics of the FET is its high input impedance.

     Typical Av of BJT is much greater than that of FET.

  • Field-Effect Transistor

     FETs are more temperature stable than BJTs, and smaller than BJTs, making them particularly useful in integrated- circuit (IC) chips.

     Three types of FETs are presented here:  Junction Field-Effect Transistor, JFET  Metal Oxide Semiconductor Field-Effect

    Transistor, MOSFET  Metal Semiconductor Field-Effect

    Transistor, MESFET

  • Field-Effect Transistor

     For JFET:

    They are simply divided into n-channel and p-channel JFETs, of which the charge carries are electrons and holes respectively.

     For MOSFET:

    The category is further broken down into depletion and enhancement type, with each has n-channel and p-channel types.

  • Field-Effect Transistor

    Due to its thermal stability & other general characteristics, MOSFET is widely used in computer & DSP fields.

    Furthermore, by using both n-channel and p-channel MOSFETs together, a new type of FET, Complementary MOSFET (CMOS) is created.

    It has high input impedance, fast switching speeds and low power consumption.

  • Field-Effect Transistor

     For MESFET: It is a more recent development and takes full advantage of the high-speed property of GaAs for RF and computer design. However, it is relatively expensive.

    CMOS logic design is now a new discipline. And modern digital logic devices, like DSP processors, micro-controllers and FPGAs, are all made of CMOS materials.

  • Field-Effect Transistor

    Figure: Difference between BJT & FET

  • Field-Effect Transistor

    The JFET is a three-terminal device with one terminal capable of controlling the current between the other two.

    Construction of JFETs

    The n-channel device will be the prominent device, just like npn transistor in the discussion of BJT. For p-channel device, the result will be obtained by changing the signs of some parameters.

  • Field-Effect Transistor

    The basic construction of n-channel JFET is shown in the figure.

     The major part of the structure is the n- type of material, which forms the channel between the embedded layer of p-type material.

     The top of the n-type of material is connected to a terminal called drain (D), whereas the lower end called source (S).

  • Field-Effect Transistor

     The two p-type of material are connected together and to the gate (G) terminal.

     So the JFET has two p-n junctions under no-bias conditions.

     And a depletion region is generated at each junction with no free carrier.

     Also illustrated in the figure, it is the water analogy.

  • Field-Effect Transistor

    The water pressure can be likened to the applied voltage from drain to source (inside the JFET), which establishes a flow of water (electrons) from the spigot (source). For FET, the gate through an applied potential, controls the flow of current to the drain. The terminology, (D, G & S), is defined for electron flow.

  • Field-Effect Transistor

    Figure: JFET Construction

  • Field-Effect Transistor

    As shown in the figure, a positive voltage VDS ( =VDD)is applied across the channel.

    Biasing: VGS = 0, VDS > 0

    The gate is connected directly to the source to establish the condition VGS= 0. The electrons are drawn to the drain, leading to the current ID, which is also the same as IS. And the ID is solely limited by the resistance of the n-channel between D & S.

  • Field-Effect Transistor

    The depletion region is wider near the top of both p-type materials. The reason is that upper region is more reverse-biased than the lower part, thus a wider depletion region.

    Also, the p-n junction is reverse-biased for the whole length of the channel, leading to no current in the gate terminal. IG = 0 is an important characteristic of JFET.

  • Field-Effect Transistor

    When VDS increasing, ID will also increase.

    As VDS increases, the depletion regions will widen, causing reduction in the channel width and a higher resistance.

    If VDS is increased to a level VP, where it appear that the two depletion regions would touch, a condition referred to as pinch-off will result.

  • Field-Effect Transistor

    The level of VDS that causes pinch-off condition is called pinch-off voltage, denoted by VP.

    Actually, under pinch-off condition, the current ID maintains a saturation level, defined as IDSS. IDSS is the maximum drain current for a JFET and is defined by the conditions VGS=0 and VDS > |VP|.

  • Field-Effect Transistor

    Figure: Biasing of JFET (VGS = 0, VDS > 0)

  • Field-Effect Transistor

    Figure: ID versus VDS for VGS = 0

  • Field-Effect Transistor

    For BJT, the characteristics is plotted to show the relationship between IC and VCE for different levels of IB.

    Biasing: VGS < 0

    The VGS is the controlling voltage of JFET, just like IB for the BJT.

    For FET, the characteristics is drawn to show the relationship between ID and VDS for various levels of VGS.

  • Field-Effect Transistor

    For the n-channel device, VGS is made more and more negative from its VGS = 0 level.

    Eventually, when VGS = -VP , it is sufficiently negative to establish a saturation level that is zero.

    The saturation level of ID has been reduced as VGS is made more and more negative.

  • Field-Effect Transistor

    For all practical purpose, the device has been “turned off”. The VGS that results in ID = 0 is defined by VGS = VP , with VP being a negative voltage for n-channel and a positive voltage for p- channel JFETs.

    The region to the right of the pinch-off locus is employed in linear amplifier and referred to as linear amplification region.

  • Field-Effect Transistor

    Figure: Biasing of JFET (VGS < 0)

  • Field-Effect Transistor

    Figure: JFET characteristics (VGS < 0)

  • Field-Effect Transistor

    The graphic symbols for the n-channel and p-channel JFETs are shown in the figure.

    Symbols of JFET

    Note that the arrow is pointing in for the n- channel device. This means that IG would flow if the p-n junction were forward-biased. For p-channel device, the only difference in the symbol is the direction of the arrow.

  • Field-Effect Transistor

    Figure: Symbols of JFET

  • Field-Effect Transistor

    Transfer Characteristics

    IC= f(IB) = IB

    For JFET, the relationship between the output and input quantities is not as simple as the that of BJT.

    For BJT, the output current IC and input controlling current IB are related by constant , which is in the following equation form,

  • Field-Effect Transistor

    The relationship between the ID output and VGS is defined by Shockley’s equation:

    2

    1  

      

     

    P

    GS DSSD V

    VII

    where the IDSS and VP are constants, and VGS controls the ID.

    The squared term results in a nonlinear relationship between the ID output and VGS .

  • Field-Effect Transistor

    The transfer characteristics are properties of JFET itself and are unaffected by the network in which the device is used. Obviously, the transfer characteristics can be obtained by Shockley’s equation. It can also be obtained from the output drain characteristics.  We draw both curves with a common

    vertical scaling.

  • Field-Effect Transistor

     One is a plot of ID versus VDS , whereas the other is ID versus VGS .

     Using the drain characteristics on the right of the vertical axis, we can draw a horizontal line from t