6. Field-Effect Transistorjpkc.xidian.edu.cn/ac/uploads/ppt/chapter6.pdf · Field-Effect Transistor...

Field-Effect Transistor

Outline: Introduction to three types of FET:

6. Field-Effect Transistor

Constructions, Characteristics & Transfer curves of:JFET & MOSFET

JFETMOSFET & CMOSMESFET


The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large extent, those of the BJTs.

Introduction

The primary difference between the two types of transistor is the fact that:The BJT is a current-controlled device, whereas the FET is a voltage-controlleddevice.


For BJT, the IC is a direct function of IB ;

In both cases, output current is controlled by an input parameter.

For FET, ID will be a function of the VGS .

The term field effect:For the FET, an electric field is established by the charges present, which controls the conduction path of the output circuit without direct contact between the controlling and controlled quantities.


The BJT is a bipolar device, which means that the conduction level is a function of two charge carriers, electrons & holes.The FET is a unipolar device, depending solely on either electrons or holes.

One of the most important characteristics of the FET is its high input impedance.

Typical Av of BJT is much greater than that of FET.


FETs are more temperature stable than BJTs, and smaller than BJTs, making them particularly useful in integrated-circuit (IC) chips.

Three types of FETs are presented here: Junction Field-Effect Transistor, JFET Metal Oxide Semiconductor Field-Effect

Transistor, MOSFET Metal Semiconductor Field-Effect

Transistor, MESFET


For JFET:

They are simply divided into n-channeland p-channel JFETs, of which the charge carries are electrons and holes respectively.

For MOSFET:

The category is further broken down into depletion and enhancement type, with each has n-channel and p-channel types.


Due to its thermal stability & other general characteristics, MOSFET is widely used in computer & DSP fields.

Furthermore, by using both n-channel and p-channel MOSFETs together, a new type of FET, Complementary MOSFET (CMOS) is created.

It has high input impedance, fast switching speeds and low power consumption.


For MESFET:It is a more recent development and takes full advantage of the high-speed property of GaAs for RF and computer design.However, it is relatively expensive.

CMOS logic design is now a new discipline. And modern digital logic devices, like DSP processors, micro-controllers and FPGAs, are all made of CMOS materials.


Figure: Difference between BJT & FET


The JFET is a three-terminal device with one terminal capable of controlling the current between the other two.

Construction of JFETs

The n-channel device will be the prominent device, just like npn transistor in the discussion of BJT.For p-channel device, the result will be obtained by changing the signs of some parameters.


The basic construction of n-channel JFET is shown in the figure.

The major part of the structure is the n-type of material, which forms the channel between the embedded layer of p-type material.

The top of the n-type of material is connected to a terminal called drain (D), whereas the lower end called source (S).


The two p-type of material are connected together and to the gate (G) terminal.

So the JFET has two p-n junctions under no-bias conditions.

And a depletion region is generated at each junction with no free carrier.

Also illustrated in the figure, it is the water analogy.


The water pressure can be likened to the applied voltage from drain to source (inside the JFET), which establishes a flow of water (electrons) from the spigot (source). For FET, the gate through an applied potential, controls the flow of current to the drain.The terminology, (D, G & S), is defined for electron flow.


Figure: JFET Construction


As shown in the figure, a positive voltage VDS ( =VDD)is applied across the channel.

Biasing: VGS = 0, VDS > 0

The gate is connected directly to the source to establish the condition VGS= 0.The electrons are drawn to the drain, leading to the current ID, which is also the same as IS.And the ID is solely limited by the resistance of the n-channel between D & S.


The depletion region is wider near the top of both p-type materials.The reason is that upper region is more reverse-biased than the lower part, thus a wider depletion region.

Also, the p-n junction is reverse-biased for the whole length of the channel, leading to no current in the gate terminal.IG = 0 is an important characteristic of JFET.


When VDS increasing, ID will also increase.

As VDS increases, the depletion regions will widen, causing reduction in the channel width and a higher resistance.

If VDS is increased to a level VP, where it appear that the two depletion regions would touch, a condition referred to as pinch-offwill result.


The level of VDS that causes pinch-off condition is called pinch-off voltage, denoted by VP.

Actually, under pinch-off condition, the current ID maintains a saturation level, defined as IDSS.IDSS is the maximum drain current for a JFET and is defined by the conditions VGS=0 and VDS > |VP|.


Figure: Biasing of JFET (VGS = 0, VDS > 0)


Figure: ID versus VDS for VGS = 0


For BJT, the characteristics is plotted to show the relationship between IC and VCEfor different levels of IB.

Biasing: VGS < 0

The VGS is the controlling voltage of JFET, just like IB for the BJT.

For FET, the characteristics is drawn to show the relationship between ID and VDSfor various levels of VGS.


For the n-channel device, VGS is made more and more negative from its VGS = 0 level.

Eventually, when VGS = -VP , it is sufficiently negative to establish a saturation level that is zero.

The saturation level of ID has been reduced as VGS is made more and more negative.


For all practical purpose, the device has been “turned off”.The VGS that results in ID = 0 is defined by VGS = VP , with VP being a negative voltage for n-channel and a positive voltage for p-channel JFETs.

The region to the right of the pinch-off locus is employed in linear amplifier and referred to as linear amplification region.


Figure: Biasing of JFET (VGS < 0)


Figure: JFET characteristics (VGS < 0)


The graphic symbols for the n-channel and p-channel JFETs are shown in the figure.

Symbols of JFET

Note that the arrow is pointing in for the n-channel device.This means that IG would flow if the p-njunction were forward-biased.For p-channel device, the only difference in the symbol is the direction of the arrow.


Figure: Symbols of JFET


Transfer Characteristics

IC= f(IB) = IB

For JFET, the relationship between the output and input quantities is not as simple as the that of BJT.

For BJT, the output current IC and input controlling current IB are related by constant , which is in the following equation form,


The relationship between the ID output and VGS is defined by Shockley’s equation:

2

1

P

GSDSSD V

VII

where the IDSS and VP are constants, and VGS controls the ID.

The squared term results in a nonlinear relationship between the ID output and VGS .


The transfer characteristics are properties of JFET itself and are unaffected by the network in which the device is used.Obviously, the transfer characteristics can be obtained by Shockley’s equation.It can also be obtained from the output drain characteristics. We draw both curves with a common

vertical scaling.


One is a plot of ID versus VDS , whereas the other is ID versus VGS .

Using the drain characteristics on the right of the vertical axis, we can draw a horizontal line from the saturation region of the curve to the ID axis.

The result current level for both graphs is IDSS .


The point of intersection on the ID versus VGS curve will be as shown since the vertical axis is defined as VGS = 0.

If a horizontal line is drawn from the VGS = -1V curve to the ID axis and then extended to the other axis, another point on the transfer curve can be located.

Continuing with VGS = -2V, -3V and VP (-4V), we can complete the transfer curve.


The transfer characteristics are a plot of an output current ID versus an input-controlling quantity, VGS . It’s a direct transfer from input to output variable.

The non-linearity of the curve is obvious from the different space between curves of different VGS level, also from the curves themselves.

It is the transfer curve of ID versus VGS that will receive extended use in the analysis of Chapter 7.


Shorthand Method

By Shockley’s equation, it’s precise but the calculation is time-consuming.

The transfer curves are useful and there are ways to plot it.

By the drain characteristics, it’s not easy since the drain characteristics should be known first.Here, a shorthand method will plot the curve in a efficient manner while maintaining an acceptable degree of accuracy.


The basic concept of the shorthand method is that the curve is sketched out with only several key points which are easy to obtain.

2

1

P

GSDSSD V

VII

If VGS = 0.5VP , then

First, from Shockley’s equation

22/1

P

PDSSD V

VII DSSI25.0


2

15.0

P

GSDSSDSS V

VII

If VGS = VP , then ID = 0.

If ID = 0.5IDSS , then

So we get VGS 0.3VP .

If VGS = 0, then ID = IDSS.

So the transfer curve can be sketched to a satisfactory level of accuracy.


Figure: Transfer curve by shorthand method


p-channel JFET

In this case, both VGS and VP will be positive.

For p-channel devices, Shockley’s equation can still be applied exactly as it appears.

The transfer characteristics will be the mirror image of the transfer curve obtained with an n-channel and the same limiting values.


Figure: Transfer curve of p-channel JFET


Summary of JFET

ID = IS

Important equations of JFET are as following: 2

1

P

GSDSSD V

VII

IG 0

And the condition IG 0 is often the starting point for the analysis of a JFET configuration.


MOSFET: Depletion-Type

A slab of p-type material forms substrate.

The basic construction of n-channel depletion-type MOSFET is shown in the figure.

The S & D are connected through metallic contacts to n-doped regions linked by an n-channel.

The G is also connected to a metal contact, but insulated from the n-channel by a silicon dioxide (SiO2) layer.


Some devices provide an additional terminal labeled SS. But in most cases, the substrate and source are connected.

From the above, the reason for the name of Metal Oxide Semiconductor FET is clear.

It is this layer of SiO2 that accounts for IG = 0 and the desirable high input impedance of the device.


Figure: n-Channel depletion-type MOSFET



The substrate and source are connected as a three-terminal device.

Shown in the figure, it is the configuration of n-channel depletion-type MOSFET.

A positive potential is applied to VDS.

An adjustable potential is applied to VGS.

When VGS < 0, the transfer curve is like that of n-channel JFET.


When VGS > 0, the drain current ID will increase at a rapid rate.So the positive VGS has “enhanced” the level of ID and leads to the enhancement region.

The region to the left of the vertical axis is the depletion region.

The Shockley’s equation is still be applicable for the depletion-type MOSFET.


Figure: Configuration of n-channel depletion-type MOSFET


For the plot of the transfer characteristics of an n-channel depletion-type MOSFET by shorthand method, please see Example 6.3.Shown in the figure, it’s the transfer curve of the p-channel depletion-type MOSFET.It is exactly the opposite of that of n-channel.

The VGS is positive for most of time and can also be negative. And when VGS = 0, ID = IDSS .


The graphic symbols for the n-channel and p-channel depletion-type MOSFET are shown in the figure.

Symbols of Depletion-Type MOSFET

The substrate is connected internally as a 3-terminal device.

The D & S is connected by channel through the vertical line in the symbol. The lack of a direct connection between Gand channel is shown.


Figure: Symbols of depletion-type MOSFET


MOSFET: Enhancement-Type

A slab of p-type material forms substrate.

Shown in the figure is the basic construction of n-channel enhancement-type MOSFET.

The S & D are connected through metallic contacts to n-doped regions .

The silicon dioxide (SiO2) layer is still present to isolate the gate platform from the region between D & S.


Note the absence of a channel between the two n-doped regions. This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs.

The characteristics of the enhancement-type MOSFET are quite different from anything obtained thus far. The transfer curve is NOT defined by Shockley’s equation.


Figure: n-Channel enhancement-type MOSFET



The substrate and source are connected as a three-terminal device.

Shown in the figure, it is the configuration of n-channel enhancement-type MOSFET.

A positive potential is applied to VDS.

When VGS = 0, the absence of an n-channel will result in a zero current.


This leads to a measurable current flow between D & S.

As VGS increases in magnitude, an induced n-type region is formed near the SiO2 layer.

The level of VGS that results in the significant increase in drain current ID is called the threshold voltage, VT .

The channel is enhanced by VGS > 0. This is the reason to the name of this type of MOSFET.


If we hold VGS constant and increase VDS , the ID will eventually reach a saturation level.

The drain characteristics is shown in the figure.For a fixed value of VT, the higher level of VGS , the greater is the saturation level for VDS.

This is the result of the narrower channel at the drain end of the induced channel.


For VGS less than VT , ID = 0.It is noticeable that the spacing between the level of VGS increases as the magnitude of VGS increases.This shows the nonlinear relationship between ID and VGS . Actually,

ID = k (VGS – VT)2

where k is a constant and can be obtained through VGS(on) and ID(on) from datasheet.


Furthermore, transfer curve can be obtained by setting it side by side with drain characteristics.

If a horizontal line is drawn from the VGS = +8V curve to the ID axis and then extended to the other axis, a point on the transfer curve can be located.

Continuing with other voltages of VGS , the transfer curve is obtained.


It must be remembered that ID is zero for VGS VT.

Also, the transfer curve is totally in the positive VGS region and does not rise until VGS = VT.

As to how to plot the transfer curve given k and VT for a particular MOSFET, see Figure 6.37 on page 330.


Figure: Channel formation in the n-channel enhancement-type MOSFET


Figure: Drain & transfer characteristics for n-channel enhancement-type MOSFET


p-Channel Enhancement-Type MOSFET

A slab of n-type material forms substrate.

The construction of p-channel enhancement-type MOSFET is exactly the reverse of that of n-channel one.

Those p-doped regions are under the drain and source connections.

All the voltage polarities and current directions are reversed.


The drain characteristics of p-channel enhancement-type MOSFET is shown in the figure.

The ID is increasing from increasingly negative values of VGS.

Also, ID is zero while |VGS| < VT.

The equation of ID discussed before is also applicable to p-channel devices.


The graphic symbols for the n-channel and p-channel enhancement-type MOSFET are shown in the figure.

Symbols of Enhancement-Type MOSFET

The substrate is connected internally as a 3-terminal device.

The dashed line between D & S reflects that a channel does not exist.The direction of arrow shows the channel type of the device.


Figure: Symbols of enhancement-type MOSFET


Introduction to FET

Summary of Chapter 6

Output characteristics: ID~VDS

For JFET & MOSFET

Transfer curves: ID~VGS

Shorthand method to sketch transfer curves

Graphical symbols

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