FET ( Field Effect Transistor)

1. Unipolar device i. e. operation depends on only one type of charge carriers (holes or electrons)

2. Voltage controlled Device (gate voltage controls drain current)3. Very high input impedance (109-1012 )4. Source and drain are interchangeable in most Low-frequency applications5. Low Voltage Low Current Operation is possible (Low-power consumption)6. Less Noisy as Compared to BJT7. No minority carrier storage (Turn off is faster) 8. Self limiting device9. Very small in size, occupies very small space in ICs10. Low voltage low current operation is possible in MOSFETS 11. Zero temperature drift of out put is possible.

Few important advantages of FET over conventional Transistors

JFET

MOSFET (IGFET)

n-Channel JFET

p-Channel JFET

Types of Field Effect Transistors (Classifications)

n-Channel EMOSFET

p-Channel EMOSFET

Enhancement MOSFET

Depletion MOSFET

n-Channel DMOSFET

p-Channel DMOSFET

FET

Figure: n-Channel JFET.

The Junction Field Effect Transistor (JFET)

Gate

Drain

Source

JFET SYMBOLS

n-channel JFET

Gate

Drain

Source

n-channel JFET(Offset-gate symbol)

Gate

Drain

Source

p-channel JFET

Figure: n-Channel JFET and Biasing Circuit.

Biasing the JFET

Figure: The nonconductive depletion region becomes broader with increased reverse bias.

(Note: The two gate regions of each FET are connected to each other.)

Operation of JFET at Various Gate Bias Potentials

P P +

-

DC Voltage Source

+

-+

-

N

N

Operation of a JFET

Gate

Drain

Source

Figure: n-Channel FET for vGS = 0.

Simple Operation and Break down of n-Channel JFET

Figure: If vDG exceeds the breakdown voltage VB, drain current increases rapidly.

Break Down Region

N-Channel JFET Characteristics and Breakdown

Figure: Transfer (or Mutual) Characteristics of n-Channel JFET

2

1

P

GSDSSDS V

VII

IDSS

VGS (off)=VP

Transfer (Mutual) Characteristics of n-Channel JFET

Biasing Circuits used for JFET

Fixed bias circuit Self bias circuit Potential Divider bias circuit

JFET (n-channel) Biasing Circuits

2

1

P

GSDSSDS V

VII

0, GGSGSGGGG IFixedVVRIV

DDSDDDS

P

GSDSSDS

RIVV

V

VII

and

12

S

GSDS

SDSGS

R

VI

RIV

0

For Self Bias Circuit

For Fixed Bias Circuit

Applying KVL to gate circuit we get

and

Where, Vp=VGS-off & IDSS is Short ckt. IDS

JFET Biasing Circuits Count…or Fixed Bias Ckt.

JFET Self (or Source) Bias Circuit

2

1 and

P

GSDSSDS V

VII

S

GS

P

GSDSS R

V

V

VI

2

1

021

2

S

GS

P

GS

P

GSDSS R

V

V

V

V

VI

This quadratic equation can be solved for VGS & IDS

The Potential (Voltage) Divider Bias

01

2

S

GSG

P

GSDSS R

VV

V

VI

DSGSI V gives equation quadratic this Solving and

A Simple CS Amplifier and Variation in IDS with Vgs

FET Amplifier Configurations

and Relationships:

'' ' m L

vi m L m L 'm L

'L d D L d D L SS L

i Th SS Thm

o d D d D SSm

i i ivs vi vi vi

s i s i s i

i i iI vi vi vi

L L L

P vi I vi I

CS CG CD

g RA -g R g R

1 g R

R r R R r R R R R

1Z R R R

g

1Z r R r R R

g

Z Z ZA A A A

R + Z R + Z R + Z

Z Z ZA A A A

R R R

A A A A A

vi I

Th 1 2

A A

where R = R R

VCC

RD

S

R2

RSS

Rs Ci

RL

Co

C2

vi vo

+

+

vs

+

_

_ _

io ii

Common Gate (CG) Amplifier

R1

D

G

Note: The biasing circuit is the same for each amp.

Rs Ci

RL

Co

CSS vi

vo

+

+

vs

+

_ _

_

io

ii

D

S

G

VDD

VDD

R1

RSS

RD

R2

Common Source (CS) Amplifier