PrecisionWafertoWaferPackagingUsingEutecticMetalBonding

Eutecticmetalbondingofwafers isused inadvancedMEMSpackagingand3Dintegrationtechnologies.Auniquefeatureofeutecticmetals is the melting of the solder like alloys that facilitate surface planarizationandprovideatolerancetosurfacetopographyandparticles.Advancedwaferlevelbondingusing2-3umthickmetallayersallowsprecisionalignmentpreventingtheaberrantviscousflowofthemetalandwaferslippage.

Alsointhisissue:

•C4NP NextGenerationWafer Bumping

IssueJuly. 2008

3 TheAgeof3DIntegration WilfriedBair

VicePresidentStrategicBusinessDevelopment,SUSSMicroTec

4 C4NPNextGenerationWaferBumping

Changingbumpingrequirementsdrivenby3DPackaging

KlausRuhmerandEmmettHughlett,SUSSMicroTec

6 PrecisionWafertoWaferPackagingUsingEutecticMetalBonding

ShariFarrens,Ph.D.andSumantSood,SUSSMicroTec

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index12ApplicationNotes

TipstoGetTheMostOutofDataViewer

SumantSood,SUSSMicroTec

13NewOfficeinUSA AntonWolejnik,ManagingDirector,

SUSSMicroTec

14Clif´sNotes

YouCanDefineThatExposureDoseInOneWafer!

CliffordJ.Hamel,SUSSMicroTec

18SUSSintheNews

20Tradeshows/Conferences

SUSSScoresFirstPlacefor10thYearasMaterialHandlingSupplier

Whencommercialwaferbonderswerefirst introduced to the industryin the early 90’s themain driver forthis new equipment type was thethen emerging MEMS technology.Pressure sensors and accelerome-ters for automotive applications setoff on its booming track providingthe first volume market opportunityforwaferbondinginlargequantities.Sincetheearly60’sanduntilthenthemechanicaluseofsiliconwasmainlylimitedtohighperformance,butlowvolumeapplicationsinaerospace.

Thesecondphase inwaferbon-ding is hallmarked by the growingdemand forMEMS devices in con-sumerelectronicsprovidingnewandunique product features to a vastmassofinsatiableconsumers.FromMEMSmicrophonestoaccelerome-tersbeingusedingameconsolesliketheNintendoWiiMEMScontinuedtopenetrateandinfluencetheappetiteof the consumer world. The latest“MEMSpublicitystunt”wasApple’sannouncementofthe2ndgenerationiPhone.Describingthelatestuniquefeatures of the iPhone the use of(MEMS) accelerometers and smartsensorswas prominently shown onthesupplier’swebsite.

Nowweare lookingat the thirdand - what we expect to be - thelargest surge in demand for waferbonding applications: We are ap-proaching theageof3D integrationof semiconductor devices. The en-visioned plan for the 3D integrationincludeslogic,memory,mixedsignal,image sensor and almost all othercommercially viable semiconductor

processes.Acommonlyusedcom-parison of 3D integration with realestate illustrates that when siliconspaceisatapremiumorcannotbemade larger theonly logicalconclu-sion is toexpandconstructions intothethirddimension.

Thus3D integration technologiesallowforanalternatepathtoMoore’slaw.This is nowcommonly referredtoas“MorethanMoore”andshowsthat the continuous scaling of tran-sistors by doubling approximatelyevery twoyearscanbepursuedbystackingdevices.

To address this newmarket op-portunity novel equipment approa-chesarerequiredtoprovidesubmi-cronalignmentaccuracyfor300mmwafers for the full product range oflithographyandwaferbondingtools.The product and process develop-ment teams within SUSS MicroTechaveworked on a new and uniquesetoftoolstoaddressthisupcomingchallenge. Millions of connectionsperstackeddevicewillbededicatedtotheuseofmetalbondprocesseswith alignment accuracies in ordertomatch the roadmapsof thecon-tinuously shrinking Through SiliconVia(TSV)sizesdowntointerconnectpitchesof3micronsandless.

Weareapproachingtheageof3Dintegration – in fact,weare alreadythere. And SUSS is right ahead tohelp our customers maximize theirwafer’s real estate. And maximizetheir profit. As their success is oursuccess.

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FullView

WilfriedBair

Vice President Strategic Business Development,

SUSS MicroTec

TheAgeof

3DIntegration

-C4NP–NextGenerationWaferBumping-

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Solderbumpswere inventedalmosthalf a century ago – an eternity in to-day’s world of micro electronics. Thetechnologyhasnotstoodstillandmanyadvances have been made in the ar-eas of solder and UBM (Under BumpMetallurgy)materials,solderdepositiontechniquesandequipmenttechnology.The basic principle however remainedunchanged: AUBM feature is createdonopenpadsofasemiconductorchip.AspecificvolumeofsolderisdepositedontopoftheUBM.Duringsubsequent

or in-situ reflow, the solder volumetransforms into a solder sphere dueto surface tension. That solder sphereisthenusedtoconnecttotheoutsideworld.Dependingonthetypeofpack-age, thatmayeitherbetoan interme-diate substrate (Flip Chip in PackageFCiP)ortotheboarditself(WaferLevelChipScalePackageWLCSP).

SUSS MicroTec has played a keyroleinWaferBumpingsinceitsinfancy.SUSSMaskAlignersandcoat/developclustersystemsareideallysuitedforthespecificrequirementsrelatedtopattern-ingtheUBMandtheresistandpolymerlayersforsubsequentmetaldeposition. Advanced packaging techniques in-cluding 3D packaging utilizing solderbumps as the primary interconnect-technology have been growing at animpressivepacesince themid1990’s.Everhigherinterconnectdensityneedscombinedwithincreasingperformancerequirementsarenolongeramatchforexistinginterconnecttechnologiessuchaswirebonding. Besidesthesolderbumpitselfhow-ever, the selection of the appropriateUBMorBLM (Ball LimitingMetallurgy)

materialshasshowntobetheprimarydriver for cost, reliability and electricalperformance. One key advantage of IBM’s C4NPis it’s capability to put bumps on es-sentially any UBMmaterial as long asitwetstosolder.Aspreviouslyreportedin this publication, C4NP also tacklesotherclassicalbumpingchallengesandenables environmentally friendly, low-cost,finepitchbumpingusingavarietyof lead-free solder alloys. With C4NP,purebulksolderismoltenandinjectedinto prefabricated glass molds. Thesemolds contain etched cavities mirror-ingthebumppatternofthewafer.Oncethemoldsarefilled,allsolderbumpsaretransferred inonestepontothewafer.Theprocessisquitesimpleanddoesn’tuseanyliquidflux.Thatmakesitalowcost,highyieldandfastcycletimeso-lution for bumpingwith awide varietyof highperformance lead free solders.Inaddition,thisprocessalsoeliminatestheneedfortoxicchemicalsneededforalternativebumpingtechniques–C4NPistrulya“GreenTechnology”.

Unlike other solder deposition pro-cesses, C4NP is independent of theUBMmaterials used. It offers full flex-

KlausRuhmer,Sales&MarketingC4NP,andEmmetHughlett,VPandBusinessUnitManagerC4NP,SUSSMicroTec

50um pitch, lead-free solder bumps (Courtesy of IBM)

-C4NP–NextGenerationWaferBumping-

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ibilitytocombinetheproperUBMwiththerightsolderalloytonotonlyfittheapplicationbutalsomeetcostandperfor-mancerequirementsofthefinalpackage.

Besides the need for lead-free, future solder bumps arealsodrivenby3Dpackagingand integration requirements.3D requires finepitchbumpingcapability toaccommodateveryhighinterconnectdensity.

EMMETTHUGHlETT

is Vice President and C4NP BusinessUnit Manager with SUSS MicroTec.EmmettholdsaPh.D. inelectricalen-gineering. Emmett‘s career includes24 years of engineering, sales andmanagement in the semiconductorequipment industry, with both Kulicke&Soffa IndustriesandSUSSMicroTecInc.

KlAUSRUHMER

Klaus Ruhmer has global Sales &Marketing responsibility forC4NPwaferbumpingtechnologyatSUSSMicroTec.He has been with SUSS since 1998startingoutasanApplicationsEngineerfor wafer bonding and lithography pro-ducts.Over theyears,hehasheldvari-ous technical and sales related posi-tions within SUSS. Prior to his currentposition, Klaus was responsible forStrategicAccountsinNorthAmerica.Klaus is a native Austrian and holds aBS in Electronics and Telecommunica-tionsTechnology.Heworkedinsoftwaredevelopment before he moved to theUSandjoinedthesemiconductorindus-tryin1996.

3D - Stacked chips using C4NP micro-bumps (Courtesy of IBM)

More information about SUSS MicroTec’swafer bumping and advanced packagingsolutionscanbefoundonwww.suss.com.

ABSTRACT Eutecticmetal bondingofwafers is used in advancedMEMS packaging and 3D integration technologies. Auniquefeatureofeutecticmetalsisthemeltingofthesolderlikealloysthatfacilitatesurfaceplanarizationandprovideatolerance to surface topography and particles.Often it isassumed that the alignment in eutecticmetal bonding iscompromisedfromtheliquidphasetransitionandprecisionalignmentisnotpossible.Thisisnottrueinadvancedwaferlevelbondingusing2-3umthickmetallayers.Precisioncon-trolofbondingforceandtemperaturepreventtheaberrantviscousflowofthemetalandpreventwaferslippage.Keywords:Eutecticbonding,waferbonding,MEMSpack-aging,Au-Sn,Au-Si,Cu-Sn.

INTRODUCTION Hermetic packaging of sensors hashistorically been achieved with glassfrit and anodic bonding techniques.However, these techniques are pres-entlylimitingscalingofdevicesandarenotappropriateforintegrationplansforCMOScompatibleMEMS. The widespread use of glass fritbonding can be attributed to its toler-ancetoparticlesandsurfacetopogra-phy,hermeticqualityof theseals, andinexpensiveprocessingcosts. Incom-parison, eutectic alloys provide betterhermeticity levels, are equally toleratetoroughnessandparticlesandenabledevicescalingandintegration.

EUTECTICREACTIONS A eutectic reaction is a triple pointinabinaryphasediagraminwhichtheliquidmetal solidifies into a solid alloywithoutgoingthroughatwophase,sol-id+ liquidequilibrium region.Becausethesolidificationisimmediatelyrealizedthe atomic rearrangements necessarytoestablish theequilibriumdistribution

of phases in the alloy is not fullyachieved.Themorphologyofthegrainswithin theeutectic solidare very smalland best described as “feather-like”.Thisfinegrainedinterdigitatedstructureis extremely rigid and strong. The finegrain size limits interdiffusion and cor-rosion. Figure 1 is the phase diagram forAu-Si.Thisphasediagram isaclassiceutectic example in which the purefcc Au phase is denoted as α andthe pure silicon diamond cubic phaseisβ. The diagram shows that there isverylittlemiscibilityineitherAuorSiand

alloysofAuandSiwillconsistofatwophasemixtureofαandβ.Whenanal-loyof2.85wtSi isheatedthesolidwillimmediately turn to liquidabove363Cavoidingboththeα+liquidandβ+liquidtwophaseregions.

MATERIAlSSYSTEMS There are several alloys choicesbased on Cu or Au eutectic metallur-gies.Table1showsthecommonlyusedalloysalongwiththeeutecticcomposi-tions and the eutectic temperature.All of these alloys have been used inMEMS packaging, or optical MEMS.

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6-PrecisionWaferToWaferPackagingUsingEutecticMetalBonding-

PRECISIONWAFERTOWAFERPACKAGINGUSINGEUTECTICMETAlBONDINGShariFarrens,Ph.D.,ChiefScientist,andCo-AuthorSumantSood,SrApplicationEngineer,SUSSMicroTec

Figure 1:Au-Si Binary Phase Diagram

Table 1: Eutectic Alloys used in MEMS Packaging

Alloy EutecticTemperature

EutecticComposition

Al-Ge 419C 49/51wt%

Au-Ge 361C 28/72wt%

Au-In 156C 1/99wt%

Au-Si 363C 97/3wt%

Au-Sn 280C 20/80wt%

Cu-Sn 231C 1/99wt%

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TheAl-Gesystemisalsoapplicabletoternary eutectic reactions between AlandSiGelayersbecauseAlformsabi-naryeutecticreactionwithbothSiandGe. This system is particularlyCMOSfriendly.

DEPOSITIONTECHNIQUES Therearetwofundamentalmethodsfor creating a eutectic seal. The firstmethod involves deposition of purematerials which then are diffused to-gether until the eutectic compositionisreached.Thentheeutecticalloycanbemeltedandreflowedtoachievetheseal.Bycontrastthebinaryalloycanbedepositedas a single layer already atthecompositionnecessary toachieveaeutecticreaction.

Eutecticalloyscanbeplated, sput-tered or evaporated onto the sub-strates. There are several sourcesfor alloy sputter targets that are ide-allysuitedtothin layerdepositionandmanyofthealloyscanbeelectroplatedateutecticcompositions.Becausethequality of the electrical connections,as well as the reaction kinetics, areadversely affected by impurities thedeposition should be done as cleanas possible. Incorporation of oxygenandothergasesinthethinfilmsduringdepositioncanlowerthediffusionratesdramaticallyaswill impuritiesfromtheelectroplatingbath.

Itisnecessarytouseadhesionlayerswhen using metal seal technologies.The semiconductor surfaces or glasssurfacesshouldbeproperlycleanedtoremoveanypreviousphotoresistlayersorothermaterials remaining fromear-lier etchingor patterning steps.Stan-dard substrate cleaningmethods be-foremetaldepositionincludestandardRCA1 and RCA2 or Piranha (sulfuricacid, water and hydrogen peroxide).To removeorganicsor tocleanmetalsurfaces dry plasma treatments havebeeneffective.

Typicaladhesion layers includeTiW,TiN,W,Cr,Niandvarywith thesub-strateused.Theadhesionlayerisveryimportanttoensurethatthestrengthofthe interface isnot limitedby thinfilmdelamination.

SURFACEPREPARATION The diffusion of metals as well asthe solidificationof eutectic phases isinhibited by contamination and oxidelayers. Inmostfabricationfacilitiesthetimingofthedevicewaferandcapwa-fer process are such that one or theothersetofsubstratesmaybequeuedup for bonding before the other. Thisdelaytimebetweendepositionofmetallayers and actual bonding can leadto surface oxidation. To achieve highyields and reproducible lots, point ofuse surface preparation is advised tomakesure thatmetal layersarecleanjustpriortobonding. Based on experience in die-to-dieandC4NPadvancedbumpingtools ithasbeenestablished that formicacidvaporcleaningisveryeffectiveformosteutectic alloys, low temperature sol-ders,andaluminumaswellascopperintheremovalofsurfaceoxides.[2,3] Vaporphasecleaningcanbeaccom-plishedinbatchprocessingorasaonewaferatatime,pointofuse,cleaning.Inbothcasesthewafer(s)areplacedinaclosedchamberorcleaningstation. The formic acid vapors are intro-ducedandthesurfacesoxidesarere-moved.ThewafersarethenrinsedinDIwaterandspundryinthecleaningsta-tion. In automated bond cluster toolssuch as theSUSSMicroTecABC200thisisdonewithoneortwowaferssi-multaneouslyforincreasedthroughput.The formic acid treatment passivatesthesurfaceofthemetalsandpreventsreoxidation during the rinse, dry andalignmentprocessthatfollows. Figure2showsacoppersurfacethatwascleanedwiththeformicacidvapor,rinsed with DI megasonic water and

spundry.Then thewaferwasheatedto 400C to see if reoxidation wouldoccur. Itdoesnotand thismethod isusedforCu-Cubondingin3Dintegra-tiontechnology.

Figure 3:Position of optics for wafer to wafer bondalignment.

Figure 2:Formic acid vapor cleaned Cu surface before and after heating to 400 C.

BottomSideAlignmentwithTransparentWafer

BottomSideAlignmentwithDigitizedImage

IRAlignment

Inter-SubstrateAlignment

AlIGNMENTTECHNIQUES Alignment techniquesare separatedintomethodswhichaligntolivetargetimagesandthosethatusestoredimagealignment.During live imagealignmentthe image of both the device and thecap wafer alignment keys are viewedsimultaneously.Thishastheadvantagethat throughout thealignmentprocessanyshiftsthatmightoccurbecauseofvibration,clampingorothermechanicalmotionscanbeobservedandcorrect-ed.Withstoredimagesoncetheposi-tion of the initial fiducial is found andcaptured (digitally stored to memory)thewafer isclampedintopositionandpresumed to be stationary during allremaining teps.However, this can notbeverifiedsincethetargetimageisnolongerinthefieldofview. Theoptionsforalignmenttechniquesinclude BSA (backside alignment)with transparent substrates, BSAwithopaque substrates, IR (infrared) align-ment, and ISA (intersubstrate) align-ment. Figure 3 is a schematic of theobjective and substrate locations foreachtechnique.TheBASw/transpar-entsubstratesandtheIRmethodalign

to live images.ISAalsoalignstoa liveimage however, after bonding themi-croscopescannotaccesstheinterfaceagainandarenotusefulforpostbondanalysis.TheBSAmethodcanbeusedto verify the post bond alignment ac-curacy because it is possible to “lookthrough” the transparent substrate atanytimeduringthealignandbondpro-cess.ThisisalsotruefortheIRmethodwhenever themetal layers do not ob-scurethefieldofviewofthetargetandthewafershavearesistivitygreaterthan0.01Ohm-cm(forsilicon).

AlIGNMENTTARGETS Alignment targets play an importantrole in achieving good quality bondalignment. Inadditionsometargetde-signsalsofacilitateprocesscontrolandmonitoring,Forexample,thealignmentkeyshown in figure4containsbothastandardcrossandboxstylealignmentkeyaswellasgraduatedscalesalongthex-andy-axes.Duringprocessde-velopment the scales can be used toaccurately determine systematic shiftsand rotation that may occur duringthe alignment or bonding steps. Notethatthegraduatedscalesareusedforanalysis and not used for alignment.Thestandardmaleandfemalekeysareusedbytheoperatorortheimagerec-ognitionsystemforoverlayalignment. Figure 5 shows an image of one ofthe keys after bonding. In this exam-ple the x-axis is perfectly aligned andthe center of the graduated scales isaligned.Onthey-axisverniersthepat-ternisshiftedslightlyupwardsandthefirsthashmarkisaligned.Ifthiswerea0.5 μm vernier then themeasurementwould implythatatmostthemisalign-mentinthisexampleis+/-0μminxand+0.5μminy.Vernierscanbescaledtogive 0.1, 0.2 or 0.5μm resolution de-pending upon the desired precisionneeded.

BONDINGTECHNIQUESANDKNOW-HOW Bonding of eutectic alloys requiresgoodcontroloverthetemperatureandpressureprofiles in thebonder.This isdirectlyrelatedtothemeltingofthealloy.The viscosity of the alloy is related tothetemperature.Asthemeltbecomeshotter the molten metal is more fluid.With increased fluidity come the pro-pensityofthewaferstosliderelativetoone another and loose alignment ac-curacy. Anotherreasonthattemperaturecon-trolisessentialinvolvesensuringthatallthe locationson thewaferaremelted.ManyMEMSstructuresarefragileandcaremustbetakenthatwhentheap-plied force isusedthe interface issoftandfluid.Ifanyareascontainsolidmet-al thiswill not be flattenedby the ap-pliedforceandthestressmaydamageunderlyingorsurroundingstructures.

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Figure 4: Male and female align-ment keys with graduate xand y- axis scales.

Figure 5: Post bond IR image of male and femalealignment keys in bonded silicon wafers.

Figure 6: Recipe for Au-Sn eutectic bonding.

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Equallyimportantistheuniformityoftheappliedforceandtheparallelismofthebondchucks to thesurfaceof thewafers. If the force is not applied di-rectlyperpendiculartotheinterfacethemoltenalloywillsqueezeintounwantedareas and distortion of the bond lineswillresult.Inextremecasesthemoltenalloycanbeextrudedintothecavityordiestructureandpreventdevice func-tionality. In many applications the parts thatarebeingbondedhavecavities.Toen-surethatthecavitiesarefilledwiththeproper atmosphere, separation flagsorspacersareusedtomaintainagapbetween upper and lower substrates.Spacersarethinshimsofmetalthatareplacedbetweenthewafersatthreelo-cations. Thespacers range from50-100μminthicknessandonlypenetratetheout-ermost2-3mmofthewaferperimeters.Thespacersallowgasestobepurgedtoandfromthecavitiesthroughouttheinterfaceviathevacuumpumpsystemin thebonder.Once theproper atmo-sphereisestablishedwithinthecavities,thespacersmustbe removedprior tobringing thewafers in contact for finalannealing. Removal of spacers hasbeenidentifiedasasourceofmechani-calmotion that can lead to shifting ofthesubstrates. Earlygenerationbondersusedanallatonceremovalmethodologytoretractthespacers.Thiswasaccomplishedbyusingacenterpintocomedownfromthe upper pressure plate and pressthewafers together in thecenter.Thisfixedthepositionofwaferstogether inthecenteronly.Thentheclampswereliftedandtheflagspulledoutoneata

timefromthewaferedge.Latergenera-tionequipmentenabledtheflagstobepulledoneatatime,howeverafunda-mentalproblemstillexisted;ifthewaferstack ispinnedonly inthecenter it isstillfreetorotateaboutthez-axis. In addition many times the centerpincausesharmtodelicatediceinthecenterofthewafer.Thesolutionisnewcontrolsoftwarethatallowsforonlyoneclamptobeliftedleavingtheothertwoclampsavailable toconfine thewafersin two locationsalong theedgeof thewaferstack.Afterthefirstclampisliftedthe spacer is removed and the clampis put back down on the stack. Thenthenextclamplocationisreleasedstillleavingtwolocationspinnedinposition.This improved flag retraction methodhasbeenshown to reduceshiftingbyseventimes.[4]Thismethod,calledse-quentialclampremovalisonlypossiblewhen there are at least three clampmechanismsonthebondfixture. The bond recipe itself will resemblethe example shown in figure 6. Theremaybesomepumpandpurgecyclesintheinitialstagesoftherecipetoex-changetheatmosphereinsidethebondchamberwithonethatistypically inertor reducing. Forming gas, hydrogenmixed with either nitrogen, argon orheliumhasbeenshowntodramaticallyimproveyieldbysuppressingoxidationandmetal film contamination. The at-mospherealsoaidsinheattransferandispreferredtovacuumannealingunlessthedevicerequiresvacuumsealing. Thetemperatureaswellastheforceshouldberampedinacontrolledfash-ion. Force is used to establish physi-calcontractbetween thesurfaces.Bygradually applying the force themetalwillflowbetweenthewafersandremainconfinedtothepatternsealringarea.

The reaction time is generally shortforeutecticbondswhenthereactionisdrivenfrommeltinganalloylayer.Whenthediffusionreactionisusedtherecipemay be lengthened by several min-utes.Once thematerial is in the liquidstateonlyafewminutesarerequiredtoequilibrate thecompositionand reflowthe interface.Coolingcanbedoneasrapidly as stress conditions in the de-viceorsamplewillallow.

APPlICATIONSANDRESUlTS Eutecticbondsareusedforavarietyof inertia devices such as accelerom-eters, gyroscopes, and applicationssuchasRFswitchesandresonators.Arecentpublicationpresenteda lengthystudy of Au-Si eutectic bonded pres-suresensors.[5,6]Itisraretofindpub-lishedhermeticitydataandthesetestsusedencapsulatedpiranigaugeswithinthedevicetomonitorthe leakratesofthesealsovermorethanoneyear.Thestudy included several eutectic alloysand data in Figure 7 is for a diffusedAu-Sieutecticbondshowingexcellentresults. Several examples of successfullybonded wafers are shown in figure8-11.Figure8showsanexampleofaAu-Sieutecticbondon6”MEMSwa-fers.ThisparticularexamplewasdrivenfromadiffusionreactionandSonoscanacousticimagingfoundnovoidswithinthesealringarea.Theblueinthisfigureindicatesavoidfreebondline.

Figure 8:Sonoscan image of 6” wafers bonded using Au-Si diffusion based Eutectic bonds.

Figure 7:Hermeticity results from 14 Au-Si eutec- tic sealed devices from reference 5 and 6.

Another feature to point out is thatthe edge of the wafer is sealed. Thisisvery important ifacoustic imaging isusedforvoiddetectionbecausewhentheedgesofthewaferarenotsealed,capillary action will draw fluid into theareasbetweenthedieandcomplicatedpostbondprocessflows. Goldtineutecticshavebeenthemost

requestedalloysysteminthedemofa-cilitiesofSussMicroTec.Showninfigure9isanexampleoftheIRandSonoscanacoustic imageofthebonded200mmwafers.Thedicewereuniformlybondedatalllocationswithinthewafer. The gold tin system has also beenusedonceramicpackagesasshowninFigure11.Duetothesurfacewaviness

oftheceramicsubstratetheconformalnature of a eutectic sealing technol-ogywasadesiredbenefitofthisbondmethod. The last example is a Au to SiGeeutectic bond. Whenever a eutecticformsbetweentwobinaryphasesitwillbe possible to forma ternary eutecticphase as well if the remaining binarysystem also has complete solubilityor exhibits a eutectic reaction. In thecaseofAuasimpleeutecticexistsbe-tweenAu-Siat363Cand2.65wt%Siand between Au-Ge at 419C and 28at%Ge.Meanwhile,SiandGearecom-pletelymiscible.Infigure11weshowa200mmwaferbondedbyeutecticalloyformationbetweenAuandaSiGealloylayeronsiliconsubstrates.Thisprocesswascompletedat420C. Because eutectic alloys melt andare therefore, self planarizing there isnoneedtoCMP(chemicalmechanicalpolishing)themetallayers.Thewettingbehavior of the alloy to its adhesionlayerwillassistwithconfinementofthemoltenflowaslongastheforceisap-plied gradually. This eliminates one ofthe costly processes normally associ-atedwithmetalbonds.

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Figure 9:The IR and acoustic image of 200mm wafers bonded using Au-Sn eutectic solder.

Figure 10: Au to SiGe eutectic bond on 200mm silicon wafer. Acoustic image shows no voids or unbonded areas.

CONClUSIONS EutecticalloybondingiswidelyusedinadvancedpackagingandMEMSde-vicefabricationforhermeticseals.Theprocessingtemperaturesofthevariousalloy choices are below 400C (exceptthe Au-Ge system) and the selfpla-narizationofthemoltenmetalmakethistypeofbondaverysurfacetopographytolerant method. Alignment methodscan include IR, intersubstrate align-ment,orbacksidealignment.Theaccu-racyofthealignedfeaturesdependsonthechoiceofalignmentmethod,qualityof the targetsand thicknessof theal-loylayer.However,formetallayers1μmthick or less alignment accuracies of~2μmcanbeexpected. Itisexpectedthateutecticalloyswillgraduallyreplacesomeoftheglassfritsealingtechnologiesinapplicationsthatrequiredevicescalingtosmallerpack-ages and for integrated devices. Themethods and materials systems de-scribedhere shouldgive some insightintowhatthepossibilitiescaninclude.

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REFERENCES

1. ThaddeusB.Massalski,BinaryAlloyPhaseDiagrams,2ndEdition,ASMInternational,MaterialsPark,Ohio,Vol.1,1990,p.434.

2. EricLaine,et.al.,“C4NP–ReliabilityandYieldDataforLeadFreeWaferBumping”,IMAPSDevicePackagingConfe-rence,DoubletreeHotel,Scottsdale,March17,2007.

3. K.Ruhmeretal.,“C4NP:Lead-FreeandLowCostSolderBumpingTechnologyforFlipChipandWLCSP”,IWLPCPanPacificConferenceOct.2006,WyndhamHotel,SanJose,CA.

4. S.Farrens,“ProcessingSolutionsforReproducibleSubmi-cron3DIntegration”,3DArchitecturesforSemiconductorIntegrationandPackagingAccessingTechnologicalDeve-lopments,Applications,andKeyEnablers,Oct22-24,2007,HyattRegencySanFranciscoAirportHotel,Burlingame,California.Proceedingstobepublished.

5. MeiY,LahijiGR,NajafiK2002”ARobustgold-siliconeutecticwaferbondingtechnologyforvacuumpackaging”,Solid-StateSensor,ActuatorandMicrosystemWorkshop,HiltonHead,SC,USA,pp.772-4.

6. MitchellJS,LahijiGR,NajafiK.,“Reliabilityandcharacte-rizationofmicropackagesinawaferlevelAu-Sieutecticvacuumbondingprocess”,Proc.,ASME/PacificRimTech.Conf.ExhibitIntegrationandPackagingofMEMS,NEMS,andElectronicSystems,InterPack05,SanFrancisco,CA,July2005

Figure 11:Ceramic packaging using Au-Sn eutectic bonds

DR.SHARIFARRENSistheinventorofplasmaactivatedsubstratebondingandholdssev-eralpatentsforthisenablingtech-nology.Dr. Farrens has authoredand co-authored over 100 pub-lications on SOI, wafer bondingand nano-technology. With over15yearsofhands-on,worldwideexperience in academia and in-dustry she is considered an ex-pertonMEMSandwafertowaferbondingtechnologies.

SUMANTSOODis the Senior Applications Engi-neer forWaferBondersatSUSSMicrotec Inc.. His recent experi-ence includes development ofplasma enhancedwafer bondingprocesses for SOI and strainedsilicononInsulator(sSOI)applica-tions. Sumant has authored andco-authoredmorethan15papersin wafer bonding, SOI, strainedsilicon and related areas. He re-ceived his B.Tech in ElectricalEngineering from Punjab Techni-calUniversity,IndiaandMSinMi-croelectronics from University ofCentralFlorida.

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The graphical user interface for allSUSS bonder products is called theProcess Control Program (PCP) Navi-gator.Oneof the lesser usedcompo-nents available in this navigator is the“DataViewer”. It isaccessedbyclick-ing the Navigator Data button. The

Data Viewer graphically displays thecontentsofselectedprocessdatafilesand allows customization and exportofprocessdata.Thisnotewilldiscussthecommonandnot-so-commonbuthelpful functions available in the DataViewer.

Whenthedataviewerisfirstopened,all buttons are disabled (grayed out)with the exception of ‘Open Datafile’and ‘Exit’. Importing a data file to theviewerenablestheremainingbuttons.

CONFIGURINGDATAVIEW The Chart configuration window(Figure 1) is accessed by clicking the‘Configure Chart’button.Thiswindowenables the user to plot the ‘actual’and‘target’valuesofselectedprocessdataitemsvs.thebondrecipetime.Inaddition to common bonding processparameters(topandbottomtooltemp,chamber pressure and tool force), theusercanalsoplototherdataitemssuchasRecipeSteps(RcpStep)andRecipeAction (RcpAction). RcpStep providesaneasywaytoviewtheactualprocesstime spent at each step of the bondprocessandcanbeusedtorefinethebond recipe and improve overall pro-cessthroughput.Theactualvalue(X,Yvalue)ofanyplottedparametercanbeviewedonthechartbydirectlyclickingthelineontheplotforthatparameter.

EDITINGCHARTPROPERTIES The ‘Editing DataChart’ (Figure 2)windowisaccessedbyclickingonthechart properties button in the ‘Chart configuration’window(Figure1)anden-ableseasycustomizationofchartdata.All general chart edit functions suchasdataformats,axistitlesandscales,andallplottedparameterscanbeed-itedbyaccessingtheChartandSeriestabs in ‘Editing DataChart’ window.The axis for any plotted data itemscan be changed by first selecting therelevantdata series in the ‘Series’ taband then selecting the horizontal andverticalaxis inthe‘General’subtab. Inaddition,theuserhasanoptiontoplotthechart in3Dbyaccessing the ‘3D’subtabunderthe‘chart’tab.

Figure 1:Data Viewer Plot and Chart Configuration Window

Figure 2:Data Export

Application NotesTipsToGetThe

MostOutOfDataViewer

The‘Editing DataChart’windowalsohasextrachartcustomizationtoolsthatcan be accessed by clicking on the

‘tools’ tab (Figure 3). These tools al-lowtheusertoaddextralegends,linesandtexttotheplottedchartwithouttheneedtoexportandcustomizethechartinanexternalapplication.

ExPORTINGANDPRINTINGDATA Data export functionality is availablefromtheExporttabonthe‘Editing Da-taChart’windowasshowninFigure2.Data Viewer allows export of processdatainthefollowingformats: (a) Common data types (XML, HTML,Excelordelimitedtext). (b) as an image (windows metafile orbitmap) (c) nativeformatUsingthefunctionsoftheDataViewerdiscussedabovewillenabletheSUSSbonder users to get the most out oftheirDataViewer.

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Figure 3:Chart Tools Gallery

SUMANTSOODis the Senior Applications En-gineer for Wafer Bonders atSUSSMicrotecInc..Hisrecentexperience includes devel-opmentofplasmaenhancedwaferbondingprocessesforSOIandstrainedsilicononInsulator(sSOI)applications.Sumanthasauthoredandco-authoredmorethan15pa-pers inwaferbonding,SOI, strained siliconand relatedareas. He received his B.Tech in Electrical EngineeringfromPunjabTechnicalUniversity,IndiaandMSinMicro-electronicsfromUniversityofCentralFlorida.

-TipsToGetTheMostOutOfDataViewer-

IntroducingtheCertifiedRemanufacturedlineofSUSSqualityproductsnowintheUnitedStates.

SUSS Remanufactured and Certi-fiedtoolsarecompletelyreconditionedbyexperttechnicianswhousegenuinespare parts and state-of-the-art test-ing methods to assure 100% confor-mity to original specifications. Toolsare fully upgraded to meet today’ssafety standards, include current andlicensed system software, warrantyandmayoffertechnologynotavailablewhentheoriginalequipmentwassold. SUSS MicroTec opened its NorthAmerican Remanufacturing divisionon May 5 in a location only a few

miles from the SUSS Wafer Bonderproduction facility in Waterbury, Ver-mont. The new site and staff will fo-cus primarily on the remanufacturedequipment business, such as locat-ing and repurchasingSUSS tools andsupporting North American sales ofremanufactured SUSS equipment. Technicalsupportwillalsoplayanim-portant role for thisofficeenabling theSUSS service teams to focus on cur-rent models of equipment platforms.TheRemandivisionwillprovidethefullspectrumofsupportonallremanufac-turedandoldermodelsofSUSStools. The site will be managed by GlennWalker in his function as BusinessManager Remanufactured Equip-ment North America. Glenn worksclosely with the SUSS ReMan head-quarter in Oberschleissheim, Ger-many and SUSS MicroTec Inc. inWaterbury,Vermont.

Though spare parts for remanufac-tured and older tools will be providedby the German site, North Americancustomers will be working with thenewoffice inWaterbury toget aquo-tation for theparts theyneed.Theof-fices will also support each other intool location and sales worldwide. NorthAmericancustomersinterestedin purchasing SUSS Remanufacturedand Certified Equipment should con-tacttheirlocalSalesAccountManager.Ifyouarenotsurewhothat is,pleasevisitwww.suss.comoremailinfo@suss.com. Customerswho need technicalsupport on older SUSS equipmentshould contact our Technical SupportHotline at 1-800-TOP-SUSS(867-7877), please give theattendant the model and se-rial number of your tool andyouwillbedirectedtothespecialistforthatpieceofequipment. Customerswishing to trade-inor sell a pieceofolder equipmentcan either contact theirlocalSalesAccountMan-agerorGlennWalkeratglenn.walker@suss.com.

NewOfficeinUSA

Anton Wolejnik, ManagingDirector,SUSSMicroTecRemanGmbH

Remanufactured MABA 6

INTRODUCTION There are many ways to determinethebestexposuredoseforaSUSS1Xfullfieldaligner.Manytimesitseemsea-siesttojustrunagroupofwaferseachat a different exposure time. Thisme-thodhowevertakestimeandresourceswhichaddscosttoprocess.Therearesome very simple and easy methodstoreducethecostofanevaluationyetstillprovidethemostinformationattheleastcost. Onemethodwhichmaybeusedforthin resistfilms involves theuseof theSUSSexposure testdialwhile these-condmethod uses a simple low coststepwedge.

Thissecondmethodalsomakesshortwork of those thick film exposures ta-kingsixtyormoreseconds.Eachofthe-semethodswillbediscussedindetail.

SUSSExPOSUREDIAl Thisunit iscomprisedoftwopiecesof metal held together in the centerslightly larger thanthewafer tobeex-posed.Thelowerpiecehassixcutoutsintheshapeofawedgewhilethetoppiecehasonewedgeshapedcutout.Thetoppiecemayberotatedaboutthecenter toallow light topass thrueachindividualwedge,Figure1forexample,shows a test dialwith top piece rota-tedbetween twowedges.Thebeautyof this method is that you can do allof your testing with themask of yourchoice, no special mask is required.Youmaydouptosixexposuresononewaferwitheachexposureatadifferenttimeorcondition.Forexample,suppo-seyouwishtoevaluatethechangesinsidewallprofileunderdifferentexposureconditionssuchasproximitygapofsay0,15,20,40,80,160μm.Yousimplyplacethedialontopofthemaskofyourchoice, set the wedge position, cyclethewafer thru the tool then rotate thedial and repeat until all six conditionsarecompleted.Younowhaveonewa-ferwhichhasbeenexposedwithyourmaskpatternatsixdifferentconditions!Ifonlytheexposuretimeistobechan-gedSUSShasaspecial featureon itsaligner called ‘exposure test mode’.Usingthemaskofyourchoicewiththis

mode a wafer is brought to exposuregapandwill remain there forasmanyexposurecyclesasyouwish.Thusyousimple place the exposure dial at onewedge position and cycle the shutterforthedesiredtime.Rotatethewedgetothenextposition,changetheexpo-sure timeandcycle the shutter again.This is repeated for each wedge untilyouhaveobtained your six exposuresand unloaded the wafer. Develop theimagesandyounowhavesixexposureconditionsononewafer. For thin films this procedure worksverynicelyandtakesaveryshorttime,however,withthickerfilmsrequiringsix-tyormoresecondseachthiscouldbeaverytimeconsumingoperation.The-reisnodoubtthatitwillwork,itisjustthat itwill take sucha very long time.Theremustbea fasterway todo thisandthereis!

THESTEPWEDGE Whentimeisoftheessenceandyoucan do only one exposure cycle thenyouneedtouseasteptabletwhichhasbeen used in the printing industry formanyyears.Itisbasicallyastripofpla-sticwithdifferentlevelsoftransmissionsimilartothatshowninFigure2whereamountof lightpassingthruthetabletwill be reduced in steps from zero toone-hundredpercent. Innormalusethetabletisplacedontheobjecttobeexposedi.e.yourmaskthentheshutteristurnedonforagiventime thusproducingasmanyexposu-

-Clif‘sNotes-YouCanDefineThatExposureDoseInOneWafer!-

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YouCanDefineThatExposureDose

InOneWafer!

Figure 1: SUSS Exposure Test Dial View

re levelson thesubstrateas therearesteps on the tablet. Thus if you needtoevaluateyourmaskpatternwithsaythree exposure modes, proximity, softandhardcontact,asa functionofex-posuredoseyouonlyneedthreesub-stratestocompletethetest! ForsemiconductorusetenexposurestepsisfartoomanytobepracticalsoSUSShasmodifiedthesteptablet1tohaveatmostfourtosixstepssimilartothoseshowninFigure3.Thefoursteptablethasbeendefinedintheshapeofapiechartsimilartotheexposuretestdial.Thesesteptabletswillallowforaninvestigation of exposures from aboutfiftytoone-hundredpercentoftheinci-dentexposureintensity. Typicalchanges inexposure intensi-tyforeachsteptablettypethatSUSSusesareshownTable1.

WHATExPOSURETIME? Amostimportantquestionishowtodefinetheproperexposurestepstobeusedwiththetestdialorthesteptablet.Inmostcasesitisquiteeasyandmay

requireyoutouseatmosttwowafersto find the correct range. First, mostthin resists of say one to fivemicronsthicknesswill requireabout75mj/cm²dosepermicronofresist.Thus,simplymultiply thisvalue times thefilm thick-nessanddividebythelightintensitytoobtainthenominalexposuretime.Thelight intensitywill bemeasured as thebroad band ultraviolet light covering arange between 330 to 450 microns,typically theSUSS405nmprobe.Thisnominal exposure timewill bemidwaybetweenthelowestandhighestexpo-suretimestobeusedwiththetestdialorsteptablets.AsamplecalculationforatypicalthinandthickfilmisshowninTable2belowusingthepercenttrans-missionvaluesfromTable1.Thegoalistoinsurethatthestepsusedwillcoverarangeofaboutfiftypercentofthetotalexposure time. The stepswill typicallybeabouttwentypercentofthenominalexposure.Smallerstepshavenotpro-ventobeanymoreusefulwhile largerstepsmaybeusedifthecharacteristicsoftheresistarenotwellknown.

-Clif‘sNotes-YouCanDefineThatExposureDoseInOneWafer!-

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Figure 3: SUSS Step Tablet

Figure 2: Transmission Step Tablet

StepWedge,%Trans

Pie Steps

None 100 % 100 %

1 81 % 81 %

2 66 % 68 %

3 54 % 63 %

4 - 53 %

5 - 46 %

Table 1: Typical Light Intensity By Tablet Type

SUMMARY In summary, using one of two pos-sible methods on the SUSS 1x fieldaligneritispossibletoevaluatetheex-posuredoseon yourmaskusingonlyonewafer,foranexampleseeFigure4.UsingtheSUSSexposuretestdialalsoallowsyoutoevaluateuptosixexposu-remodesonasinglewafer.

-Clif‘sNotes-YouCanDefineThatExposureDoseInOneWafer!-

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ResistFilm

Thin Thick Units

Film Thickness 1.2 20 µm

Dose per Micron of Resist 75 55 mj/cm²/µm

Nominal Dose 90 1100 mj/cm²

UV Light Intensity 70 mw/cm²

Nominal Exposure Time 1.3 15.7 seconds

UsingPercentTransmissionfromTable1

No Step 1.9 24.9 seconds

1 1.6 20.2 seconds

2 1.3 17.0 seconds

3 1.1 15.7 seconds

4 - 13.2 seconds

5 - 11.5 seconds

Table 2: Calculating the Steps

Figure 4: Step Tablet Image Size Evaluation AZ50XT, 50µm Thickness, Copper Plate, Design to Substrate Image is approx +13µm.

ClIFFHAMElis theprincipleapplicationsengineeratSUSSMicroTec,Inc.forlithographyprocessesinvolvingfullfieldmaskalig-nersandautomatedclustercoatingequipment.OverthelasttenyearsatSUSShehasco-authoredseveralpapersin thefieldof thickresistprocessesandprocessoptimi-zation.Hehasover26yearsofBEOLprocessandmaskfabricationexperienceatIBMwherehewastheprincipleengineerandinventorforliftoffprocessdevelopment.HereceivedhisBSinchemicalengineeringatTrinityCollegeofVermont.

Maximize Your Wafer’s Real EstateYour success in the third dimension relies on innovative technology. SUSS technology is leading the way

in the advancement of 3D applications with innovative equipment solutions enabling the development of

production-ready 3D processes. Our commitment to superior performance will prepare your business for

the next dimension.

www.suss.com E-Mail: info@suss.com

+

+

+

+

3D Lithography Wafer-to-Wafer-Bonding

Micro-Bumping Thin Wafer Handling

Scaling in 3 Dimensions

suss_semi08_7.875x10.5.indd 1 6/9/2008 5:15:00 PM

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SUSSintheNews

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Here’sasummaryofourrecentpressreleases.Toreadtheentirepressrelease,pleasevisitwww.suss.com/about_suss/latest_news

Jan 14, 2008 . SUSSMicroTec litho-graphyQualityManagementNowCer-tifiedAccordingtoISO9001:2000SUSS MicroTec Lithography GmbHnow holds the globally recognizedISO9001 certification for having es-tablished a high level process- andsystem-orientedqualitymanagement(QM)basedonISO9001qualitystan-dards. The certificate is evidence ofSUSS MicroTec Lithography’s com-mitment to provide consistent high-qualitydevelopment,productionandservice processes at both GermanmanufacturingsitesinGarching(nearMunich) and Vaihingen/Enz (nearStuttgart).

Jan16,2008.FreescaleSelects200mmSUSSToolSetforMEMSFacilitySUSS MicroTec announced it hasshipped and successfully installedseveral microelectromechanical sys-tems (MEMS) production tools atFreescaleSemiconductor.Theequip-mentincludedanewDSM200SeriesFront-to-Back Alignment VerificationSystem, the latest generation SUSSMA200Compact Mask Aligner aswellasaSUSSABC200seriesWa-fer Bond Cluster system for use inMEMSsensorapplications.With shrinking design rules, MEMSdevicesmustbeproducedwithhig-her precision and accuracy to en-sure reliability and the required per-formance. With an accuracy of 0.2micronat3sigma, theDSMsystemdemonstrates excellent measure-ment results in automated mode.Working in concert with the SUSSCompact seriesmask aligner, thesetwo machines represent the perfectpackage for double-sided alignmentandexposureapplicationsfrequentlyusedinthemanufacturingofMEMS,powersemiconductorsandoptoelec-tronicdevices.

Feb12,2008.SUSSMicroTecAGap-pointsnewVPSalesSUSSMicroTechas appointedTho-mas Breser to the position of VicePresidentSales.ThomasBreser co-mes to SUSSwith almost 20 yearsinternational experience within thesemiconductor industry.Hehasheldpositions in general management,sales management, business deve-lopment,productplanningandstra-tegicmarketing.

March3,2008.SUSSMicroTecBoostsNanotechnologywithNewToolset forMaskAlignersSUSS MicroTec has launched anadvanced nanotechnology toolsetfor itsMaskAligners.ThenewNanoImprintLithography(NIL)toolenablesSUSS Aligners to print resist thick-nesses from less than100nanome-ters to a few hundredmicrons witha printing resolution down to a fewnanometers. UV-NIL is a low-costproduction technology that is basedon UV-curing. It has been develo-pedasacost-effectivealternativetohigh-resolutione-beamlithographytoprint sub-20 nanometer geometries.UV-NIL applications with promisingperspectives include semiconductor,MOEMS, NEMS and optoelectronictechnologies.

April8,2008 .SUSSMicroTecInstallsFirst300mmWlRTestSysteminJa-panSUSSMicroTecannouncedtheinstal-lationof itsPM300WLR, theworld’smost advanced 300mmwafer-levelreliability(WLR)testsystem,atalea-ding Japanese manufacturer of se-miconductordevices. Itwill beusedfortestingthereliabilityofcurrentandnext-generationdevices.Asthetechnologyanddesignofse-miconductor devices advance, theneedtotesttheirreliabilityandgaugetheir lifetime becomes acuter. Com-monreliabilitytests,suchaselectro-migration (EM) and time-dependentdielectricbreakdown(TDDB),requirethedeviceundertest(DUT)tobeputunder thermal and electrical stressover longperiodsof time to accele-rate failure mechanisms. Before thePM300WLR, these measurementswere carried out after the DUT hadbeenpackaged,acostlyprocessthatdelays time to data and lengthensthe device design cycle. Bymovingthese tests to wafer level with thePM300WLR, reliability data is ob-tainedsooner,andthedevicedesigncycleandthustimetomarketcanbeimprovedsignificantly.

April 29, 2008 .SUSSMicroTecSignslicense Agreement with Philips Re-searchtodevelopaNewNanoImprin-tingTechnology:SubstrateConformalImprintlithography(SCIl)SUSSMicroTechasentereda licen-seagreementwithPhilipsResearch,

Eindhoven/TheNetherlands,foranewenablingtechnologycalledSubstrateConformalImprintLithography(SCIL).Theaimofthiscooperationistobringan existing equipment platform withthis additional Nanoimprinting (NIL)feature to themarket, enabling newapproachestolarge-areaimprintap-plicationsalongwithexcellentprintingresolutionandrepeatability.Thisnewimprinttechnologyforsub-50nmpatterning isbridging thegapbetweensmallrigidstampapplicationforbestresolutionandlarge-areasoftstamp usage with the usual limitedprintingresolutionbelow200nm.SCILisanenablingtechnologyofferingthebestof twoworlds – large-area softstamps with repeatable sub-50nmprintingcapability,avoidingstampde-formationasnocontact force isap-plied, non-UVbasedcuringat roomtemperatureandallowinghighaspectratiosevenupto1:5andmore.

May29,2008–SUSSAutomatedBondClusterSelectedforMEMSFoundryinKoreaSUSS MicroTec,announced thatu-ITC, Korea, has selected the ad-vancedwaferbondingequipmentofSUSSforitsMEMSfoundry.u-ITCisaworldclassMEMSfoundryspecializing in MEMS sensors. TheIncheon facility will incorporate de-sign,manufacture,assemblyandtestwithin one location for the growingfablessMEMSmarket.“The SUSS ABC200 AutomatedBondCluster isakeyacquisition forour foundry operations,” said Suh,Dong-RyangPh.D,Directoratu-ITC,“wecaneasilymeetour customers’needsbyusingaclustertoolthatcanbequickly reconfigured forchangingprocessconditions.”“The flexibility of the SUSS bondcluster to quickly reconfigure pro-cess parameters from small runs tofullproduction isabigadvantageofthe toolset, especially in thecaseofafoundryservingnewmarkets,”saidDanielT.Hurley,InternationalProductManager, Wafer Bonder Division,SUSSMicroTec.“Wearepleasedtosupportu-ITCastheyestablishthem-selves as the primary best in classMEMSfoundryinKorea.”The ABC200 is a 200mm Automa-ted Bond Cluster. It delivers supe-rior post-bond alignment accuracy

resulting from precision mechanics,uniform force capability and leadingedgetemperaturecontrol.SUSSMi-croTecoffersadvancedwaferbondi-ngsolutionsfortheMEMS,SOI,Op-toelectronics, and 3D Interconnectmarkets.

June 26, 2008 . SVTC TechnologiesSelects Processing Tools from SUSSMicroTecSUSSMicroTec,Inc.announcedthatasuiteofprocessingtoolsthatenablenewgenerationsofmicro-electrome-chanical systems (MEMS) has beenselected for SVTCTechnologies’ fa-cilityinAustin,Texas.As a key supplier to SVTC, SUSSMicroTec also will provide joint de-velopment and support for processand tooling. The SUSS toolsets atSVTCincludemanualandautomatedplatformstoperformlithographyandbonding-twoofthecriticalprocesssteps in the creation of MEMS de-vices.SVTC,aleadingindependentsemiconductorprocess-developmentfoundry,willusethesetoolstoprovi-deprocess solutionsandaprototy-pingfoundryforemergingMEMSandotherdevices.“The SUSS toolset represents thelatest technology-givingourcusto-merstheopportunitytoleadthewayfor emerging MEMS devices,” saidDave Bergeron, chief executive offi-cerofSVTC.MEMSdeviceshavebeeninstrumen-tal in creating many state-of-the-artproducts for the consumer, health-care, automotive and entertainmentindustries.Expectedtoincreaseata13percentcompoundannualgrowthrate through 2010, MEMS are theenabling technology behind manywell-known applications such as in-kjet printing, automobile air bags,global positioning systems andmo-tion sensinggamecontrollers. Futu-remarkets tobeopenedbyMEMStechnology include fuel cells, com-bustionoptimization, drugdiscoveryanddeliverysystems,aswellasnext-generation navigation and gamingsystems.“We are very pleased to be chosenbyahigh-qualityorganizationsuchasSVTCandareexcitedaboutthepos-sibilitiesthatthispartnershipbringstoSUSSMicroTecandourcustomers”,said Dr. Stefan Schneidewind, CEO

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of SUSS MicroTec. “The MEMS in-dustryhaslongbeenafocusforourcompany.Theopportunitytopartnerwith such highly respected forward-lookingorganizationasSVTCwillonlystrengthen our ability to service ourgrowingcustomerbaseandourpo-sitionasaleadingequipmentsuppliertotheMEMSmarket.”

July 1, 2008 . SUSS MicroTec leadsRankingof10BestMaterialHandlingSuppliersforthe10thYearSUSS MicroTec has been rankedagainamongthebestsuppliersinthe2008VLSIResearch10BESTCusto-

merSatisfactionAwards.CustomersratedSUSSMicroTecfirstamongtheMaterialHandlingSuppliers and fifthamongSmallSuppliersofWaferPro-cessingaswellaseighthamongtheoverallcategoryFocusedSupplierofChipMakingEquipment.Thesurvey’srespondents represent 95% of theworld’ssemiconductormarket.By securing a number one rankingfor the tenth year in the categoryMaterialHandlingSuppliers inwhichthe company’s probe systems arefeatured SUSS MicroTec has signi-ficantly extended its lead in the field

of customer satisfaction. Customersselected SUSS as best in Cost ofOwnership, Uptime, Build Quality,UsableThroughput,QualityofResult,Product Performance and Commit-mentthusmakingSUSSfirstinsevenofthethirteencategories.In the category Small Suppliers ofWafer Processing Equipment SUSSMicroTec was awarded fifth. Again,customersratedSUSSbestforBuildQualityandrankedSUSSamongthefirstthreewithinthecategoriesQua-lity of Results, Uptime and ProductPerformance.

“Ourcontinuoussuccessshowsthatourcustomershighlyvaluethequalityand customer support from SUSS.”said Dr. Stefan Schneidewind, CEOof SUSSMicroTec AG.” Clearly, ourcustomers appreciate our high-levelapplication expertise and superiorperformance theyhavecome toex-pect from us. We are dedicated tofurther proving ourselves as reliablepartnerand returning their trustwithon-goingcommitment.”

3DIntegrationTour

May22,2008SanJose,CA The “3D IntegrationNorthAmeri-canTour”cametoSanJoseonMay15afterstops inDurham,NCandDallas, TX. The event, hosted bySUSS MicroTec, Surface Tech-nologySystems(STS)andNExxSystemsoutlinedthecurrentstateof the art in through silicon vias(TSVs) and related technology. AnoverviewbyconsultantPhilGarrou,Ph.D.ofMCNCdescribingvariousprocess steps involved in 3D TSVtechnology led naturally into de-tailed presentations on processesandmaterials. The primary application for thistechnology today is CMOS im-age sensors, with DRAM stackedmemory as the next high volumeapplication.Garroushowedaroad-mapthatpredictedcompletelyhet-erogeneous stacks with via sizesaround 2 μmby 2014. AsGarrounoted,manyindustryleaders,rang-ingfromimagesensorandmemorymanufacturers to IDMs, foundriesandSATScompanies,areinvolvedin or have included roadmaps for3Dactivity.StephenVargo,Ph.D.,applicationsmanager at STS, discussed the

via etching process. He focusedonmethods to improveetch rateswithout producing rough sidewallsthat negatively impact via fill. De-signswithavarietyofviasizesarestillamajorchallenge.Theviafillprocessisthemostex-pensive step in the TSV processandthemosttime-consuming.Ad-vances inCuplatingchemistry,aspresentedbyDr.YunZhang,R&Dand technical marketing directorat Enthone, improve throughputforawide rangeofviasizeswhileproducing void-free vias. ArthurKeigler,VPof technologyatNEXXSystems, explained how agitatingtheplatingfluidnearthewaferpro-motedbottom-upfilling,eliminatingvoidsatthebottomofvias.Healsoadvised using electrochemical de-position todeposit the seed layer,reducingoverallcost.Forverylargevias, Bob Forman of Rohm andHass discussed a combination ofCu-platedlinerandpolymerplugtoreduce total fill time. Forman alsomentioned indium plating as anoption forapplications that requirelowertemperatureprocessing. Memory manufacturers empha-sized performance limitations of

wire-bondedstackeddiesolutionsfor future generations of DRAM.KyleKirby, seniorprocess integra-tionengineeratMicron,showedaroadmapofTSVtrendsformemorywith via sizes decreasing below 5μmanddensityincreasingto1000I/Operdevice.Challengesinmov-ing toward this goal include rout-ingbetweendieondifferent levels(design tools are not really readyfor3Dintegration)andovercomingthermo-mechanicalstressesasviaspacingdecreases.BobPatti,CTOofTezzaron, proposed a solutionthatde-couplesthecontrollerfromthe memory functions in separatelayers, decreasing the number ofTSVs required. He also discussedincreased use of built-in self testand stacking using a template,achievingahybridbetweenwafer-wafer and die-wafer bonding thatallowstheuseofKGDwithreason-ablyhighthroughput.Bothoftheseapproachesimproveoverallyieldofawaferstack.Thecurrentstateoftheartinwaferaligning,bondingandthinning,alsodiscussed at the seminar, seemsufficient to enable further devel-opment of 3D processes. Kirbystatedthat,“TSVsarethefutureofadvanced packaging.” That maybe true,but it remains tobeseenwhether3DICintegrationwillbringaboutthedeathofwirebonding,asflipchippromisedtodoyearsago.

ThiscolumnisreprintedwithpermissionfromAdvancedPackagingMagazine.

AreTSVstheFutureofAdvancedPackaging?

byJuliaGoldstein,Ph.D.

Julia Goldstein, Ph.D. has beentechnical editor of AdvancedPackagingmagazinesince2001.ShereceivedaB.S. inengineer-ing from Harvey Mudd College,and M.S. in materials sciencefrom Stanford, and a Ph.D. inmaterials science from U.C.Berkeley. Julia hasworked as aprocess development engineerat nCHIP, where she developeda flip chip process formultichipmodules. Since 1996, she hasbeenatechnicalconsultantinar-easrangingfromflipchipbump-ingtothinfilmcoatings.Juliahasauthored 11 technical publica-tions,andisamemberofIMAPSandMEPTEC.

Some of the opportunities to meet with SUSS MicroTec in the upcoming months:

July

IPFA . July 07 - 11, 2008

SemiconWest . San Francisco, CA, USA . July 15 - 17, 2008

MIG (MEMS Industry Group) EducationSeries . San Francisco, CA, USA . July 18, 2008

Micromachine . MEMS . Tokyo, Japan . July 30 - August 01, 2008

August

NanoKorea . Nano . Seoul, Korea . August 27 - 29, 2008

September

ESTC . Greenwich, UK . Sept 1 to 4, 2008

SemiconTaiwan . Taipei, Taiwan . Sep 09-11, 2008

LEDSeminarSemiconTaiwan . Taipei, Taiwan . Sep 11, 2008

MNE08 . Athens, Greece . Sep 15 to 18, 2008

Micronora . Besancon, France . Sept 23 to 26, 2008

MME . Aachen, Germany . Sep 28 to 30, 2008

ESREF . Maastricht, Netherlands . Sep 29 - Oct 02, 2008

October

SemiconEuropa . Stuttgart, Germany . Oct 07-09, 2008

ABMSSeminar . Kitakyushu, Japan . Oct 8-10, 2008

ECSFallMeeting/PRIME . Honolulu, Hawaii . Oct 12-16, 2008

EuropeanMicrowaveWeek . Amsterdam, Netherlands . Oct 27-31, 2008

SUSSSeminar . Tokyo, Japan . Oct 29, 2008

SUSSSeminar . Shanghai, China . Oct 31, 2008

November

ISTFA . Portland, OR, USA . Nov 2-6, 2008

SUSSSeminar . Seoul, Korea . Nov 3, 2008

SUSSSeminar . Taipei, Taiwan . Nov 5, 2008

MEMSExecutiveCongress . Monterey, CA, USA . Nov 5-11, 2008

SUSSSeminar . Singapore . Nov 7, 2008

RTI-3D . Burlingame, CA, USA . Nov 17-19, 2008

Microwave . Yokohama, Japan . Nov 26-28, 2008

December

SemiconJapan . Chiba, Japan . Dec 03-05, 2008

ARFTG . Portland, OR, USA . Dec 9-12, 2008

SponsorMRS . Boston, MA . Dec 12, 2008

APMC . Hong Kong . Dec 17-19, 2008

Please check our website for any updates: www.suss.com/events

SUSS.OurSolutionsSetStandards

SUSSMicroTecAGSchleissheimerStrasse9085748GarchingnearMunichGermany

We hope you found this edition of the SUSS Report interesting and informative. For more information about SUSS and our products, please visit

www.suss.comor write toinfo@suss.comwith your comments and suggestions.