Powering tests

Laura Gonella Physikalisches Institut Uni Bonn

Powering configurations

2 L. Gonella - Powering tests

Meaurements

• For different powering configuration, measure

For now done on bare chips. Current PCB does not have circuitry for sensor HV.

Wire bond from VDDA pad to measurement point. Same for VDDD.

VDDA2M is not connected on the PCB. It was removed to make space for regulator testing circuitry.

43PrmpVbp,

PrmpVbp_L/R

• Power is provided via an independent power supply– Either to VDDD and VDDA directly or to the input of the

regulators• USBpix is used only to send/receive signals to/from the chip

– Stcontrol– Standard configuration file

• Top row not powered– DC1 and DC40 disabled

Direct powering configuration 1 (DP1)

Rwire RpcbRwb

Voltages and currents

V @ supply (V) V @ chip (V) I (mA)

Power up A 1.5 1.502 13

D 1.2 1.199 3

Clock on A 1.5 1.502 13

D 1.2 1.176 92

Std cfg A 1.5 1.458 268

D 1.2 (1.22) 1.172(1.191) 107(109)

PrmpVbp*2 A 1.5 1.440 372

D 1.22 1.192 105

• Ra = 0.157Ohm• Rd = 0.265Ohm

Threshold scan

Threshold scan – PrmpVbp*2

• VDDD and VDDA shorted at supply– Same Rwire, Rpcb, Rwb as in the previous measurement– Use calculated Ra and Rd to extimate analog and digital current

RpcbRwb

Voltages and currents

V @ supply (V)

V @ chip (V)

I (mA) I calc (mA)

Power up A 1.5 1.502 20

D 1.502

Clock on A 1.5 1.498 98 13

D 1.484 60

Std cfg A 1.5 1.458 481 268

D 1.440 226

PrmpVbp*2

A 1.5 1.447 508 338

D 1.455 170

• The analog current should increase of 100mA when PrmpVbp = 86, the digital current should stay the same

• The analog current increases of 70mA• The digital current decreases of 60mA ???

Threshold scan

Regulator configuration 1 (Reg1)

L. Gonella - Powering tests15

0.01Ω

Power up - Voltage

• Vin is the voltage at the power supply• Vin Reg1, Vin Reg2, VDDD, VDDA are measured at the pad

– Wire bond from the pad to a measurement point

Power up - Current

• Iin is the current measured at the power supply, i.e. total current flowing to the chip

VDDD regulated VDDA regulated

Voltages and currentsVin (V) Iin (A) Vin

Reg1/2(V)VDDD/A Ia, Id

Power up A 1.8 0.239 1.716 1.473 0.150

D 1.728 1.198 0.140

Clock on A 1.8 0.262 1.709 1.470 0.180

D 1.722 1.189 0.141

Std cfg A 1.8 0.409 1.640 1.418 0.375

1.458(*)

D 1.686 1.189 0.137

PrmpVbp*2

A 1.8 0.509 1.588 1.413 0.511

D 1.660 1.189 0.134

• Ia, Id measured as a Vdrop across a R=10mOhm• Ia + Id > Iin ????

• (*) Vref1 = 0.730V, increased to 0.750V after loading the std cfg

Threshold scan

Vref = 0.740V

0.01Ω

Power up - Voltage

• Vin is the voltage at the power supply• Vin Reg1, Vin Reg2, VDDA are measured at the pad

– Wire bond from the pad to a measurement point

Power up - Current

• Iin is the current measured at the power supply, i.e. total current flowing to the chip

VDDA regulated

Voltages and currentsVin (V) Iin (A) Vin

Reg1/2(V)VDDA/D Ia (A)

Power up A 1.8 0.250 1.711 1.484 0.160

1.727 0.135

D 1.2 0.015 - 1.193 -

Clock on A 1.8 0.265 1.708 1.483 0.190

1.723 0.135

D 1.2 -0.065 - 1.217 -

Std cfg A 1.8 0.296 1.693 1.471 0.227

1.715 0.137

D 1.2 -0.063 - 1.216 -

PrmpVbp*2

A 1.8 0.397 1.657 1.455 0.295

1.679 0.193

D 1.2 -0.063 - 1.216 -

Threshold scan

Vref mismatch

• Vref1 = 0.740V

Vref2 (V) Vin Reg1 (V)

Vin Reg2 (V)

Iin1 (A) In2 (A) VDDA (V)

0.740 1.692 1.714 0.232 0.137 1.471

0.730 1.663 1.700 0.314 0.134 1.455

0.720 1.636 1.685 0.390 0.132 1.435

0.710 1.609 1.672 0.461 0.130 1.418

0.700 1.578 1.650 0.505 0.127 1.399

Summary table

DP 1 DP 2

Std PrmpVbp*2

Vth 4652 4630 4433 4433

Vth dispersion 639.1 625.6 569.5 565.3

Noise 149.1 143.6 135.9 133.7

Noise dispersion

15.63 13.83 10.81 10.3Reg 1

Std PrmpVbp*2

4499 4466

599.4 588

152.2 142.3

16.26 13.45

Vth dispersion

Noise dispersion

Std PrmpVbp*2

4557 4557

612 599.3

166.2 153.3

18.1 15.6

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