© 2013
Copyrights © Yole Developpement SA. All rights reserved.
Technology and Market forecast for
2.5/3D and Wafer Level Packaging
Courtesy of Fraunhofer-IZM
Christophe Fitamant
Nokia
© 2013 • 2Copyrights © Yole Developpement SA. All rights reserved.
Fields of Expertise
• Yole Developpement is a market, technology and strategy consultingcompany, founded in 1998. We operate in the following areas:
• Our expertise is based on research done by our in-house analysts,conducting open-ended interviews with most industry players.
MEMS & image sensors
Photovoltaic
Advanced Packaging
Microfluidic
& Med Tech
Power Electronics
HB LED, LED & LDEquipment and materials
© 2013 • 3Copyrights © Yole Developpement SA. All rights reserved.
Introduction
Advanced Packaging Overview
Middle-End Characteristics
2.5 & 3D Packaging
Market Forecasts
Applications
IP Activities
Conclusions
Presentation Outline
Xilinx
Micron
© 2013 • 4Copyrights © Yole Developpement SA. All rights reserved.
Introduction
Wafer-level-packaging market is gaining more and more significance in the
semiconductor industry; it shows the greatest potential for significant future growth in
the semiconductor industry.
The evolution of semiconductor packaging technologies over the past 40 years has
been driven by the need to bridge the increasing “I/O interconnect gap”, between the
fast decreasing silicon geometries (Moore’s law) and the slower shrink of the Printed
Circuit Board technologies
© 2013 • 5Copyrights © Yole Developpement SA. All rights reserved.
2011 2012 2013 2014 2015 2016 2017
TOT Semiconductor IC wafers 84 92 101 111 122 135 148
TOT Wafer-Scale-Packaged IC wafers 13 14 17 21 25 31 35
% ratio 15% 16% 17% 19% 20% 23% 23%
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
0
20
40
60
80
100
120
140
160
% p
enet
rati
on
Rat
io
Waf
er
ship
me
nts
(i
n M
un
its
of
30
0m
m w
afer
s eq
.)
% Ratio of WW Semiconductor IC Wafers Packaged at the Wafer-Scale(Volume in millions of 300mm wafers eq.)
Yole Développement © October 2012
Wafer-Level-PackagingIn the semiconductor IC wafer processing industry
In 2012, ~ 16% of overall semiconductor IC wafers were manufactured with packaging features
(bumping, RDL, TSV, etc…) processed at the wafer-scale
CAGR
21%
10%
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Advanced Packaging Platforms
Wafer-Level Electrical Redistribution
Flip-chip & Wafer-LevelStacking / Integration
WL CSP‘Fan-in’
FOWLP‘Fan-out’
Glass / Silicon Flip-chip wafer bumping
on BGA
3D IC
& TSVEmbedded die in PCB / laminate
Wafer-Level Interface / Encapsulation
3D WLPFor MEMS & sensors
(also called 3D SiP sometimes)
LED & Sensors
WLOptics 2.5D
interposers
Historically supported by flip-chip wafer bumping with electroplated gold & solder bumps,
today there are an array of solutions, such as: copper pillars, Fan-in WLCSP packages, 3D
WLP, FO-WLP packages, 2.5D Glass / Silicon interposers and 3DIC with TSV
interconnects
Wafer-level-packages have emerged in many different varieties that can be
categorized into different advanced packaging technology platforms
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Middle End Area
Advanced Packaging Platforms
RDL
BumpingBalling
Wafer Bonding
TSV
WL-Optics
WL-Capping
Balling
WLCSPFO
WLPEmbedded
ICFlip Chip
MEMS IC
Capping
IC
Sensor
Memory
Logic
3DWLCSP
Die 1 Die 2 Die 3 Die 4
Middle-End Process Steps
3D-IC2.5D
Interposer
© 2013 • 8Copyrights © Yole Developpement SA. All rights reserved.
WLP – “Middle-End” Technologies
FEwafer manufacturing
‘Middle-end’
BEassembly & testetch
implant
CVD
PVD
CMP
Wafer test
TSV bumpingRDL / wiring C2W
C2C / C2S
underfill molding Final testhandling
thinning BGAdicing
inspection
cleaning
“Middle-end” vs Front-End vs Back-End
inspection W2W
Courtesy of Stats ChipPAC
Wafer level packages are true “Middle-end’ technologies, leverage similar type
of process manufacturing know-how
Middle-end is a strategic area where Foundries, OSATs, WLP Houses and IDMs
stepped in, an infrastructure that has emerged by itself in the last 5 years.
Middle end technologies are found in the overlap area between the IDMs or CMOS
foundries’ back-end of line (BEOL) wafer fabs and the the back-end wafer bumping
assembly facilities of the OSATs and wafer bumping houses
© 2013 • 9Copyrights © Yole Developpement SA. All rights reserved.
Middle-end Infrastructure is Growing
Significant growth of 3D Packages: 3D IC, Embedded (3D SIP and FOWLP) and Interposers
0,0
5,0
10,0
15,0
20,0
25,0
30,0
35,0
40,0
2011 2012 2013 2014 2015 2016 2017
Vo
lum
e (i
n M
un
its
of
30
0m
m w
afer
eq
.)
Global Wafer-Level-Packaging Demand(in Munits of 300mm wafer eq. )
Yole Développement © October 2012
3DIC
Flip-chip
2.5D interposers
3D WLP
WL CSP
FO WLP
3D SiP
« Mid-End » infrastructure – the leading driver and the fastest growing semiconductor
packaging technology with more than 18% CAGR in units over the next 6 years
© 2013
Copyrights © Yole Developpement SA. All rights reserved.
2.5D & 3D Packaging
Market Trends & Applications
Infineon
MicronSynopsysVTI
CEA LETI
Xilinx
© 2013 • 11Copyrights © Yole Développement SA. All rights reserved.
“More than Moore”
Heterogeneous integration
Co-integration of
RF+logic+memory + sensors
in a reduced space
Density
Achieving the highest
capacity / volume ratio
Form Factor-
driven
Performance-
driven
3DICOptimum Market
Access Conditions
Wide IO
memory
CIS
DRAM
RF-SiP
Electrical performance
Interconnect speed / bandwidth and
reduced power consumption
3D vs. “More Moore”
Can 3D be cheaper
than going to the next
lithography node?
Flash
Cost-driven
Partitioning
Sensors
3DIC Market DriversUnchanged since 2010!
CPU
GPU
Power.
Analog.
FPGA
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3D TSV Application Segmentation
Imaging
LED
MEMS &
SensorsHB-LED Stacked
memories
RF, Power,
Analog &
Mixed Signal
Logic 3D-
SiP/SoC
3D TSV Applications
WLP CIS
BSI CIS
Wafer level
auto-focus
3D integrated
CIS
Gyros
Acceleros
Pressure sensors
Si-micro
FBAR filters
Oscillators
µProbes
µFluidic / IJ
µValves
Fingerprint
sensors
Micro-mirrors
IR-bolometer
Opto (laser, VCSEL)
Mobile µ-Flash
Automotive
General Lighting
Projection engine
PA
MOSFET
IGBT
IPD
DC-DC
converters
Stacked DRAM
StackedNAND
Flash
StackedNOR /
PCRAM
3D SoC
Baseband / DSP
MCU / Processors
Touchscreen
controller
Low-end ASICs
PMIC
3D SiP
Wide IO BB
CPU / GPU
FPGA
High. Perf ASICs
© 2013 • 13Copyrights © Yole Développement SA. All rights reserved.
What are the Markets for 3D ICs?
• 3D integrated ICs will be introduced in a variety of applications, all with their own
specifications, challenges and individual roadmaps!
High Volumes
Lower Volumes
3D IC opportunities
High-end Multimedia
Smart-phones / PMP
High-density
Solid State
Storage & µ-Cards
Notebooks / MID
‘connectivity’ devices
Gaming / Graphic
application engines
High-performance
computers / Network &
Storage components /
Green Data servers
High-performance
Digital Video
Wireless
Connectivity /
Network Center
AutomotiveMedical
© 2013 • 14Copyrights © Yole Developpement SA. All rights reserved.
-
2 000 000
4 000 000
6 000 000
8 000 000
10 000 000
2010 2011 2012 2013 2014 2015 2016 2017
Waf
er c
ou
nt
(12
’’e
q.)
Global TSV Chip Wafer Forecast (All 3D Platforms)Breakdown by Segment (12''eq wafers)
3D Stacked NAND Flash
3D Wide IO Memory
Logic 3D SiP / SoC
3D Stacked DRAM
MEMS / Sensors
LED
RF, Power, Analog &Mixed signal
Imaging &Optoelectronics
Yole Developpement © July 2012
Global TSV Chip Wafer ForecastBreakdown by segment (12’’eq. Wafers)
Logic 3D SiP (including Interposers, APE, CPU, FPGA, Wide IO
memory, etc. will be the largest segment using 3D platforms in
the next few years.
© 2013 • 15Copyrights © Yole Développement SA. All rights reserved.
The Future 3DIC Market is Driven by
Stacked Memories & Logic SOC Applications• 3DIC technology is seen today as a new paradigm for the future of the
semiconductor industry, as it will enable several more decades of chip evolution
at ever lower costs, higher performance and smaller-sized features
– 3D stacked DRAM and 3D Logic SOC applications are expected to be the biggest drivers for the
volume adoption of 3DIC technology in the next five years, followed by CMOS image sensors, power
devices and MEMS.
DRAM$363 M
22%
Wide IO Memory$325 M
19%
Logic SoC (APE, BB/APE)$404 M
24%
NAND Flash Memory$66 M
4%
CIS$63 M
4%
Low-End ASIC$110 M
7%
Power Devices (IGBT, PA, PMU)
$172 M10%
Other Logic (ASIC, FPGA, ASSP …)$76 M
5%
MEMS/Sensor$87 M
5%
3DIC Platform Middle-End Revenues by 2017 (M. US$)Breakdown by IC type
* Middle-end activity revenues including TSV, Filling, RDL, Bumping,
wafer test & wafer level assembly
Yole Developpement © July 2012
Total =
$1.7B
Memory
Logic
© 2013
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Patent Analysis
IP Landscape
© 2013 • 17Copyrights © Yole Développement SA. All rights reserved.
Assumptions and Methodology
• Topic of the research– Three dimension integrated circuits
• Database– The data was extracted from the Questel IP portal www.orbit.com (FamPat). The FamPat database
covers more than 60 million patent documents (90+ offices) grouped in invention-based families. The
screening is performed for US, EP, WO, JP translated English full text, GB, DE, FR, CN+TW+KR
translated English full text using English + French + German keywords
• Search strategy– Keywords (? replaces 0 or 1 character, + replaces 0 or n characters)
TSV: Through Silicon Via?, TSV, Through Substrate Via?, Through Via Hole?, Through Hole Via?, Through
Silicon Hole?, Through Substrate Hole?, Through Silicon Interconnect+, 3D Interconnect+, Vertical
Interconnect+
3D: 3D Integrat+, 3DIC, 3D (associé à un composant), Vertical Integrat+, Vertical (associé à un composant), Chip
to Chip, Chip to Wafer, Wafer to Wafer, 2.5D Interposer?, 2.5D IC, Silicon Interposer?, More Moore, More Than
Moore.
Components: IC?, Integrated circuit?, Circuit?, Die?, +Chip?, Device?, Module?, Component?, SoC, SiP, Wafer?,
Semiconductor?
– Fields of search: title, abstract and claims
• Data analysis– The quantitative analysis of data was made using the Intellixir software
© 2013 • 18Copyrights © Yole Developpement SA. All rights reserved.
Focus of the analysis
Targeted Platforms for the IP Report
Advanced Packaging Platforms
RDL
BumpingBalling
Wafer Bonding
TSV
WL-Optics
WL-Capping
2.5D Interposer
3DIC
Balling
WLCSPFO
WLPEmbedded
ICFlip Chip
MEMS IC
Capping
IC
Sensor
Memory
Logic
3DWLCSP
Die 1 Die 2 Die 3 Die 4
Middle-End Process Steps
© 2013 • 19Copyrights © Yole Developpement SA. All rights reserved.
Trend of Patent Filing for 3DIC Technologies
Patent Filing Trends for 3DIC Technologies
• 1013 patent families were filed from 1969 to 2012
• 82% of patents were filed since 2006
Yole Developpement © December 2012
0
20
40
60
80
100
120
140
160
180
200
220
240
260
1968 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012
No
. of
Pat
ent
Fam
ilies
Priority years
© 2013 • 20Copyrights © Yole Developpement SA. All rights reserved.
Geographical Distribution of Patents Filing
for 3DIC Technology
• Patents in domain are mainly filed by firms or universities located in USA (56%)
and Korea (18%)
• These patents are mainly extended in USA, China, Korea, Taiwan and Japan (map
on the right)
Geographical Distribution of Patents Based on
Publication Country
Geographical Distribution of Patents Based on
Priority Country (related and relevant included)
© 2013 • 21Copyrights © Yole Developpement SA. All rights reserved.
Legal Status of Patent Filings for 3DIC Technologies
• Among the 1569 patent documents constituting the 961 relevant patent families, 85% are
active (granted or pending) and 13% are inactive (lapsed, revoked or expired).
• Pending patents and granted patents represent almost equivalent shares
• The significant number of pending patents reflects the youth of 3DIC technologies
Legal Status Distribution of Relevant Patent
(all members of each patent family)
Yole Developpement © December 2012
Granted616 (39%)
Pending713 (45%)
Lapsed150 (10%)
Revoked43 (3%)
Expired13 (1%)
Not available34 (2%)
ALIVE
1329 (85%)
DEAD
206 (13%)
© 2013 • 22Copyrights © Yole Developpement SA. All rights reserved.
Patent Assignees for 3DIC Technologies
• About 260 players are involved in 3DIC technology while the top 10
assignees represents 48% of patents filed in 3DIC domain
Top 10 Patent Assignees for 3DIC Patents (relevant and related included)
Yole Developpement © December 2012
74
71
70
61
56
48
25
24
23
21
2
5
2
1
1
4
2
0
0
1
0 25 50 75 100
IBM (US)
SAMSUNG (KR)
MICRON (US)
TSMC (TW)
HYNIX (KR)
STATS CHIPPAC (SG)
INTEL (US)
AMKOR (US)
ELPIDA (JP)
ITRI (TW)
No. of Patent Families
Assignee
Relevant
Related
© 2013 • 23Copyrights © Yole Developpement SA. All rights reserved.
Legal State of Relevant Patents for Top 10 Assignees
Top 10 Assignees / Legal State of Relevant Patents (all members of each patent family)
Yole Developpement © December 2012
203
176
167
156
140
131
56
44
32
25
7
17
1
2
2
8
1
1
0 50 100 150 200 250
MICRON (US)
IBM (US)
SAMSUNG (KR)
TSMC (TW)
HYNIX (KR)
STATS CHIPPAC (SG)
INTEL (US)
ELPIDA (JP)
ITRI (TW)
AMKOR (US)
No. of Patent Documents
Assignees
Alive
Dead
• 14% of Intel’s relevant patents are inactive while 100% of relevant patents of both
STATS ChipPAC and ITRI are active (granted or pending)
© 2013 • 24Copyrights © Yole Developpement SA. All rights reserved.
Top Academic Assignees for 3DIC Patents
• Top 10 academic assignees represent more than 11% of the patents filed in 3DIC domain.
ITRI (TW), CEA (FR) and FRAUNHOFER (DE) are within the Top 15 assignees.
Top Academic Assignees for 3DIC Patents
Yole Developpement © December 2012
21
19
15
14
11
9
8
7
6
5
1
2
2
0
0
0
0
0
0
0
0 5 10 15 20 25
ITRI (TW)
CEA (FR)
FRAUNHOFER (DE)
KAIST (KR)
IMEC (BE)
UNIV BEIJING (CN)
ASTRI (HK)
UNIV TSINGHUA (CN)
CHINESE ACA. SCI. (CN)
ETRI (KR)
No. of Patent Families
Assignee
Relevant
Related
© 2013 • 25Copyrights © Yole Developpement SA. All rights reserved.
Intel Patent Filing Evolution for 3DIC Technologies
• Intel’s patent portfolio is composed of 27 patent families comprising 86 patents (> 50% are
pending). Their patenting activity on 3DIC started early 2000s with most patent filings in
2005. Their patenting activity has been relatively limited during last 5 years.
• About 65 inventors are involved in 3DIC at Intel.
Note: The data corresponding to the years 2011 and 2012 may not be complete since a significant number of patent applications filed during these
years might not have been published yet.
1 1
4
7
4
21 1
3
1
1
1
0
1
2
3
4
5
6
7
8
1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
No
. o
f p
ate
nt
fam
ilie
s
Priority year
Related
Relevant
Patent Filing Evolution for 3DIC at Intel
Yole Developpement © December 2012
© 2013 • 26Copyrights © Yole Developpement SA. All rights reserved.
Country of Origin
(relevant and related included)
• All Intel’s priority patent applications are originating in USA.
• Note that use of World (WO) and European (EP) codes may hide a significant portion of other
countries patent activities.
Country of Deposition
(relevant and related included)
US27
(100%)
US27 (43%)
WO11 (17%)
CN6 (9%)
TW5 (8%)
KR3 (5%)
DE3 (5%)
JP2 (3%)
UK2 (3%)
EP2 (3%)
RU1 (2%)
SG1 (2%)
Intel Countries of Origin & Deposition for 3DIC
Yole Developpement © December 2012
© 2013 • 27Copyrights © Yole Developpement SA. All rights reserved.
Intel Patent Portfolio Analysis
As an Integrated Device Manufacturer (IDM), Intel is involved in both Design and Process development.
=> However, almost 80% of the Intel’s patents are dedicated to 3DIC & TSV process optimization
Design8%
Process79%
Architecture13%
Intel Patent Portfolio AnalysisBreakdown by technological area
Lithography4%
Etching14%
Isolation17%
Barrier / Seed17%
Filling14%
Bump / Passivation /
UBM / 21%
TB / TDB10%
Thinning / Grinding
3%
Intel Patents Describing ProcessBreakdown by process step
• All the process steps for 3DIC manufacturing are
described in Intel’s patents
– Bumping is the main area patented by Intel
– Followed by barrier/seed, TSV isolation, TSV etching
and filling
As an IDM, Intel is strongly focused on middle-end
activities, epecially on inter/intraconnections for 3D
stacking
• Memory is the most mentioned in patents (54%)
Interposer31%
Memory54%
Logic(CPU, GPU, processor)
15%
Applications Mentioned in Intel's PatentsBreakdown by end applications
Yole Developpement © January 2013
© 2013 • 28Copyrights © Yole Developpement SA. All rights reserved.
Samsung Patents Describing TSV and 3DIC
Manufacturing Processes
• Most Samsung patents about process describe
isolation (31%) and bumping (25%)
– Indeed, as an IDM Samsung, like Intel, has strong
knowhow in the middle-end area (especially in
bumping) and moved fast to 3DIC in order to
develop and adapt the technologies to the new
requirements
• Following isolation, the process steps which are
the most described in Samsung patents are TSV
etching, TSV filling and barrier/seed deposition
Lithography6% Etching
11%
Isolation31%
Barrier / Seed8%
Filling10%
Bump / Passivation /
UBM / 25%
TB / TDB6%
Thinning / Grinding
3%
Samsung Patents Describing ProcessBreakdown by process step
Design3%
Process62%
Test 11%
Architecture24%
Samsung patent portfolio analysisBreakdown by technological area
Yole Developpement © January 2013
Interposer15%
Memory69%
Logic(CPU, GPU, processor)
16%
Applications mentioned in Samsung patentsBreakdown by end applications
© 2013 • 29Copyrights © Yole Developpement SA. All rights reserved.
IBM Patents Describing TSV and 3DIC
Manufacturing Processes
• Initially using TSV for power amplifier, IBM spent
a great deal of effort on TSV isolation to improve
electrical performance, especially at high
frequencies.
• Isolation brick is followed by TSV filling,
bumping, barrier & seed layer and TSV etching
Lithography6%
Etching8%
Isolation32%
Barrier / Seed8%
Filling13%
Bump / Passivation /
UBM / 9%
TB / TDB17%
Thinning / Grinding
6%
Nailing1%
IBM Patents Describing ProcessBreakdown by process step
Interposer28%
Memory42%
Logic(CPU, GPU, processor)
30%
Applications Mentioned in IBM PatentsBreakdown by end applications
Yole Developpement © January 2013
Design9%
Process76%
Test 9%
Architecture6%
IBM Patent Portfolio AnalysisBreakdown by technological area
Yole Developpement © January 2013
© 2013 • 30Copyrights © Yole Developpement SA. All rights reserved.
TSMC Patents Describing TSV and 3DIC
Manufacturing Processes
• TSMC’s patent portfolio is composed of 62 patent
families comprising 159 patents
• 82% of TSMC patents mention silicon interposer
• TSMC patents are mainly focused on 3DIC & TSV
process (78%) as well as new architectures (15%)
• Strong focus on TSV isolation in TSMC patents (33%
are describing this step), followed by barrier & seed
layer (15%), bumping (14%) and temporary
bonding/debonding (13%)
Lithography6%
Etching4%
Isolation33%
Barrier / Seed15%
Filling8%
Bump / Passivation /
UBM / 14%
TB / TDB13%
Thinning / Grinding
5%
TSMC Patents Describing ProcessBreakdown by process step
Interposer82%
Memory9%
Logic(CPU, GPU, processor)
9%
Applications mentioned in TSMC's patentsBreakdown by end applications
Design3%
Process78%
Test 4%
Architecture15%
TSMC's patent portfolio analysisBreakdown by technological area
Yole Developpement © January 2013
© 2013
Copyrights © Yole Développement SA. All rights reserved.
Conclusions & Perspectives
© 2013 • 32Copyrights © Yole Developpement SA. All rights reserved.
2.5D, 3DIC & TSV InterconnectsIP Landscape conclusions
• For this patent analysis on 3DIC, more than 1800 patent families have been
screened– Patents are mainly filed by firms or universities located in USA (56%) and Korea (18%)
– These patents are mainly extended in USA, China, Korea, Taiwan and Japan
– USA is the early player increasingly involved in 3DIC since 1969
– China and Korea are new players since 2005
• Among the 1569 patent documents constituting the 961 relevant patent families,
85% are active (granted or pending) and 13% are inactive– Important number of pending patents reflects the youth of 3DIC technologies
• About 260 players are involved in 3DIC technology while the top 10 assignees
represents 48% of patents filed in 3DIC domain
• IBM, Samsung, Micron, TSMC, SKHynix, StatsChipPAC, Intel, Amkor and ITRI are
top players involved in 3DIC patenting activity
• IBM (US) and Micron (US) are the main assignees since 1990 and are still active
• Hynix (KR) and StatsChipPAC (SG) emerged as new players during these 5 last
years
© 2013 • 33Copyrights © Yole Developpement SA. All rights reserved.
Despite normal slower than expected adoption, Yole continues to see significant growth for 2.5 / 3DIC and other TSV based applications based upon our bottom up surveying of the advanced packaging supply chain.
Supply chain options are increasing which should lead to a lower cost structure for TSV based products (chips, interposers etc.)
All announced products are still based on high density silicon interposers
IP landscape for key players in the 2.5 / 3DIC market reveals very significant activity in the middle-end area
Conclusions
© 2013 • 34Copyrights © Yole Developpement SA. All rights reserved.
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