Xilinx Motor Solutions ADI Short June 2012

Cliff Tsai , [email protected] , 02-81761006Channel FAE ManagerJune.2012

Xilinx Motor Solutions

© Copyright 2012 Xilinx

Xilinx 28nm 7-series FPGA

Vivado and High Level Synthesis(C/C++/SystemC to RTL)

FPGA Motor Solutions

Zynq and Motor Solutions

ADI FMC cards for Xilinx Platforms

Agenda



Xilinx 28nm Platforms


7 Series Power Efficiency Focus from Every Angle – 50% Lower Total Power

BRAM

High performance, low power process Transistor choice

optimization

ConfigMemory

VCCAUX

Reduced from 2.5V to 1.8V

Reducing Static Power

5th gen. partial reconfiguration

Additional Power Saving

FeaturesIntegrated Analog Front End

Unused BRAM Power Savings

Out

InPad

-+

VCCO

IO Design & User Power

Saving Modes

Reducing I/O Power

Process Shrink Reducing

Dynamic Power

Optimized Hard

BlocksFine grain clock and logic gating

Lower device core voltage

-2LXilinx

7 SeriesFPGAs

Before After

reconfiguration

Scalable Optimized Architecture Boosts Design Productivity - Accelerating Design Creation, Debug and Simplifying Reuse

XST

ngdbuild

map

par

trce

bitgen

Coregen

EDK

SysGen

3rd party

Rodin

Pre-verifiedIP

assemblytool

Unified SW Architecture

AXI4 (data)

AXI4

Streaming

AXI4

AXI4 Lite

AXI4 Lite

AXI4 Lite

AXI4

AXI4 LiteProcessor

AXI

Interconnect

Block

AXI DDR3

Mem Ctrl

DMA

Timer

IntCtrl.

Flash Int.

TEMAC

AXI

Interconnect

Block

Plug & Play IP

3 party

Plug & Play Boards

Solving Next Generation Design Challenges For All Market Segments

Agile Mixed Signal Technology Customized Applications

Motor Control/Power Conversion Touch Control (HMI)

System Management Sensor Interface

FPGA Leadership at 28nm

Lowest Total Power FPGAs– HPL process proven 50% lower over alternative

Highest Productivity FPGAs– Unified, plug and play with extensive Ecosystem– Agile Mixed Signal (AMS) providing analog capability in all 7 series family members– Fastest cost reduction path with EasyPath™-7 (Kintex-7 7K355T-7K480T, all Virtex-7 FPGAs)

Highest Performance FPGAs– Largest capacity: 2M logic cells (XC7V2000T)– Largest capacity: 2M logic cells (XC7V2000T)

– Largest transceiver count: 96 (XC7VX1140T)

– 100x better connectivity/watt: Stacked Silicon Interconnect Technology– Fastest memory interface: 1,866 Mb/s (Kintex-7 and Virtex-7 FPGAs)

– Largest Block RAM capacity: 68 Mb (XC7VX1140T)

– Highest DSP performance: 5,335 GMACS - symmetric mode (XC7VX980T)

Innovative Architecture Breaks the Rules– Extensible Processing Platform (Zynq-7000 EPP family)

Industry’s Most Capable Programmable Offering

Vivado and High Level Synthesis


Why Now?

Programmable Logic DevicesEnables Programmable

‘Logic’

ALL Programmable DevicesEnables Programmable

Systems ‘Integration’

Page 10

Bottlenecks are Shifting

System Integration Bottlenecks– Design and IP reuse

– Integrating algorithmic and RTL level IP

– Mixing DSP, embedded, connectivity, logic

Implementation Bottlenecks– Hierarchical chip planning

– Multi-domain and multi-die physical optimization

– Predictable ‘design’ vs. ‘timing’ closure

– Late ECOs and rippling effect of changes

– Mixing DSP, embedded, connectivity, logic

– Verification of blocks and “systems”

Page 11

Vivado: Accelerating Productivity up to 4X

AcceleratingIntegration

IP & SystemIP & System --centriccentricIntegration with FastIntegration with Fast

VerificationVerificationup to

4X

Vivado Next Vivado Next Generation Generation

Design SystemDesign System

AcceleratingImplementation

Fast, Hierarchical and Fast, Hierarchical and Deterministic ClosureDeterministic ClosureAutomation w/ ECOAutomation w/ ECO

RTL to BitRTL to Bit--stream withstream withIterative ApproachIterative Approach

1X

1X up to 4X

Page 12

ESL Algorithm

IP-Centric Integration with Fast Verification

Processor

SystemPCIe

Memory

Interface

User IP Xilinx IP 3rd Party IP

Display

Processing Datapath

Embedded Interconnect

Memory Interfaces

Hand-coded

VHDL

Vivado HLS

C

Design Time(weeks)

12 1

Latency(ms)

37 21

Memory(RAMB18E1)

134 (16%) 10 (1%)

Memory(RAMB36E1)

273 (65%) 138 (33%)

Registers 29686 (9%) 14263 (4%)

LUTs 28152 (18%) 24257 (16%)

IP & SystemIP & System --centriccentricIntegration with FastIntegration with Fast

VerificationVerification

IP Assembly

ESL Algorithm� IP Synthesis

IP & HW-SWIntegrator

Stds BasedIP Reuse

Fast Simulation & HW Co-Sim

ISimVivado

Runtim

e

w/ HW Co-sim

Tcl SDC

Page 13

Package Designs into System -Level IP for Reuse

IP Packager

Source (C, RTL, IP, etc)

Simulation Models

Documentation

Example Designs

Test Bench

Vivado IP Integrator

Standardized IP-XACT representation

Xilinx IPXilinx IP

33rdrd Party IPParty IP

User IPUser IP

Share IP within your team, project or company

3rd party IP delivered with a common look and feel

Reuse IP at any point in the implementation process– Source, placed, or placed and routed

Reuse in different designs

Reuse multiple times

Vivado IP Integrator

� A graphical design environment to enable rapid and accurate connection of complex IP– Connections made at the interface level, not the individual signal level

– Automatic setting and propagation of IP parameters

– Automated generated of RTL

– Full support for arbitrary levels of design hierarchy

– Capable of processor-based or non-processor based design creation

� Tight integration with Vivado IP Packager flow for rapid IP and subsystem reuse

Vivado HLS C Development

CDT based– Simplified for HLS user

– Windows• MinGW/msys included

– Linux

SystemC libraries included

SystemC libraries included

Video/Image functional verification: 10000x speed versus RTL simulation

Standard Input

Design Specification– Superior language support

• C Easy, familiar• C++ Methodical• SystemC Standard

Directives– Tcl Efficient Exploration– Pragma Self-documenting

Structured Programming

Object Oriented Programming (OOP)

System Modeling

C(C99)

CPP(Standard C++)

OSCI SystemC(IEEE 1666-2005)

Function ClassTemplate (STL)

Module/PortArbitrary precisionParallel processTime (Simulation Kernel)Abstraction (TLM)

DSP Applications

Arbitrary Precision– C

• Simulation and Synthesis

– C++• Rounding and Saturation

void yuv2rgb (

pixel_t *in,

pixel_t *out

) {

uint8 R, G, B;

void yuv2rgb (

pixel_t *in,

pixel_t *out

) {

hls_ufixed<8,8,HLS_RND,HLS_SAT> R, G, B;

hls_fixed<8,8,HLS_RND,HLS_SAT> Y, U, V;

const ap_fixed<11,2,HLS_RND> Wyuv[3][3] = {

{1, 0, 1.13983},

{1,-0.39465,-0.5806},

{1, 2.03211, 0},

};

Y = in->col1;

U = in->col2;

uint8 R, G, B;

int9 C, D, E, Y, U, V;

const int11 Wyuv[3][3] = {

{298, 0, 409},

{298, -100, -208},

{298, 516, 0},

};

Y = in->col1;

U = in->col2;

V = in->col3;

C = Y - 16;

D = U - 128;

E = V - 128;

R = CLIP(( Wyuv[0][0] * C + Wyuv[0][2] * E + 128) >> 8);

G = CLIP(( Wyuv[1][0] * C + Wyuv[1][1] * D + Wyuv[1][2] * E + 128) >> 8);

B = CLIP(( Wyuv[2][0] * C + Wyuv[2][1] * D + 128) >> 8);

out->col1 = R;

out->col2 = G;

out->col3 = B;

}

U = in->col2;

V = in->col3;

R = Wyuv[0][0] * Y + Wyuv[0][2] * V;

G = Wyuv[1][0] * Y + Wyuv[1][1] * U + Wyuv[1][2] * V;

B = Wyuv[2][0] * Y + Wyuv[2][1] * U ;

out->col1 = R;

out->col2 = G;

out->col3 = B;

}

DSP Applications

HPC Applications

Floating-Point– Performance

– Latency

#include "fir.h"

IEEE 754Compliance

Full

AllocatedVectorization

data_t fir(data_t x) {

const coef_t c[N] = {

#include "fir.inc"

};

// Delay line has extra delay at input

static data_t z[N];

acc_t acc = 0;

int i,j;

taps: for (i = N-1; i >= 0; i--) {

z[i] = (i==0) ? x : z[i-1];

acc += z[i] * c[i];

}

return acc;

} typedef float coef_t;

typedef float data_t;

typedef float acc_t;

FullVectorization

FPGA Motor Solutions


Different Electrical Motors

Brushless DC (BLDC)

Permanent Magnet Synchronous Motor

Stepper Motors (hybrid)

Xilinx solution today

DC motors

uC easy play

Induction Motor Reluctance

Xilinx additional solution in future

Xilinx Motor Control Reference Design Features

Networking support – Industrial Ethernet, CAN and other protocols

– Zero impact on motor control performance

Resource efficient, high resolution space vector mo dulation– Any custom modulation for high efficiency and high performance

– Switching of modulation waveforms on the fly

Scalable solution for – DC, BLDC, PMSM and Stepper motors

– Supports up to four DC, two BLDCs/PMSMs or two Stepper motors per daughter card

Number of motors only limited by FPGA size

Xilinx Motor Control PlatformsHardware Configurations Supported

Base board hosting maintenance and communication functio n– Xilinx Spartan-6 LX45 Development Kit (SP605) or

– Xilinx Spartan-3A DSP 3400A Development Platform Kit or

– Avnet Spartan-6 LX150T Development Kit

Qdesys FMC daughter card implementing motor controlQdesys FMC daughter card implementing motor controlfunctions

– 2 Full H-Power Bridges,

– 2 Ethernet Physical Layer interfaces @ 10/100/1000 Megabits

– 5 Sigma-Delta high speed analog to digital converter and Sinc3 filter,

– 8 Digital Output with insulation capability @ 24Volts,

– 8 Digital Inputs @ 24 Volts,

– 2 Incremental Encoder Interfaces,

– Spartan-XC3S50AN interface device

Base Board Design Block Diagram

FMC FMC

Interrupt Controller

Timer/Counter

MicroBlazeMPMC

UART

Ethernet MAC

DDR2DDR2

PLBEthernet MAC

SPARTAN

XC6SLX45

FMC

Connector

FMC

Connector

Serial LinkSerial Link

CAN

USB

Xilinx Motor

Control IP

Xilinx Motor

Control IP

USB

Transceiver

USB

Transceiver

= Xilinx‘ standard IP library

= dedicated motor control IP library

Xilinx Motor

Control IP

Xilinx Motor

Control IP

CAN

NETMOT Daughter Card System Block Diagram

RS485 Transceiver

RS485 Transceiver

10/100/1000 Transceiver

10/100/1000 Transceiver

Σ-∆ADC

H bridge

Current measurement

Σ-∆

H bridge

FMC

Σ-∆ADC

EthernetRS485DC_Link MotorCoil

MotorCoil

High Speed Serial Link

ADI strong position

CAN Transceiver

CAN Transceiver

8 Digital

Output @24V

8 Digital

Inputs

@24V

SPARTAN

XC3S50AN

Σ-∆ADC

Current measurement

Σ-∆ADC

H bridge

Current measurement

Σ-∆ADC

H bridge

Current measurement

Connector

Encoder 1 Encoder 2

MotorCoil

MotorCoil

CAN Bus Incremental Encoders Field I/O

8 LED

Xilinx Motor Control Reference DesignFOC for PMSM (Permanent Magnet Synchronous Motor) and BLDC

Ethernet

PHY


Tim

er/C

ounter

MicroBlazeprocessor

Watch D

og

PL

BI/F

Clo

ck

PL

B B

US

MPMCDDR / DDR2

FO

CF

OC

Control

Ethernet

PHY

P L B B U S

TEMAC

TEMAC

Bridge

PW

M

Bridge

PW

M

ADI strong position

Crystal

Oscillator

DCMclock

management

Watch D

og

DC_Bus Voltage

CAN

AD

Cs

Co

ntr

olle

r

Σ∆Sinc3

Acquisition

Stator

Current

Stator

Current

Σ∆Sinc3

Σ∆Sinc3

Σ∆Sinc3

Σ∆Sinc3

Stator

Current

Stator

CurrentEncoder Filter X-4 Accumulator

Filter X-4 AccumulatorEncoder

Position and Angle

PHY

RS485

Digital I/O FilterDigital Output

Digital

Input

I/O

UART

CAN

Networking

PW

M

Base board

Daughtercard

Xilinx Motor Control Reference DesignFOC for STEPPER allows finer Torque Control

H- Bridge

PW

M

H- Bridge

PW

M

H- Bridge

PW

M

Ethernet

PHY


Tim

er/C

ounter

MicroBlazeprocessor

Watch D

og

PL

BI/F

Clo

ck

PL

B B

US

MPMCDDR / DDR2

FO

CF

OC

Control

Ethernet

PHY

P L B B U S

TEMAC

TEMAC

ADI strong position

H- Bridge

PW

M

Crystal

Oscillator

DCMclock

management

Watch D

og

CAN

AD

Cs

Co

ntr

olle

r

Σ∆Sinc3

Acquisition

Stator

Current

Stator

Current

Σ∆Sinc3

Σ∆Sinc3

Σ∆Sinc3

Σ∆Sinc3

Stator

Current

Stator

CurrentEncoder Filter X-4 Accumulator

Filter X-4 AccumulatorEncoder

Position and Angle

PHY

RS485

Digital I/O FilterDigital Output

Digital

Input

I/O

UART

CAN

Networking

Base board

Daughtercard

DC_Bus Voltage

Xilinx Motor Control IP LibraryFOC (field oriented control) HDL Block Diagram – 5us full loop @50Mhz a 15x of uC

Id

Iq

V a,b,c

QDESYS NETMOT Daughter Card

� Features– Two 10/100/1000 Ethernet interfaces

– Multi-channel Analog Sigma Delta acquisition – Measurement of stator’s currents and motor’s bus voltage

– Sinc3 filter and high speed data link.

– Device DNA unique identifier – Motor identifier for remote maintenance. – Motor identifier for remote maintenance.

– Isolation barrier between the power and the control

– Two power bridges supporting permanent magnet motors (PMSM, BLDC, Stepper)

– Legacy communication like Profibus® or RS485 and CAN.

� Supports multiple hardware platforms‒ AVNET ® Xilinx® Spartan®-6 IEK

‒ Spartan-6 FPGA SP605 Kit

‒ Spartan-3 VSK

‒ Price 860Euro

XILINX MOTOR CONTROL LIBRARYThe LEGO® concept an extensible pipeline

•Basic Building Blocks

•15 Control Functions

•Every function stand-alone

•DSP48 centric

•Dynamic operation

•Minimum foot-print

•Start/Finish Lego®mechanism•Start/Finish Lego®mechanism

•Allows simple wrapping

•Extensible concept

•Full parallelism

•Full DSP48 precision

•48bit operations

•18bit precisions

•Interpolated Sin/Cos/Atan2

•15 Times faster than uC

•Freescale® 55us@96Mhz

•Xilinx-QDESYS IP 5us@50Mhz

FOC PID CLARK PARK PWM-SVM

ATAN2 SIN/COS Rect2Pol Encoder IIR

FULLY DOCUMENTED IP

Customer can know, understand, estimate and use

IP USE MODELA start / finish pipeline mechanism allows full parallelism and extension

x_iny_instart

finish

x_outy_out

CLARK

x_iny_in

startfinish

x_outy_out

PARK

x_iny_in

startfinish

x_outy_out

Atan2

Pipelined

Inputs Outputs

x_in x_out

Wrapper

x_iny_in

startfinish

x_outy_out

Rect2Pol

Parallel

FULL SOFTWARE STACKThe Application is controlled as layered oriented model in S/W

Microblaze (no O.S.)

RS232 Back Door UDP/IP -100Mb

Storage Buffer

UDP/IP -100Mb

C# layer profile – communication- xml interpreter

XML Database Data entry

GUI National Instruments Lab Studio

Sof

twar

e

PC

Microblaze UDP/IP Agent•House-keeping

•Initialization•IP Registers mapping

•IP Registers I/O

•HAL (Hardware Abstraction Layer)•Multiple IP instances•Consistent S/W view2

3

Hw

Hw Drivers (I/O)

Motor control IP blocks

HAL (hardware abstraction layer)

HD

L

•Consistent S/W view•Easy Migration to Zynq

•Realtime Signal Acquisition•Current, Voltages, Angles

•Allow Re/Im display realtime•Allow Postprocessing

•Observers•New Algorithms

•XML Database•Motors description•Board calibration

FULL S/W STACK & Labview® GUI

1

2

1-2-3 = Source code Software on board with UDP/IP Agent

SOFTWARE STACK AS PLUG -INEasy plug-in all modules decoupled MC performances unaffected



Microblaze

RS232 Back Door CAN

Storage Buffer

HD

L

Software

•Customer can strip the GUI•Bare bone application

•Plug the I/F (example CAN)•Field bus adaptation layer

•MC performances unaffected

Hw

Hw Drivers (I/O)

HD

L

•Testing in new environment

MOTOR CONTROL IP ZYNQ FRIENDLYThe layered architecture allows the exploitation of the Zynq environment

DMA

C++ layer profile – communication- xml interpreter

XML Database Data entry

GUI Qt

Sof

twar

e

Zynq

LINUXCAN A

CPEthernet

•Zynq can open to new applications•Motor Control fully independent

•Acceleration profile via S/W•Motion Control

•NURBS•Neon processor

•Up to 16 axis•CNC

Hw

Hw Drivers (I/O)



DMA

HD

L

Zynq

Hw Hw Hw Hw Hw Hw

Motor

2

Motor

3

Motor

4

Motor

5

Motor

6

Motor

7

Motor

2

•CNC•RS274NGC language

GUI with LabstudioNetmot V2.0 and AVNET-AES-FMC-MC1-G

� ON-LINE DOCUMENTATION –

� 2 MODALITIES� ‘DEMO’ beginner

� ‘EXPERT’ full control

� AQUISITION MODE

� Currents, Voltage, Angles

� On-the-fly switch� On-the-fly switch

� SVM – Sinusoidal

� PWM – RPFM

� PWM frequency

� RPFM repetition

� Vector Space Display

� Diagnosis

� Tuning

� FFT for noise measurement

Demonstration hardware – Block Diagram

SP605*

LX45T

SP605 Power Supply

Bridge

Mod

_Ctr

l

Σ∆Stator Current

EncoderFM

C

Motors

SD_CARD

Interrupt Controller T

imer/

Counter

MicroBlazeprocessor

MPMC

UART

PLB

Encoder

Bridge

Mod

_Ctr

lΣ∆

Stator Current

Encoder

NETMOT Power Supply 9Vdc

FM

C

Motors Power Supply 24Vdc

ETH

ETH

3S50

AN

FOC

PWM/SVPWM

Current

Serial Link

I/O

* Could also be Avnet LX150T Industrial Ethernet kit

Zynq and Motor Control Solution

Zynq -7000 Family Highlights

Complete ARM®-based Processing System– Dual ARM Cortex™-A9 MPCore™, processor centric

– Integrated memory controllers & peripherals

– Fully autonomous to the Programmable Logic

Tightly Integrated Programmable Logic– Used to extend Processing System

7 SeriesProgrammable

Logic

ProcessingSystem

MemoryInterfaces

– Used to extend Processing System

– High performance AXI based Interface

– Scalable density and performance

Flexible Array of I/O– Wide range of external multi-standard I/O

– High performance integrated serial transceivers

– Analog-to-Digital Converter inputs

Software & Hardware Programmable

Common Peripherals

CustomPeripherals

Common Accelerators

Custom Accelerators

CommonPeripherals

ARM®

Dual Cortex-A9 MPCore™ System

Zynq -7000 Industrial Motor Control Application

Embedded World Demos – Part 1

HD Video Processing HD Video Processing SW vs. HW SW vs. HW SobelSobel FilterFilter

PONGPONGReal Time Control LoopReal Time Control Loop

with Video Object Trackingwith Video Object Tracking

UbuntuUbuntu Linux withLinux withMedical Image AccelerationMedical Image Acceleration

(SW vs. HW algorithm)(SW vs. HW algorithm)

with Video Object Trackingwith Video Object Tracking

Cadence Virtual PlatformCadence Virtual PlatformMedical Image Acceleration demoMedical Image Acceleration demo

Embedded World Demos – Part 2

ARM DSARM DS--5 Tools5 ToolsMultiMulti--processor Debug and Traceprocessor Debug and Trace

LauterbachLauterbach Trace32 ToolsTrace32 Tools

Linux + FreeRTOSLinux + FreeRTOSPetaLogix Linux SDK with FreeRTOSPetaLogix Linux SDK with FreeRTOS

LauterbachLauterbach Trace32 ToolsTrace32 ToolsAMP and SMP TraceAMP and SMP Trace

iVeia iVeia Android 2.3Android 2.3Image Processing ApplicationImage Processing Application

Zynq -7000 Extensible Processing Platform Summary

New Scalable Family of Devices– Zynq-7000 EPP device portfolio

– Four devices for a broad range of applications

Industry Standard Design Environments– Well defined SW programming model

– Familiar HW design flow

– Flexible accelerators and IP– Flexible accelerators and IP

– Standard AMBA® AXI interfaces

Broad and Expanding Ecosystem– Tools, OS’s, IP

– Middleware, codecs …

Availability– Z-7020 Sampling Now

– Production 2H CY2012

ZYNQ AND FPGA DELIVERS MODULAR PLATFORMS

Ind.

Net

.In

d.N

et

.U

SB

.

DV

I

I/OI/O

I/OI/O

I/O

I/OI/O

I/OI/O

I/O

I/OI/O

I/OI/O

I/OI/O

I/OI/O

I/OI/O

I/OI/O

I/OI/O

I/O

CPU Module

DVIModule

AnalogModule

I/OModule

I/OModule

MEMSModule

Mot

orM

otor

Motor Control

Pro

cess

Con

trol

ler

ZYNQ

ARTIX

ARTIX

ARTIX

ARTIX

DVI

SDC

Eth

Eth

High Speed Link

Analog Input @24V

Output@24V

Mems

ZYNQ

Motor Contr.

SD

CA

RD

I/O I/O I/OI/O I/O

Mot

or

USB

Zero latency with Gigabit backplane

Pro

cess

Con

trol

ler

•Performance•Personality•Platform

Zynq =

ZYNQ THE PROCESSING ACCELERATOR

A9 Cortex

debug

A9 Cortex

FPU & NEON FPU & NEON

MMU

MMU

32K I- cache32K D-cache

32K I- cache32K D-cache

Snoop Control Unit (SCU)

Application Processing Unit

SDC

Q-SPI 1,2,4,8 bit

Parallel 8-bit NOR/SRAM

NAND 8,16-bit

GPIOx54, x64

UART

UART

USB USB GigE

GigE

SDC Controller

Eth.

USB.

ZYNQ Stable Platform

DDR2

DDR Controller

L2 Cache On Chip Memory

AXGM# x 2General Purpose32-bit AXI Master

AXGS# x 2General Purpose32-bit AXI Slave

AXDS# x 4 AXI Data

32/64-bit Slave

AXCS AXI Coherent 64-bit Slave

Memory Switch

UART

SPI

SPI

I2C

I2C

CAN

CAN

TTC/WDTCore Switch

DMA 8 ch

Comm Backplane

High Speed Channels 1…4Process Data

IEC61131-3 Acceleration

Industrial Networking

Personality

Diagnostic Data

MEMS Acceleration

HMI

Field IF

Custom Platform

ZYNQ AND FPGA DELIVERS MODULAR PLATFORMS

Ind.

Ne

t.In

d.N

et.

SD

CA

RD

US

B.

DV

I

I/OI/O

I/OI/O

I/O

I/OI/O

I/OI/O

I/O

I/OI/O

I/OI/O

I/OI/O

I/OI/O

I/OI/O

I/OI/O

I/OI/O

I/O

CPU Module

DVIModule

AnalogModule

I/OModule

I/OModule

MEMSModule

Mot

orM

otor

Motor Control

SD

CA

RD

Process Control Platform Modular I/O with PersonalityMotor Control

backplane

Overall Xilinx Strategy vs. MCU

MCU OnlyAdvantages

MCU OnlyDisadvantages

• Stuck with drive and decoding logic from MCU vendor

CorrespondingXilinx Strength

Flexibility in optimizing algorithms

• Low cost (~$5)

• Legacy code & tools

• Limited performance

• Limited connectivity –No CAN / Ethernet combo

• May require multiple peripheral chips

SW botttlenecks go away in HW

We have both!

Integration, Integration, Integration!

• Likely to have on-chip Flash and ADC

• No FPGA tools or experience required

• Many CPU architectures to choose from

The World Leader in High Performance Signal Processing Solutions


“xCOMM” FMC Simplified Block Diagram

Frequency

ADL5375 ADL5602

AD9548 AD9523-1ADF4351

LPC

(32 Data + 3 C

LK LV

DS

) FM

C C

onnector (500MH

z)X

ilinx D

evelopment P

latform

RF Out

DAC

16-bit 1250MSPS

AD9122Modulator

400 – 6000MHz20dB Fixed Gain

50 – 4000MHz ADL5605/6

700 - 1000MHz1800 – 2700MHz

π π

Master Clock Out

16 + 1 LVDS Pair @

1000 Mbps500MHz (DDR)

S

S

50MHz Ref Clock

I2C / USB to SPI

SPI

SPI SPI SPI

5V @ 500mA

Tx

RF output power control is accomplished by

adjusting baseband data

Optional Front end

2

0dB0dB

49

Clock Generator /

Sync

Clock distribution

FrequencySynthesizer

ADL5380AD8366AD9643

AD9548 AD9523-1

LPC

(32 Data + 3 C

LK LV

DS

) FM

C C

onnector (500MH

z)D

evelopment P

latform

RFIn`

Slave Clock InSync In

ADC

14-bit 250MSPS

0.25dB Step Size600MHz Bandwidth

Demodulator400 – 6000MHz

Output: 1 – 1000MHzInput: 1 Hz - 750MHz

Output: 35 - 4400MHz

FrequencySynthesizer

16 + 1 LVDS Pair @

500 Mbps250MHz DDR

π Pi network

Solder bump jumperS

S

S

1 LVDSPair

SMA connector

SPI SPI SPI

SPI

SPI

SPI

Power

ADL5523

400MHz to 4000MHz Low Noise AmplifierTuned for frequency

π

RxOptional Front end2

-9dB

Non-SMA connector

ADI provided blocks

ADC

ADC

IQ

Mod

IQ

Demod

DAC

AD

I Developed

HD

L (Verilog)

� FMCCOMMS1-EBZ Board � HDL for connectivity (AXI Master which can source/s ink data) + dual tone DDS� Linux IIO drivers for HDL (data path) and each part on the FMCCOMMS1-EBZ Board (control)� Linux userspace application, to provide basic exampl e of how to use everything� All released as source (schematics, HDL, C Source) under open license, for others to build on� No optional / custom front ends (can use pre-existi ng evaluation boards for PA, LNA, etc)

50

ModDAC

ADI HDMI: Not Just color barson ~45,000 Xilinx Development Boards

� Xilinx boards� Artix EVB

� ADI HDMI Tx ADV7511

� Kintex EVB� KC705 ADI HDMI Tx: ADV7511

� Virtex EVB� ADI HDMI Tx and Rx: ADV7511 and

Not Just Color Bars:

Xilinx AD HDMI test pattern in embedded ROMa commercial ships with every board

ADI HDMI Tx and Rx: ADV7511 and ADV7611

� Zynq EVB� ADI HDMI Tx & Rx ADV7511 and ADV7611

� Zed Board� ADI HDMI Tx ADV7511 and ADI Audio

ADAU1761

51

Reference Design Features Reference Design Benefit

High image quality Compliant to HDMI 1.4,HEAC (ARC), and 3D video

Audio 8-channel Supports stereo or 7.1 surround audio up to 768 kHz., compressed audio including Dolby® Digital, DTS®, and THX®.

Proven Reference Design, HDL, Linux Drivers provided

Reduced Risk: Support for the ADV7511 and ADV7611integrated into Xilinx Tools and support package for ease of use and drives ADI preference

KC705

Security Camera Design

LPC

(32 Data + 3 C

LK LV

DS

) FM

C C

onnector (500MH

z)X

ilinx D

evelopment P

latform

CompOut

VDAC

Low Power, Chip Scale 10-Bit SD/HD Video Encoder

ADV7393

16 + 2 Single ended

I2C

MEMS Omni Directional MicDigital Output

ADMP421

Motor Control for Pan/Tilt

ADuM5230

Reference Design Features

ReferenceDesign Benefit

Standard Linux running on

52

LPC

(32 Data + 3 C

LK LV

DS

) FM

C C

onnector (500MH

z)D

evelopment P

latform

1

Power

MIC

Lens DriverFor Zoom/Focus

AD5808

I2C

AR0331 - 3.1-megapixel, 1/3-inchAptina CMOS Sensor

3 Axis inclinometerADXL345

I2C

16-Bit Temp SensorADT7410

I2C

Standard software, open source camera control application

Linux running on Zynq

Proven Reference Design, HDL, Linux Drivers provided and supported on Web

Risk reduction example software defined radio including high performance analog and RF design capable of Tx and Rx

Lots of ADI parts Allows for multiple distributorregistration opportunities

AD9739A FMC Board

�Application Segments�Broadband

communications systemsCMTS/VOD Xilinx ML605 + AD9739A FMCCMTS/VOD

�Cellular infrastructure �Point-to-point wireless �Instrumentation,

automatic test equipment �Radar, avionics

53

Reference Design Feature s Reference Design Benefit


Customer is provided standard software production ready HDL, Linux device drivers for integration into projects

A dual-port interface with double data rate (DDR) LVDS data receivers supports the maximum conversion rate of 2500 MSPS.

Lowers total power consumption for high data rate transfer

Runs on Standard XilinxML605 and Series 7 boards

FMC connection allows for FAE demos with latest ADI and Xilinx parts distributor Registration opportunities

AD9467 FMC Board

�Application Segments�Wireless Infrastructure

� Emphasis on developingcommon radio platformsserving worldwide 4G deployment Xilinx ML605 + AD9467A FMC

�Test Equipment (Spectrum Analysis)� High performance over broader

bandwidths� “More bits and more speed”

�Defense and Aerospace� Improved dynamic range

supports different radar modesof detection and response

54

Reference Design Feature s Reference Design Benefit




Reduced Risk: Support for the ADV7511 and ADV7611integrated into Xilinx Tools and support package for ease of use and drives ADI preference

FMC Interposers

High Speed DAC and ADC Interposer Benefits SDP FMC Interposer Interposer Benefits

Xilinx ML605 FMC Interposer and AD9649 Eval Board

SDP-FMC Interposer

Xilinx KC705

AD5415 Eval Board

55

High Speed DAC and ADC Interposer Features

Interposer Benefits

Proven Reference Design, HDL, Linux Drivers and sample applications provided and supported on Web


Connects High Speed DACs and ADC evaluation boards to Xilinx Development boards

Connects to over 140 ADI evaluation boards allowing for rapid development of customers applications


FMC connection allows for FAE demos with latest ADI and Xilinx parts

Lots of Demos Multiple Registrationopportunities

SDP FMC InterposerFeatures

Interposer Benefits

Standard software, open source application demo and examples

Linux running on Zynq (Arm) or MicroBlaze Includes tested interface HDL, device drivers

Connects ADI PrecisionEvaluation boards that have SDP connector

Connects to all new SDP boards (estimate 50 new boards/year) allowing FAEs to demonstrate ADI products connected to Xilinx platform


FMC connection allows for FAE demos with latest ADI and Xilinx parts

Lots of Demos Multiple Registrationopportunities

All you can download from wiki.analog.com

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Xilinx Motor Solutions ADI Short June 2012

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