Week 2 Report

7/16/2013

Contents1 Counters..............................................................................................................................................3

1.1 Asynchronous Counters...............................................................................................................3

1.2 Synchronous counters.................................................................................................................5

1.2.1 2-BIT SYNCHRONOUS UP COUNTER.....................................................................................5

1.3 Classification of Counters on the basis of Counting Progress......................................................6

1.3.1 UP/DOWN Counter..............................................................................................................6

1.3.2 UP/DOWN Ripple Counters..................................................................................................6

2 Digital Shift Registers...........................................................................................................................8

2.1 Serial In Serial Out Register (SISO)...............................................................................................9

2.2 Parallel In Serial Out Registers (PISO)..........................................................................................9

3 Back end designing............................................................................................................................11

3.1 Stick Diagram.............................................................................................................................11

3.1.1 Stick diagram properties....................................................................................................11

3.1.2 Rules of Stick Diagram........................................................................................................11

3.1.3 Rule 1.................................................................................................................................11

3.1.4 How to draw stick diagram................................................................................................13

4 Microwind.........................................................................................................................................14

4.1 Example Designs........................................................................................................................15

4.1.1 NAND gate.........................................................................................................................15

4.1.2 AND gate............................................................................................................................16

5 W/L ratio............................................................................................................................................18

FigureFigure 1 Logic Diagram of 2-bit Asynchronous Counter_________________________________________________3Figure 2 Logic Diagram of 2 Bit synchronous Counters__________________________________________________5Figure 3 Logic Diagram of Up/Down Counter_________________________________________________________6Figure 4 an asynchronous up counter_______________________________________________________________8Figure 5 Timing diagram of SISO register____________________________________________________________9Figure 6 4-Bit PISO register______________________________________________________________________10Figure 7 Layers used in Stick diagram______________________________________________________________11Figure 8 Rule 1 representation___________________________________________________________________11Figure 9 Rule 2 representation___________________________________________________________________12Figure 10 Rule 3 Representation__________________________________________________________________12Figure 11 Rule Representation___________________________________________________________________12Figure 12 P diffusion inside N well_________________________________________________________________13Figure 13 an N well____________________________________________________________________________13Figure 14 A PMOS_____________________________________________________________________________13Figure 15 An N diffusion layer____________________________________________________________________13Figure 16 An N-MOS___________________________________________________________________________13Figure 17 NOT gate____________________________________________________________________________14Figure 18 NOT Gate Stick Diagram________________________________________________________________14Figure 19 Pallet_______________________________________________________________________________14Figure 20 Design in the Microwind________________________________________________________________15Figure 21 NAND gate CMOS_____________________________________________________________________15Figure 22 NAND gate___________________________________________________________________________16Figure 23 Timing Diagram of the NAND gate________________________________________________________16Figure 24 AND gate using CMOS__________________________________________________________________16Figure 25 AND gate by CMOS____________________________________________________________________17Figure 26 Clock wizard__________________________________________________________________________17Figure 27 Timing diagram of AND gate_____________________________________________________________17

1 COUNTERS

Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Counters can be classified into following types:-

1.1 ASYNCHRONOUS COUNTERSThe logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are being used. But we can use the JK flip-flop also with J and K connected permanently to logic 1. External clock is applied to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop i.e. FF-B.

Counters

Based on Clock input

Synchronus Counters

Asynchronous Counters

Based on counting Progress

Up Counter Down Counter Up Down Counter

Figure 1 Logic Diagram of 2-bit Asynchronous Counter

S.N. Condition Operation

1Initially let both the FFs be in the reset state

QBQA = 00................initially

2 After 1st negative clock edge

As soon as the first negative clock edge is applied, FF-A will toggle and QA will be equal to 1.QA is connected to clock input of FF-B. Since QA has changed from 0 to 1, it is treated as the positive clock edge by FF-B. There is no change in QB because FF-B is a negative edge triggered FF.

QBQA = 01................After the first clock pulse

3 After 2nd negative clock edge

On the arrival of second negative clock edge, FF-A toggles again and QA = 0.The change in QA acts as a negative clock edge for FF-B. So it will also toggle, and QB will be 1.

QBQA = 10................After the second clock pulse

4 After 3rd negative clock edge

On the arrival of 3rd negative clock edge, FF-A toggles again and QA become 1 from 0.Since this is a positive going change, FF-B does not respond to it and remains inactive. So QB does not change and continues to be equal to 1.

QBQA = 11................After the third clock pulse

5 After 4th negative clock edge

On the arrival of 4th negative clock edge, FF-A toggles again and QA become 1 from 0.This negative change in QA acts as clock pulse for FF-B. Hence it toggles to change QB from 1 to 0.

QBQA = 00................After the fourth clock pulse

1.2 SYNCHRONOUS COUNTERSIf the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is called as synchronous counter.

1.2.1 2-BIT SYNCHRONOUS UP COUNTERThe JA and KA inputs of “FF-A” are tied to logic 1. So FF-A will work as a toggle flip-flop. The JB and KB inputs are connected to QA.


1 Initially let both the FFs be in the reset state QBQA = 00................initially

2 After 1st negative clock edge

As soon as the first negative clock edge is applied, FF-A will toggle and QA will change from 0 to 1.But at the instant of application of negative clock edge, QA, JB = KB =0 Hence FF-B will not change its state. So QB will remain 0.

QBQA = 01................After the first clock pulse

3 After 2nd negative clock edge

On the arrival of second negative clock edge, FF-A toggles again and QA change from 1 to 0.But at this instant QA was 1. So JB = KB=1 and FF-B will toggle. Hence QB changes from 0 to 1.

QBQA = 10................After the second clock pulse

4 After 3rd negative clock edge

On application of the third falling clock edge, FF-A will toggle from 0 to 1 but there is no change of state for FF-B.

QBQA = 11................After the third clock pulse

5 After 4th negative clock edge

On application of the next clock pulse, QA will change from 1 to 0 as QB will also change from 1 to 0.

QBQA = 00................After the fourth clock pulse

Figure 2 Logic Diagram of 2 Bit synchronous Counters

1.3 CLASSIFICATION OF COUNTERS ON THE BASIS OF COUNTING PROGRESS

Depending on the way in which the counting progresses, the synchronous or asynchronous counters are classified as follows:-

Up counters Down counters Up/Down counters

1.3.1 UP/DOWN CounterIn the up/down counter, when up counter and down counter combined together to obtain an UP/DOWN counter. A mode control (M) input is also provided to select either up or down mode. A combinational circuit is required to be designed and used between each pair of flip-flop in order to achieve the up/down operation.

Type of up/down counters UP/DOWN ripple counters UP/DOWN synchronous counters

1.3.2 UP/DOWN Ripple CountersIn the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every other FF is obtained from (Q = Q bar) output of the previous FF. UP counting mode (M=0) - The Q output of the preceding FF is connected to the clock of the next stage if up counting is to be achieved. For this mode, the mode select input M is at logic 0 (M=0). DOWN counting mode (M=1) - If M =1, then the Q bar output of the preceding FF is connected to the next FF. This will operate the counter in the counting mode.

EXAMPLE:-

3-bit binary up/down ripple counter. 3-bit: hence three FFs are required. UP/DOWN: So a mode control input is essential. For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next

one. For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next

one. For a ripple down counter, the Q bar output of preceding FF is connected to the clock input of

the next one. Let the selection of Q and Q bar output of the preceding FF be controlled by the mode control

input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1, DOWN counting. So connect Q bar to CLK

Figure 3 Logic Diagram of Up/Down Counter


1 Case 1: With M = 0 (Up counting mode)

If M = 0 and M bar = 1, then the AND gates 1 and 3 in fig. will be enabled whereas the AND gates 2 and 4 will be disabled.Hence QA gets connected to the clock input of FF-B and QB gets connected to the clock input of FF-C.These connections are same as those for the normal up counter. Thus with M = 0 the circuit work as an up counter.

2 Case 2: With M = 1 (Down counting mode)

If M = 1, then AND gates 2 and 4 in fig. are enabled whereas the AND gates 1 and 3 are disabled.Hence QA bar gets connected to the clock input of FF-B and QB bar gets connected to the clock input of FF-C.These connections will produce a down counter. Thus with M = 1 the circuit works as a down counter.

2 DIGITAL SHIFT REGISTERS

Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and it is capable of storing an n-bit word. The binary data in a register can be moved within the register from one flip-flop to another. The registers that allow such data transfers are called as shift registers. There are four mode of operation of a shift register.

Serial Input Serial Output Serial Input Parallel Output Parallel Input Serial Output Parallel Input Parallel Output

Figure 4 an asynchronous up counter

Shift Registers

Serial input

Serial In Serial Out

Serial in Parallel Out

Parallel input

Prallel In Serial Out

Parallel In Parallel Out

2.1 SERIAL IN SERIAL OUT REGISTER (SISO)As shown on Figure 4 a Serial Input Serial output digital register, the input is given in serial fashion and output is taken in serial fashion as well.

As shown above in Figure 5 a timing diagram of SISO register, the first wave form is of clock, second one is data and the last is the output, as you can see, whatever the data is given is reflecting in output after sometime, this is because of the delay of the register, in the figure the data is 1010 which is reflecting in the output after the data entry is completed.

2.2 PARALLEL IN SERIAL OUT REGISTERS (PISO)In this type of register the input data is given in parallel fashion, and the output is taken in the serial fashion. There are two modes on which this register works:-

Shift Mode => This mode is for shifting the data from one register to another


1 With M = 1 : Shift right operationIf M = 1, then the AND gates 1, 3, 5 and 7 are enable whereas the remaining AND gates 2, 4, 6 and 8 will be disabled.The data at DR is shifted to right bit by bit from FF-3 to FF-0 on the application of clock pulses. Thus with M = 1 we get the serial right shift operation.

2 With M = 0 : Shift left operationWhen the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are enabled while 1, 3, 5 and 7 are disabled.The data at DL is shifted left bit by bit from FF-0 to FF-3 on the application of clock pulses. Thus with M = 0 we get the serial right shift operation.

Load Mode => this mode is for loading the data into the register

Figure 5 Timing diagram of SISO register

A 4bit PISO register and is time flow diagram is shown below in the figures:-

In this type of register a multiplexer is used, so as to switch between the output of Flip-Flop and the input data, the switch decides the mode of the register. This is made by using 3 multiplexer and 4 flip flop.

3 BACK END DESIGNING The back end designing refers to design the particular circuit verified by the HDL or Verilog finally in the silicon wafer, there are several EDA tools available for designing, like Microwind, cadence, L edit etc. we will use Microwind for this purpose.

Figure 6 4-Bit PISO register

3.1 STICK DIAGRAM Stick diagram is the representation of the layout of the digital circuit on the silicon wafer, it uses different colors to represent different layers of whole layout.

3.1.1 Stick diagram properties Does show all components/Vias. It shows relative placement of components. Goes one step closer to the layout Helps plan the layout and routing

In essence we can say that a stick diagram is a cartoon of the circuit diagram.

3.1.2 Rules of Stick Diagram

3.1.3 Rule 1.When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact

3.1.3.1Rule 2When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).

Poly

Figure 7 Layers used in Stick diagram

Poly

P diffusion

N-diffusion

Metal 1

Figure 8 Rule 1 representation

3.1.3.2Rule 3When a poly crosses diffusion it represents a transistor.

3.1.3.3Rule 4In CMOS a demarcation line is drawn to avoid touching of P-diffusion with N-diffusion. All P-MOS must lie on one side of the line and all N-MOS will have to be on the other side.

Figure 10 Rule 3 Representation

Figure 11 Rule Representation

3.1.4 How to draw stick diagram As we know CMOS abbreviated for Complementary Metal oxide semiconductor, it means it contain both NMOS and CMOS in one substrate, so as to make circuit diagram some steps have to be considered, these steps are

3.1.4.1Steps to draw a PMOSFor implementing a PMOS-

Step1:- Design an N-well Step2:- Insert a P-diffusion in the well Step3:- draw a polyvinyl gate Step4:- finally allocate source and drain

3.1.4.2Steps to Draw a NMOSFor Implement a NMOS-

Step1:- Draw an N-diffusion Step2:- draw a polyvinyl gate Step3:- finally allocate source and drain

Figure 12 an N well

N well

Figure 13 P diffusion inside N well

P diffusion inside the N- well

Figure 14 A PMOS

As in Figure 14 a PMOS having a Source, Drain and a Gate is shown, the layers are shown in Figure 7. The source and Drain can be interchange accordingly.

Figure 15 An N diffusion layer

N Diffusion

Figure 16 An N-MOS

3.1.4.3Example Designing stick diagram of a Not gate:-

This is how a Stick diagram can be designed.

4 MICROWIND

Microwind is an EDA tool to design Stick diagram of the CMOS circuits, technically saying this software is used by Back End Designers to design a digital CMOS circuit on a silicon wafer. We will be using Microwind v-3.5 and 22n rule to design the circuits.

This part of designing will be limited to simulation only because it not possible to design an IC anywhere.

All the tools of the Micro-wind are same except its pallet, Pallet is a replacement of symbol library in DSCH. Every option of Pallet is described below: -

Starting from Down to up the functions are explained below: -

N-well: -When on the P substrate we create a hole of N type layer then it is known as N well.

N+ diffusion: - Highly doped N element use to make N-MOS.

P+ diffusion: - Highly doped P element use to make P-MOS.

Poly-silicon: - Used to make gate of CMOS device, 1 and 2 refers to the layers of gates.

Contact: - Metal contacts.

Metal1-6: - For make connection, 1 to 6 define layers.

Option layer: - To define our own layer.

Figure 17 NOT gate Figure 18 NOT Gate Stick Diagram

Shorted drain

N-MOS

P-MOS

Shorted drain

P-MOS

N-MOS

Shorted Gates

Shorted Gates

Figure 19 Pallet

The above symbols are for VDD, VSS, CLOCK and OUTPUT respectively. Out of all these things there one more thing we need to know is about rules of VLSI. The rules of designing are categories by the level of miniaturization of design. The latest is 22nm design rule and others are 45nm, 6µm etc.

The latest version of Micro-Wind supports 22nm design rules. In Micro-Wind design rules are scaled by lambda, Lambda is scaled such that it fulfill the requirement of all design rules. Design rules can be changed as technology improved.

Now it’s the time for our first design, for that follow some screenshots and it is done.

Note in upper left corner of fig 20 under the white circle there is rating of lambda, which informs about current scale we are using, this changes as design rule changes. And besides that notice each and every part of the design. The metal contacts on the left side of the gate of both N-MOS and P-MOS are source and we are taking output from the drain which is short by the metal layer and now watch the design of NOT GATE shown in Figure 17 and then co relate them in terms of source and drain this is the easiest way to understand this as far as I think.

4.1 EXAMPLE DESIGNS

4.1.1 NAND gate

Figure 20 Design in the Microwind

Figure 21 NAND gate CMOS

A NAND gate is shown on the diagram and its stick diagram is shown below in Figure 22, note that how drain of two PMOS is considered in one metal contact, this is how space can be reduces to the lowest level.

4.1.2 AND gate

Drai

Figure 22 NAND gate

As shown in the figure the input clock is given in gates, now for checking its performance we will simulate is and have a look on its timing diagram.

Figure 23 Timing Diagram of the NAND gate

This is timing diagram of the NAND gate, the green and white graph are the clocks and the one with red color is our output.

layout is simple, though there are some extra learnings to design the layout as short as possible, however there can be more ways to make it more miniature then the one is shown in Figure 24

Figure 24 AND gate using CMOS

Now let’s look out its response and for that we have to configure the clock as shown below: -

The Figure shows the layout of and gate, the thing to notice is all the PMOS’s are fabricated in the single piece of P-well which eliminate the need of making another P well for another device.

Figure 25 Clock wizard

Figure 26 Timing diagram of AND gate

This is clock diagram of the AND gate, you can see the timing response of the red graph.

5 W/L RATIO

We can optimize this design too by varying W/L ratio of P and N MOS, this is the only factor a designer can vary.

W/L is the transistor length to width ratio. It basically the only transistor parameter that an IC designer will ever be able to change. It’s hard for me to write here the detailed equations so I will just give you some rules of thumb

As W/L increases the current drain-to-source increases. As W/L increases the response time increases. W/L is roughly proportional to the transistors resistance. The PMOS W/L should in any cmos circuit should always 2-3 times as big as the NMOS W/L. If multiple MOS are in series make the ones furthest from the output larger (increase W/L) then the

ones closest to the output. This is called progressive sizing.

This is enough for back end designing, the thing worth notice is, and we make all our back end by referencing DSCH designs (front end), in every case we had our front end and then we design back end, but sometimes it becomes very hard to implement the logic and even if we did then no guarantee it is going to work or not, so for sorting out this problem here is a software which implement hardware for us, all we have to do is to write the logic. The logics are written in VHDL language, which is based in C script. VHDL stands for (VLSI hardware description language).

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