SPIROC update Felix Sefkow Most slides from Ludovic Raux HCAL main meeting April 18, 2007.
W. Shen arXiv:0911.1566v1 [physics.ins-det] 8 Nov...
Transcript of W. Shen arXiv:0911.1566v1 [physics.ins-det] 8 Nov...
arX
iv:0
911.
1566
v1 [
phys
ics.
ins-
det]
8 N
ov 2
009
Overview of Studies on the
SPIROC Chip Chara terisation
R. Fabbri
1, B. Lutz
1, W. Shen
2
1DESY, Hamburg
2University of Heidelberg
September 26, 2013
Contents
1 Introdu tion 2
2 SPIROC ASIC Des ription and Properties 2
3 Test-Ben h Des ription 4
4 Ele tri al Noise Investigation 5
5 ENC and Input Dete tor Capa itan e 8
6 Pedestals Uniformity 11
7 Trigger Dis riminator and E ien y 11
8 Trigger Time Walk and Jitter 14
9 SiPM Voltage Adjustment 17
10 Low Gain - High Gain Coupling 20
11 Cross Talk between Input Channels 21
12 Tra k and Hold Swit h 22
13 Dynami Range, Linearity, and Gain of the ASIC 23
14 Amplitude Dependen e on Shaping Time 28
15 SiPM Single-Pixel Spe tra 30
16 Towards Real Data Taking Conditions 34
17 Con lusions 39
1
1 Introdu tion
The requirements imposed by the high pre ision physi s forseen at the Interna-
tional Linear Collider (ILC) set high demands on alorimetry. The ambitious
required jet energy resolution of σE/E ≈ 0.3/√
E [1 ould be a hieved by om-
bining the potentials of the parti le ow approa h [1 with extremely segmented
(in both transverse and longitudinal dire tions) ele tro-magneti (ECAL) and
hadroni (HCAL) alorimeters.
The ECAL design is based on a Si-W sampling stru ture with sensitive
sili on pads of 1 m
2surfa e. The prototype will onsist of approximately
10000 hannels. A group of the CALICE ollaboration has developed the analog
option for the hadroni alorimeter (AHCAL) based on a sampling stru ture
with s intillating tiles (of smallest size 3x3x0.5 m
3) individually readout by
Sili on Photo-Multiplier (SiPM) mounted on ea h tile.
The SiPM is a pixelated avalan he photo-diode operated in limited Geiger
mode. The dete tor surfa e typi ally of few mm
2is divided into hundreds to
thousands pixels. The analog output is obtained by adding the response of all
pixels ring as independent digital ounters. SiPMs are operated at 2-3 volts
overvoltage. Given an internal pixel apa itan e Cpixel of typi ally 50 fF, the
harge olle ted for one photoele tron signal is approximately 1.2 pC (equivalent
to ≈ 7.5 · 105ele trons). The SiPM oers a very fast response with a typi al
rise time of 3-5 ns. The dynami range is determined by the nite number of
pixels and rea hes ≈ 92 pC.
In order to test the feasibility of the parti le ow approa h prototypes of
both ECAL and HCAL are being built by the CALICE ollaboration and being
tested in a ombined test beam experiment. To meet the needs of the analog
HCAL prototype it was de ided to adapt the design developed for the ECAL
front-end ele troni s to read the SiPM signal. This ILC-SiPM ASIC has been
used during the test-beam runs at CERN and FNAL in 2006-07 and 2008-09,
respe tively. SPIROC is an evolution of the ILC-SiPM to be used for the next
generation of ILC AHCAL prototype. In the following the main features of the
new ASIC, version SPIROC 1B, proposed for the readout are des ribed and its
properties analysed. More spe i ately, the results on the analogue part of the
hip are presented in this work. When reading out signals from photon dete tors,
SiPMs from MEPhy/Pulsar, identi al to the devi es used in the AHCAL test
beam operations, were used. These SiPMs have a 1x1 mm
2surfa e divided into
1156 pixels.
The on going investigation of the digital omponent of the ASIC, imple-
mented in the version SPIROC 2, will be presented in a separate future note.
2 SPIROC ASIC Des ription and Properties
The SPIROC hip is a dedi ated very front-end ele troni s for an ILC prototype
hadroni alorimeter with sili on photomultiplier readout. This ASIC has been
designed and developed by OMEGA at Orsay [2.
2
Figure 1: SPIROC: one analog hannel stru ture.
SPIROC was submitted in Fall 2007 and being tested sin e then. It em-
beds utting edge features that full ILC nal dete tor requirements. It has
been realised using AMS 0.35 µm SiGe te hnology, and developed to mat h
the requirements of large dynami range, low noise, low power onsumption,
high pre ision and large number of readout hannels needed. SPIROC is an
auto-triggered, bi-gain, 36- hannel ASIC whi h allows to measure on ea h han-
nel the harge from one to 2000 photoele trons and the signal timing with a
100 ps a ura y TDC. The integrated ASIC omponents allow 16 sele table
pre-ampli ation gain fa tors (with output gain values from 3 to 100 mV/pC),
and seven CR(RC)
2shaping times from 25 to 175 ns. After shaping, the signal
is held at its maximum amplitude with a tra k and hold method. For ea h han-
nel, an analogue 16 slots memory array is used to store the time information
and the harge measurement, and a 12-bit Wilkinson ADC has been embed-
ded to digitise the analogue memory ontent (time and harge for the two gain
modes). The data are then stored in a 4 kbytes RAM. A very omplex digital
part has been integrated to manage all theses features and to transfer the data
to the data a quisition system. An adjustable 8-bit DAC (0-4.5 V) in the ASIC
allows individual adjustment of the SiPM forward voltage for ea h one of the
36 hannels.
A s hemati view of a single hannel of the ASIC hip is given in Fig. 1.
3
hold
ASICpulse generator
50Ω
−20dB
100 pF
STS DG 535
ADC module
CAEN V785N
gategenerator
bufferamplifier1x or 9x
VME CAEN 8002
Figure 2: Typi al test ben h set up for the ommissioning of the SPIROC hip
at DESY.
3 Test-Ben h Des ription
The hara terisation measurements of the SPIROC hip were performed at
DESY. The typi al set up of the test ben h is shown in Fig. 2. A digital
pulse voltage generator (STS DG535) provides a re tangular signal at 10 kHz
rate and with variable amplitude up to 4 V. Additionally, a 20 dB attenuator
(10 fa tor attenuation) is inserted in the signal line. To simulate a real urrent
signal from SiPMs, the generated squared signal is driven through a oupling
apa itor (C = 100 pF) and a resistor (R = 50 Ω) lo ated before the input han-nels in the SPIROC board, resulting in a hara teristi de ay time τ = 5 ns for
the urrent signal.
The signal is then inje ted in one of the 36 input hannels, and the pro essed
4
output signal an be measured either at the os illos ope (Tektronix TDS 3034B,
running at 300 MHz bandwidth with 2.5 Gs/s sampling rate) or dire tly via an
external ADC module (CAEN V 785N), a ommodated in a VME reate (CAEN
8002). The data a quisition is performed via a LINUX ma hine onne ted to
the VME rate. The pulse generator is also onne ted to the LINUX ma hine,
and is driven by s ripts, allowing, together with the a quisition, for automati ,
exible, and systemati measurements in a large parameters spa e using SHELL
s ripts. Via an USB onne tion the hip is driven by a LabView user interfa e
running under WINDOWS be ause the USB driver to steer the hip is not
available for LINUX systems. This restri ts the automation and exibility of
the measurements performing the s an of the ASIC related parameters. The
porting of this software to a LINUX platform is ongoing.
A buer amplier, built at DESY, was often used (before the ADC input
hannels) to improve the pre ision of the measurement, as in the noise studies.
4 Ele tri al Noise Investigation
The noise ae ting the pro essed signal out of the board was measured at dif-
ferent working onditions of the hip. Additional sour es an superimpose to
the hip noise during the measurement, as the USB- onne tion to the omputer
driving the board, the lo k on the board whi h handles the input/output om-
muni ations with the omputer, and the onne tions to the pulse generator for
the input and hold signals.
After dis onne ting these additional noise sour e from the board, the noise
was measured as the RMS of the analogue output signal. The dependen e of the
noise on the variable apa itan e in the preamplier stage of the hip is shown
in Fig. 3, for both high and low gain operation modes. The expe ted 1/Cgain
dependen e in the high gain mode is observed. The noise rea hes its asymptoti
value for the largest feedba k apa itan e investigated value. For the low gain
mode, where the ampli ation is one order smaller than for the high gain mode,
no dependen e is visible, being the noise dominated by the either the hip or the
experimental board (the noise from the external ADC module was measured to
be up to 0.1 mV).
The dependen e of the hip noise on the shaping time values is presented in
Fig. 4. An almost linear dependen e in the high gain mode is observed, while
for the low gain mode no dependen e is visible, similarly to what observed for
the dependen e on the feedba k apa itan e.
The uniformity of the noise in the SPIROC 36 input hannels was also in-
vestigated, and the result of the measurement is presented in Fig. 5, for the
hip operating in high gain mode, at 50 ns shaping time, and 400 fF variable
apa itan e in the pre-amplier stage. The measured noise is uniform within
fra tions of millivolts, well enough for the hip purposes. Although the upper
half of hannels appears to have a higher noise, this feature was not furtherly
investigated being the ee t negligible.
The largest ee t superimposed to the ele tri al noise is given by using the
5
[fF]gainC0 200 400 600 800 1000 1200 1400 1600
no
ise
(o
utp
ut R
MS
) [m
V]
0
0.2
0.4
0.6
0.8
1
1.2
1.4
High Gain
Low Gain
Figure 3: The hip noise is measured versus the variable apa itan e in the
preamplier stage, for 50 ns shaping time.
Shaping time [ns]0 20 40 60 80 100 120 140 160 180 200
no
ise
(o
utp
ut R
MS
) [m
V]
0
0.2
0.4
0.6
0.8
1
1.2
1.4
High Gain
Low Gain
Figure 4: The hip noise is measured versus the shaping time for 400 fF variable
apa itan e in the preamplier stage.
tra k and hold swit h to hold the pre-amplied and shaped signal at its peaking
amplitude. An in rease of the noise up to a fa tor 2-3 is observed in the output
signal, Fig. 6. With the used setup we ould not distinguish between an in rease
of the noise or of the sensitivity to the noise (due to the in reased bandwidth
6
Input channel0 5 10 15 20 25 30 35
no
ise
(o
utp
ut
RM
S)
[mV
]
0.39
0.4
0.41
0.42
0.43
0.44
0.45
0.46
High Gain mode
50 ns shaping time
400 fF variable capacitance
Figure 5: The noise is measured independently for all the 36 input hannels of
the hip in high gain mode.
Entries 100002
Mean 76.07
RMS 0.3972
Pedestal [mV]60 65 70 75 80 85 90 95
Yie
ld
0
2000
4000
6000
8000
10000 Entries 100002
Mean 76.07
RMS 0.3972
Entries 100000
Mean 75.39
RMS 0.9843
Entries 100000
Mean 75.39
RMS 0.9843
High Gain
Shaping time: 50 ns
Feedback capacitance: 400 fF
High Gain
Shaping time: 50 ns
Feedback capacitance: 400 fF
High Gain
Shaping time: 50 ns
Feedback capacitance: 400 fF
With T. & H.: Without T. & H.:
Figure 6: The hip pedestal and noise are measured in high gain mode for 50 ns
shaping time and 400 fF feedba k apa itan e. The distributions were obtained
separately while keeping the tra k and hold omponent swit hed on and o
(hat hed and lled histograms, separately). The USB onne tion to the driving
PC, and the internal lo k were left on during these measurements.
indu ed by the tra k and hold swit h). Instead, a negligible ee t is observed
by the swit hing on the internal lo k for input/output ommuni ation with an
external driving interfa e (via USB port), and by plugging the USB onne tor
7
Entries 100003Mean 75.68RMS 0.407
Pedestal [mV]73 74 75 76 77 78 79 80
Yie
ld
0
2000
4000
6000
8000
10000Entries 100003Mean 75.68RMS 0.407
Entries 100000Mean 75.94RMS 0.4065
Entries 100000Mean 75.94RMS 0.4065
Entries 100002Mean 76.06RMS 0.4009
Entries 100002Mean 76.06RMS 0.4009
High Gain
Shaping time: 50 ns
Feedback capacitance: 400 fF
High Gain
Shaping time: 50 ns
Feedback capacitance: 400 fF
High Gain
Shaping time: 50 ns
Feedback capacitance: 400 fF
W/O Clock and USB:W/O Clock and W USB:
With Clock and USB:
Figure 7: The hip pedestal and noise are measured while keeping the tra k and
hold omponent swit hed o (lled histogram), and in sequen e plugging the
USB onne tor to the board and swit hing on the internal lo k (striped and
point histograms, separately).
into the board, Fig. 7. In normal data taking onditions the ASIC is supposed
to pro ess the in oming signals via the tra k and hold omponent swit hed on.
Therefore it is important also to measure its impa t on the measured noise
dependen e on the preamplier gain, Fig. 8. Consistently with what shown in
Fig. 6, an in rease of the noise up to approximately a fa tor 3 is observed at
Cgain = 1500 fF.
5 ENC and Input Dete tor Capa itan e
Sofar the ele tri al noise of the stand-alone ASIC was investigated, without any
input signal line onne ted to the board. Conne ting a SiPM to the readout
system is expe ted to in rease the noise, depending on the dete tor apa itan e.
In prin iple, a harge-sensitive preamplier would be favoured [5, providing
small sensitivity to hanges of the parasiti apa itan e at its input, as in the
ase of SiPMs whose apa itan e hanges with temperature. Nevertheless, in
order to over the large dynami range of SiPMs, a voltage-sensitive preamplier
was adopted for the hip. It is ru ial therefore to quantify the noise sensitivity
to an external variable apa itan e oupled via the onne ted dete tor.
Sin e the signal from the SiPM appears as ele tri harge, ele troni noise
will be quantied by giving its 'equivalent noise harge' (ENC), dened as the
input harge whi h would be ne essary to generate a signal equivalent in am-
plitude to the measured noise output of the ASIC. This value an be obtained
by normalising the noise to a referen e signal. As an example, the signal origi-
8
[fF]gainC0 200 400 600 800 1000 1200 1400 1600
no
ise
(o
utp
ut R
MS
) [m
V]
0.5
1.0
1.5
2.0
2.5
High GainHigh Gain
Figure 8: The hip noise is measured versus the variable apa itan e in the
preamplier stage keeping the tra k and hold omponent swit hed o. The hip
was operated in high mode at 50 ns shaping time.
nating from one photo-ele tron in the SiPM, and its orresponding output are
onsidered. Assuming a SiPM gain GSiPM of order 5 · 105would result in an
input harge Qin approximately of GSiPM · e = 80 fC. The orresponding out-
put signal Vout for the highest gain was found to be ≈ 7.6 mV (see Se . 16),
obtaining an ENC of order
ENC = VRMS ·Q1pxl
in
V 1pxlout
= VRMS ·80
7.6≈ VRMS · 10.5 [fC · mV −1]. (1)
Here VRMS is the average voltage noise level (in millivolt) appearing at the
output. Dividing it by the the ele tron harge e (in femto oulomb units) gives
the ENC in number of ele trons
ENC = VRMS ·10.5
1.6 · 10−4≈ VRMS · 7 · 104 [electrons · mV −1]. (2)
Using the external pulse generator, the output noise was measured and on-
verted in number of equivalent ele trons following the above formula (2). Dur-
ing the measurement, the oupling apa itan e value was varied to simulate the
hange of the SiPM internal apa itor. The results of two s ans performed in
sequen e, without any hange in the setup apart repla ing the apa itor, are
presented in Fig. 9, showing a noise VRMS in rease up to 20% in the range
0-100 pF, from 1.6 to 2.1 mV ( orresponding to an ENC variation from 9 ·104to
11.5·104ele trons). A ording to these measurements, the signal over noise ratio
a hievable by the SPIROC an be al ulated, ranging approximately between
4.7 and 3.6 assuming a SiPM of 5 · 105.
9
Input Coupling Capacitance [pF]0 20 40 60 80 100
Ou
tpu
t N
ois
e [m
V]
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
4x10 ]-E
qu
ival
ent
No
ise
Ch
arg
e [e
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
Input charge: 0.5 pC
HG shaping time: 50 ns
HG feedback capacitance: 100 fF
Input charge: 0.5 pC
HG shaping time: 50 ns
HG feedback capacitance: 100 fF
Input charge: 0.5 pC
HG shaping time: 50 ns
HG feedback capacitance: 100 fF
Input charge: 0.5 pC
HG shaping time: 50 ns
HG feedback capacitance: 100 fF
Figure 9: Equivalent noise harge measured while varying the oupling apa i-
tan e at the input signal line.
Entries 99Mean 2.103RMS 0.01729
Output Noise [mV]1.5 1.6 1.7 1.8 1.9 2 2.1 2.2
Yie
ld
0
5
10
15
20
25
30
35
40
45
Entries 99Mean 2.103RMS 0.01729
Entries 99Mean 1.65RMS 0.01247
Entries 99Mean 1.65RMS 0.01247
High GainInput charge: 0.5 pCShaping time: 50 nsFeedback capacitance: 100 fF
High GainInput charge: 0.5 pCShaping time: 50 nsFeedback capacitance: 100 fF
High GainInput charge: 0.5 pCShaping time: 50 nsFeedback capacitance: 100 fF
High GainInput charge: 0.5 pCShaping time: 50 nsFeedback capacitance: 100 fF
CC: 10 pF: CC: 100 pF:
Figure 10: Distribution of noise
measurement performed at two
dierent oupling apa itan e
values.
To verify that the observed non-reprodu ibility of the measurements is not
given by any feature of the ASIC, a series of measurements was taken in se-
quen e at a xed oupling apa itan e to simulate the dete tor apa itan e. No
additional hange in the experimental apparatus was introdu ed. The results
for two values of the oupling apa itan e, Fig. 10, shows a spread in the mea-
surement whi h is of the order of a fra tion of millivolt. This is well below the
maximum spread observed in the two onse utive s ans, thus suggesting a noise
sour e external to the ASIC, possibly due to the experimental setup.
The measurement of the oupling apa itan e dependen e of the ENC was
performed inje ting 0.5 pC into the ASIC (ex ept for the measurement at zero
apa itan e, when the line was dis onne ted from the board). To validate the
results it should be veried the reasonable assumption that the measured noise
10
Injected voltage [mV]1 2 3 4 5 6 7 8 9 10
no
ise (
Ou
tpu
t R
MS
) [m
V]
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
High Gain
Shaping time: 50 ns
Feedback capacitance: 100 fF
High Gain
Shaping time: 50 ns
Feedback capacitance: 100 fF
High Gain
Shaping time: 50 ns
Feedback capacitance: 100 fF
CC: 100 pF
CC: 10 pF
Figure 11: The signal noise is measured for dierent values of the inje ted
voltage from the pulse sour e, and for two extreme values of the oupling
apa itan e (CC).
is not inuen ed by the amount of inje ted harge. A measurement of the
noise was taken at dierent values of inje ted harge, and for two values of the
oupling apa itan e, showing, as expe ted, no dependen e, Fig. 11.
6 Pedestals Uniformity
Pedestals were investigated for all the the 36 input hannels of the hip, to verifytheir uniformity, and are presented in Fig. 12, using the external ADC module.
Note that the mean values reported here are not the absolute pedestal values,
due to an oset introdu ed for onvenien e in the amplier before the ADC.
The measured spread of pedestals is about 2.3 mV, Fig. 13, a value slightly
larger than what reported in [2.
7 Trigger Dis riminator and E ien y
The hip is designed to operate in the so alled 'auto-trigger' mode. The input
signals are rst pre-amplied a ording to both low and high gain line settings.
In the high gain se tion a dedi ated 15 ns fast shaping line is also present in
parallel to the line to the analogue memory. There the signal enters a dis rimi-
nator with a threshold ommon to all 36 input lines, and a 120 ns wide trigger
is generated whenever the voltage in the line is above the threshold value set,
11
Channel number0 5 10 15 20 25 30 35
pe
de
sta
l (o
utp
ut
me
an
) [m
V]
50
60
70
80
90
100
High Gain mode
50 ns shaping time
400 fF variable capacitance
Figure 12: Pedestals measured for all the 36 input hannels of the hip, using
the external ADC module.
pedestal (output mean) [mV]60 65 70 75 80 85 90 95 100
Yie
ld
0
1
2
3
4
5
6
7Entries 36
Mean 84.15
RMS 2.302
High Gain
50 ns shaping time
400 fF variable capacitanceFigure 13: Pedestal distri-
bution for all the 36 input
hannels.
Fig. 1. The ommon threshold is tunable by a 10 bits DAC. On top of the
ommon threshold value, ea h hannel threshold an be individually tuned via
a 4-bit DAC.In normal ILC operations the generated trigger is forseen to subsequently
hold the pre-amplied signal, pro essed in the meanwhile by slower shapers, at
its amplitude peaking value. It is therefore ru ial to investigate the trigger
e ien y and homogeneity for the 36 hannels.
The alibration of the ommon DAC values was performed, and is shown in
Fig. 14. The threshold is found to range from 0.35 V up to 2.26 V. The residuals
12
DAC value0 200 400 600 800 1000
Mea
sure
d Vo
ltage
[V]
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2 / ndf 2χ 8.41e-05 / 17
p0 0.001242± 2.262
p1 1.943e-06± -0.001864
/ ndf 2χ 8.41e-05 / 17
p0 0.001242± 2.262
p1 1.943e-06± -0.001864
DAC value0 200 400 600 800 1000R
esid
ual t
o Li
near
ity [m
V]
-10-8-6-4-202468
10
Figure 14: The alibration of the ommon signal threshold 10-bit DAC values
into volt units.
to linearity, found to be within few millivolts (a fra tion of a photon-ele tron
signal), are presented in the small insert panel.
After having performed the dis riminator DAC alibration, the trigger ef-
ien y an be investigated hannel by hannel. This is done using a built-in
pro edure in the LabView user interfa e. The program in reases the threshold
level in sequen e of DAC units, remains at a xed DAC value for 200 y les,
and ounts the number of triggers generated by the pedestal of the investigated
hannel. It provides thus a measurement of the trigger e ien y, whi h is pre-
sented in Fig. 15 for an inje ted harge of 100 fC, separately for ea h of the 36
Discriminator Threshold [mV]
Trigg
er Ef
ficien
cy %
0
20
40
60
80
100
1205 1210 1215 1220 1225 1230 1235
Figure 15: The trigger e ien y spread for all the 36 input hannels in the
ASIC, relative to an inje ted harge of 100 fC.
13
Time jitter
Trigger level
Pedestal
Figure 16: Examples of trigger time walk (left panel) and jitter (right panel).
hannels.
The in rease of the trigger ounting is smoothed by the noise amplitude in
the line, whi h was typi ally found to be around 2-3 mV during that spe i
measurement, and was obtained onsidering the threshold value variation needed
to in rease the trigger e ien y from 10% to 90%. Also, the maximum e ien y
is rea hed at threshold level values dierent from hannel to hannel, with a
spread of around 5 mV, resulting in a negligible pedestal spread between all
the 36 hannels. During forseen data taking operations, the observed spread
an, in prin iple, be ured tuning the dis riminator level hannel by hannel
using the forseen 4-bit threshold ner adjustment. At the moment, this feature
is not properly working in the released versions of the hip (SPIROC 1 and
SPIROC 2), and ould not be investigated.
8 Trigger Time Walk and Jitter
As mentioned in Se . 7, SPIROC is forseen to be used in auto-trigger mode
during ILC running onditions. It is ru ial therefore to investigate the size of
the main un ertainties whi h an ae t the trigger timing. Signals with dierent
amplitudes (and same peaking time) ross the dis riminator level at dierent
times, resulting in a time shift (trigger walk) of the generated pro essing trigger,
left panel of Fig. 16. On top of this un ertainty, the rossing of the dis riminator
level is varied in time (trigger jitter) by the noise in the analogue signal, right
panel of Fig. 16.
The trigger time walk and jitter were investigated inje ting a signal from
the pulse generator, and then measuring at the os illos ope the timing of the
oin iden e of the generated trigger in the hip with the main pulse generator
trigger. Dierent threshold values for the analogue signals were set (via the
LabView interfa e) at the 10-bit DAC dis riminator ( ommon to the 36 input
hannels) in the fast shaping line, and dierent harge values were inje ted, thus
allowing for the study of the time walk and jitter dependen e on the trigger
threshold level and on the amplitude of the input signal. The shift of the mean
14
Figure 17: The trigger signal (light blue) is measured in the os illos ope in
oin iden e with the pulse generator trigger (green). The shift of the mean and
the RMS value of the trigger distribution provide the measurement of the trigger
time walk and jitter, respe tively.
and the RMS value of the measured trigger distribution, whi h is shown for a
typi al setting in Fig. 17, provide the measurement of the trigger time walk and
jitter, respe tively. Typi al distributions of the trigger timing above des ribed
are presented in Fig. 18.
The results of the time walk measurements are shown in Fig. 19, for in reas-
ing values of the inje ted harge, from 0.08 up to 1.60 pC (equivalent to one
pixel and 20 ring pixels in an AHCAL SiPM, respe tively), and of the dis rim-
inator threshold level. The time walk values are presented with respe t to the
trigger timing orresponding to the largest inje ted harge. When setting the
threshold value above the pedestal the time walk appears to be up to 7 ns only
for the rst pixel peaks. For a larger number of ring pixels it is within one
nanose ond; this feature is observed also for a threshold at about half a mip
(SiPMs are ongured su h that on average 15 pixels should re due to a mip
energy deposition [3, thus orresponding to 1.2 pC input harge).
The trigger jitter dependen e on the inje ted harge, for dierent values of
the dis riminator threshold, is presented in Fig. 20. The jitter appears to be
up to 1.4 ns, at the smallest threshold values and for small values of inje ted
harge, while it is within 1.0 ns at a threshold of about half a mip.
Con erning the forseen operation of the hip in auto-trigger mode, resolving
single-pixel stru ture in the SiPM spe tra (i.e., in alibration mode) appears
to be not infeasible, due to the reasonably small measured trigger jitter and
time walk At the moment, the SiPM alibration is expe ted to be performed
15
Entries 66013
Mean 50.87
RMS 1.241
Trigger timing [ns]46 48 50 52 54 56 58 60
Yie
ld
0
500
1000
1500
2000
2500
3000
3500
4000
4500Entries 66013
Mean 50.87
RMS 1.241
Discriminator Threshold: 0.00pC
Injected Charge: 0.1pC Entries 6184
Mean 44.21
RMS 0.3916
Trigger timing [ns]40 42 44 46 48 50
Yie
ld
0
200
400
600
800
1000
1200Entries 6184
Mean 44.21
RMS 0.3916
Discriminator Threshold: 0.00pC
Injected Charge: 0.7pC
Figure 18: The trigger timing distribution is presented for the dis riminator
threshold value set above the pedestal, and for dierent values of the inje ted
harge in the SPIROC board.
Discriminator threshold at:
pedestal
Discriminator threshold at:
0.16 pC
Discriminator threshold at:
0.32 pC
Discriminator threshold at:
0.64 pC
Injected Charge [pC]
Trigg
er T
ime W
alk [n
s]
0
2
4
6
8
10
12
14
16
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Figure 19: The trigger time walk is presented for dierent threshold values of
the 10-bit DAC dis riminator, and for in reasing values of the inje ted harge
in the SPIROC board.
via an LED system providing an external trigger to the ASIC readout. This
issue will be extensively presented in Se . 15. Instead, the small time walk and
jitter values observed at thresholds and input harges above half a mip, should
denitely allow the hip to properly operate in the physi s mode. The inuen e
of largely varying SiPM gain values, light generation and olle tion e ien y
16
Discriminator threshold at:
pedestal
Discriminator threshold at:
0.16 pC
Discriminator threshold at:
0.32 pC
Discriminator threshold at:
0.64 pC
Injected Charge [pC]
Trigg
er Ji
tter [
ns]
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Figure 20: The trigger jitter is presented for dierent threshold values of the
10-bit DAC dis riminator, and for in reasing values of the inje ted harge in
the SPIROC board.
has not been studied in this work.
9 SiPM Voltage Adjustment
The hip is forseen to be onne ted to an external power supply and to provide
a ommon high voltage bias to all onne ted 36 SiPMs. Tuning of the applied
voltage, hannel by hannel, is a hieved using an 8-bit DAC HV adjustment
dedi ated to ea h dete tor power line, Fig. 21.
The alibration of the input HV DAC for all hannels is at the moment
performed via dedi ated LabView interfa e routines. The applied voltage ranges
approximately from 0 V to 4.5 V, varying from hannel to hannel, Fig. 22.
The measurements are linearly tted in the range 10-245 DAC units, and
the residual of ea h measurement to the resulted linear fun tion is al ulated.
A large hannel by hannel variation in the residuals size is observed, and two
extreme ases are reported in Fig. 23.
The results show a dierential non-linearity on average up to 70 mV, and
for some hannels up to 200 mV, Fig. 24, resulting in a relative gain hange of
approximatively 1.8% and 5.2% [4, respe tively, and thus providing a potential
systemati un ertainty of similar size to the energy alibration of the dete tor,
in ase the observed deviation annot be systemati ally reprodu ed.
To investigate the reprodu ibility of the voltage tuning applied to the ASIC
hannels, two series of DAC s ans (ve s an per series) were performed for one
hannel in separate periods hara terised by a temperature variation of three
degrees Celsius. Within ea h data set, the maximum deviation between the
17
50
100 nF
Ω10 pF
ASIC
DAC
amplifiershaper
SiPM
cable
100 nF
100k
+HV
Ω
Figure 21: Diagram of the SiPM onne tion to the ASIC board. The same line
is used for both power and signal. While a ommon voltage bias is provided by
an external power supply to all 36 SiPMs onne ted to the ASIC, ea h voltage
is tunable via a separate 8-bit DAC HV adjustment.
measured voltage values was al ulated for ea h DAC value, and is presented in
Fig. 25. As expe ted, for ea h series of measurements the spread in reases with
the DAC value, i.e. with the amount of urrent in the DAC swit h, resulting
in a maximum systemati al deviation up to one millivolt. As a onsequen e,
the observed large dierential non-linearity an be orre ted via a alibration of
hannel by hannel HV adjustment DAC.
Although a negligible deviation is observed among the measurements, when
ombining the two data sets the maximum spread of the measurements in reases
up to 10 mV. This an be possibly interpreted as due to the large variation of
the temperature (up to three Celsius degrees) measured during the systemati al
studies, resulting in a larger applied voltage value observed at a lower temper-
ature. In this ase, the observed hange of voltage adjustment value ould be
Entries 36Mean 90.39RMS 95.68
Minimum applicable voltage per channel [mV]0 50 100 150 200 250 300
Yie
ld
0
2
4
6
8
10
12
14 Entries 36Mean 90.39RMS 95.68
Figure 22: Distribution of the mini-
mum appli able voltage via the 8-bitDAC HV adjustment. Ea h en-
try represents the minimum volt-
age value measured in one SPIROC
hannel.
18
Voltage Adjustment Set [DAC]0 50 100 150 200 250
Me
as
ure
d V
olt
ag
e [
V]
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Channel Nr. 5
0.00138±Offset: 4.49625
0.00001±Slope: -0.01690
Voltage Adjustment Set [DAC]0 50 100 150 200 250
Me
as
ure
d V
olt
ag
e [
V]
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Channel Nr.16
0.00138±Offset: 4.41819
0.00001±Slope: -0.01639
Voltage Adjustment Set [DAC]0 50 100 150 200 250M
ea
su
red
Vo
lta
ge
Re
sid
ua
ls [
mV
]
-100
-80
-60
-40
-20
0
20
40
60
80
100
Channel Nr. 5
Voltage Adjustment Set [DAC]0 50 100 150 200 250M
ea
su
red
Vo
lta
ge
Re
sid
ua
ls [
mV
]
-100
-80
-60
-40
-20
0
20
40
60
80
100
Channel Nr.16
Figure 23: Upper Panels: Calibration of the high voltage DAC adjustment.
Lower Panels: The residuals of the measurements with respe t to the fun tion
obtained by a linear t.
Entries 36Mean 78.91RMS 39.92
Max residual per channel [mV]0 20 40 60 80 100 120 140 160 180 200
Yie
ld
0
0.5
1
1.5
2
2.5
3 Entries 36Mean 78.91RMS 39.92
Figure 24: Distribution of the de-
viation from linearity of the high
voltage adjustment. Ea h entry rep-
resents the maximum deviation ob-
served in one hannel.
19
Voltage Adjustment [DAC]0 50 100 150 200 250
Ma
xim
um
Vo
ltag
e D
evi
atio
n [
mV
]
0
2
4
6
8
10
12
CoData taken at T=33CoData taken at T=30
Combined data
Figure 25: The measured maximum deviation of the voltage adjustment applied
to the SPIROC hannels is presented for two separate DAC s ans performed at
dierent temperatures. When ombining the measurements of the two data sets
the spread in reases up to 10 mV.
orre ted via a proper alibration. The alibration might not be needed in ase
of small temperature gradient during data taking, sin e the observed 10 mV sys-
temati al spread is still small ompared to the overvoltage of SiPMs, typi ally
of 2-4 V for the devi es used in urrent AHCAL test beam operations [4. Thus,
this spread would orrespond to a gain hange below 1%.
10 Low Gain - High Gain Coupling
In ea h input hannel of the ASIC the low and high gain paths are ele tri ally
oupled, Fig 26. As a result, the harge sharing between the two paths is
inuen ed by the feedba k apa itan e value set.
In order to estimate the ee ts of the high-low gain oupling, the output
signal in one path was measured for dierent apa itan e values in the other
preamplier line. No signi ant ee t is observed in the output signal of the
high gain line while hanging the ampli ation in the other line. Instead, a
sizable ee t (up to 10%) is visible when measuring the output signal in physi s
mode and hanging the ampli ation in the high gain line. An example of the
observed orrelation is presented in Fig. 27 for dierent values of the harge
inje ted in the ASIC (using a 6.4 dB attenuator at the pulse generator output).
20
1.5 pF
Input
15 pF
Slow Shaper
Slow Shaper
50−100 ns
50−100 ns
0.1 − 1.5 pF
0.1 − 1.5 pF
Fast Shaper
15 ns
PreamplifierHigh Gain
Low GainPreamplifier
Figure 26: Ele tri al diagram of
the high gain and low gain paths
per single hannel in the ASIC
hip.
High Gain Feedback Capacitance [fF]0 100 200 300 400 500 600
Lo
w G
ain
Ou
tpu
t [A
DC
]
40
50
60
70
80 Input charge: 9.6 pC
LG shaping time: 50 ns
LG feedback capacitance: 400 fF
Input charge: 9.6 pC
LG shaping time: 50 ns
LG feedback capacitance: 400 fF
Input charge: 9.6 pC
LG shaping time: 50 ns
LG feedback capacitance: 400 fF
Input charge: 9.6 pC
LG shaping time: 50 ns
LG feedback capacitance: 400 fF
High Gain Feedback Capacitance [fF]0 100 200 300 400 500 600
Lo
w G
ain
Ou
tpu
t [A
DC
]
100
110
120
130
140
150Input charge: 19.1 pC
LG shaping time: 50 ns
LG feedback capacitance: 400 fF
Input charge: 19.1 pC
LG shaping time: 50 ns
LG feedback capacitance: 400 fF
Input charge: 19.1 pC
LG shaping time: 50 ns
LG feedback capacitance: 400 fF
Input charge: 19.1 pC
LG shaping time: 50 ns
LG feedback capacitance: 400 fF
Figure 27: The output signal (in ADC units) is measured in the low gain path
while hanging the feedba k apa itan e value for the high gain amplier. Here
presented are two measurements obtained using dierent values of input harge
in the ASIC.
11 Cross Talk between Input Channels
The hip will handle 36 in oming signal lines. A ording to previous measure-
ments [2 the estimated ross-talk among the neighbouring hannels is below
0.3% for an inje ted harge of 15 pC. The measurement in [2 was presented for
few inje ted harge values only. This investigation of the ross-talk was done
performing a wider s an of inje ted harge. While in reasing the inje ted harge
in steps of 1 pC from one to 40 pC, orresponding approximately to the range
1−33 mips, the output signal (pedestal subtra ted) was measured in the neigh-
bouring hannels. The ASIC was run in low gain mode (physi s mode) at 50 ns
of shaping time, and 400 fF of feedba k apa itan e.
An example of the performed measurements is presented in Fig. 28. The
output signal in the line where the harge was inje ted is shown in the upper
21
5 10 15 20 25 30 35 40
Sig
na
l o
utp
ut
[mV
]
0
50
100
150
200
Charge injected in channel 5
5 10 15 20 25 30 35 40
Sig
na
l o
utp
ut
[mV
]
-2
-1.5-1
-0.50
0.51
1.52
Injected charge [pC]5 10 15 20 25 30 35 40
Cro
ss
Ta
lk [
%]
-2-1.5
-1-0.5
00.5
11.5
2
channel 4
channel 6
Figure 28: The measurement of the ross-talk is presented for the low gain mode
at 50 ns of shaping time, and 400 fF of feedba k apa itan e.
panel. The reason of the observed non-linearity was found in the tra k and hold
swit h (see Se . 12). In the neighbouring lines the measured signal is typi ally
within ±0.5 mV in the analysed input harge range (middle panel), onrming a
negligible harge leakage between the hannels. A small trend is visible, within
the ±0.5 mV range, moving from small to large inje ted harge. For ea h harge
value the ross-talk (bottom panel) in one hannel was al ulated dividing its
signal (held at its maximum amplitude) to the orresponding signal in the line
where the harge was inje ted. As expe ted by using this method, the ross-
talk inates at small input harge values. At the 15 pC of inje ted harge, the
measurement is lose to what reported in [2.
12 Tra k and Hold Swit h
The hip has to save the amplitude of the pre-amplied and shaped signal
at its peaking time (arrival time of signal maximum). This is a hieved using
the tra k and hold swit h, Fig. 29, whi h holds the signal at the amplitude
orresponding to a provided holding-trigger arrival, to be tuned to hold the
signal at its maximum amplitude.
The peaking time is not expe ted to depend on the amount of inje ted harge
(mainly depending instead on the shaper type [6), and the hoi e of the holding-
trigger should hold for all values of input harge. Surprisingly, it was observed
22
Figure 29: Ele tri al diagram of the
Tra k and Hold swit h.
that the peaking time varies with the harge. The signal amplitude was mea-
sured with the external ADC while performing a s an of the holding-trigger
arrival time, in both low and high gain modes, for 50 ns shaping time, and for
all possible values of the feedba k apa itan e. An example of these measure-
ments is shown in Fig. 30. In these test-ben h measurements the hold signal
is generated by the external voltage sour e. Its arrival time an be arbitrarily
varied to anti ipate or delay it with respe t to peaking amplitude of the inje ted
harge. The measurements show that the peaking time (displayed with a verti-
al line in ea h plot) in reases with in reasing inje ted harge (while remaining
onstant only after rea hing saturation), thus suggesting that either the peaking
time is harge dependent ( ontrary to the expe tations) or that the tra k and
hold swit h somehow interferes with the signal developing in time.
After investigation by the Orsay group, a possible explanation of the ob-
served feature in the small harge region was proposed [7. Due to the small
bias transistor size in the tra k and hold buer (bottom transistor in Fig. 29)
and to the large parasiti apa itan e at its output, small input harge will
make the buer enter the non-linear working region. The investigation with
simulations is on-going by the Orsay group.
13 Dynami Range, Linearity, and Gain of the
ASIC
During normal AHCAL data taking (low gain) the dynami range of the ASIC
should over the region between one mip and ≈ 77 mips (1156 pixels per SiPM
/ 15 pixels ring per mip), onsidering saturation ee ts in the SiPM due to the
limit number of pixels and to the pixel re overy time. Assuming a SiPM gain
of the order of 5 · 105( orresponding to 0.08 pC harge generated per pixel),
the overed dynami mips range orresponds to the region between 1.2 and
92.5 pC. It should be noted that this upper harge limit depends on the spe i
photodete tor gain (MEPhy/Pulsar devi es, onsidered here, have a pixel gain
23
0
100
200
300
400
500
0
200
400
600
800
1000
50 100 50 100
Outp
ut Si
gnal
[mV] Qinj: 10 pC
FC: 100 fF
Qinj: 20 pC Qinj: 30 pC
Outp
ut Si
gnal
[mV] Qinj: 40 pC Qinj: 50 pC
Hold Timing [ns]
Qinj: 60 pC
50 100
0
25
50
75
100
125
150
175
200
225
250
0
100
200
300
400
500
600
50 100 50 100
Outp
ut Si
gnal
[mV] Qinj: 10 pC
FC: 300 fF
Qinj: 20 pC Qinj: 30 pC
Outp
ut Si
gnal
[mV] Qinj: 40 pC Qinj: 50 pC
Hold Timing [ns]
Qinj: 60 pC
50 100
Figure 30: The output signal from the ASIC is measured in low gain mode for
50 ns shaping time and for dierent input harge values, while performing a
s an in the hold arrival time. No attenuator on the input line was used.
24
variation between 0.25 · 106and 1.00 · 106
).
The hip preamplier gain should be hosen su h to provide a linear response
in the whole energy range. On this purpose, a s an was performed over all
feedba k apa itan e values possible in low gain mode, while in reasing the
amount of inje ted harge. For ea h input harge, it was hosen the hold-
trigger timing orresponding to the maximum amplitude for the output signal
measured at the external ADC. This hoi e was motivated by the impossibility of
performing su h a time onsuming multi-parameter s an extra ting the proper
holding-time via the os illos ope, without an automatised pro edure (ea h single
point of the s an was systemati ally measured several times). Systemati ee ts
arising by the tra k and hold swit h, as dis ussed in Se . 12, might ae ts the
results.
The results of this s an, presented in the upper panel of Fig. 31 for 50 ns
shaping time, indi ate that the minimum feedba k apa itan e value needed to
over the required SiPM dynami range (77 mips) is 400 fF. Above this value
the maximum expe ted mip signal an be pro essed before the ASIC runs into
saturation. As a referen e, the values of the inje ted harge are also reported
in terms of equivalent AHCAL mips values.
The sets of data were linearly t in the range 10-30 pC and the residuals to
the linearity were al ulated dividing the deviation of the measured points from
the t results over the t values. A non linearity up to 20% is observed with
in reasing inje ted harge, bottom panel of Fig. 31. The region where the ASIC
saturation appears (anyway not relevant for the forseen operation of the hip)
shows a onsistent drop of the residuals.
Similar measurements were performed operating the hip in high gain mode,
Fig. 32. In this mode, used for alibration, it is preferable to use the largest
(smaller) gain (feedba k apa itan e) to investigate the SiPM single-pixel spe -
tra. The results show that for 100 fF of feedba k apa itan e the saturation
is rea hed for values of input harge above 10 pC, orresponding to a dynami
range up to ≈ 8 mips, enough for performing the alibrations. Note that here
the linear t was performed in the range 1-3 pC.
The observed non linearity is mainly due to the mentioned features of the
tra k and hold swit h, whi h are under investigation and will be possibly ured
in the next generation of the hip. In addition to the observed inje ted harge
dependen e of the peaking time, it was also observed that the peaking amplitude
obtained via the tra k and hold swit h is typi ally larger than what observed
when the signal is not held.
The gain of the hip was al ulated out of the same data a ording to the
formula GASIC =Voutput
Qinput(in
mVpC
units), and is presented in Fig. 33 for dierent
values of the feedba k apa itan e CFC in both low and high gain modes at 50ns shaping time.
In the low (high) gain mode the hip ampli ation fa tor was measured
for 30 pC (3 pC) of inje ted harge, a value not sizably ae ted by the non-
linearity indu ed by the tra k and hold swit h. The expe ted 1/CFC fun tional
dependen e of the gain [5 is observed, quantitatively in agreement with the
25
FC: 100 fF
FC: 300 fF
FC: 500 fF
FC: 700 fF
FC: 1000 fF
FC: 1500 fF
Shaping time: 50 ns Low Gain
Injected Charge [pC]
Outp
ut A
SIC
[mV]
Equivalent mips
0
200
400
600
800
1000
0 50 100 150 200 250 300
0 25 50 75 100 125 150 175 200 225 250
FC: 100 fF
FC: 300 fF
FC: 500 fF
FC: 700 fF
FC: 1000 fF
FC: 1500 fF
Shaping time: 50 ns
Low Gain
Injected Charge [pC]
Resid
uals
to li
near
ity [%
]
Equivalent mips
-60
-40
-20
0
20
40
0 25 50 75 100 125 150 175 200 225 250
0 20 40 60 80 100 120 140 160 180 200
-10
-5
0
5
10
0 20 40
Figure 31: The output signal from the ASIC is measured in low gain mode for
50 ns shaping time and for dierent input harge values. Upper panel: Results
obtained using dierent feedba k apa itan e values are ompared. Bottom
Panel: Residuals to linearity al ulated as des ribed in the text.
measurements presented in [2 and [8.
26
FC: 100 fF
FC: 300 fF
FC: 500 fF
FC: 700 fF
FC: 1000 fF
FC: 1500 fF
Shaping time: 50 ns High Gain
Injected Charge [pC]
Outp
ut A
SIC
[mV]
Equivalent mips
0
200
400
600
800
1000
1200
1400
0 10 20 30 40
0 5 10 15 20 25 30 35
FC: 100 fF
FC: 300 fF
FC: 500 fF
FC: 700 fF
FC: 1000 fF
FC: 1500 fF
Shaping time: 50 ns
High Gain
Injected Charge [pC]
Resid
uals
to li
near
ity [%
]
Equivalent mips
-60
-40
-20
0
20
40
0 5 10 15 20 25 30 35 40 45
0 5 10 15 20 25 30 35
-5
0
5
0 5
Figure 32: The output signal from the ASIC is measured in high gain mode for
50 ns shaping time and for dierent input harge values. Upper panel: Results
obtained using dierent feedba k apa itan e values are ompared. Bottom
Panel: Residuals to linearity al ulated as des ribed in the text. A 20 dB
attenuator at the input line was used during these measurements.
27
Shaping time: 50 ns
Low Gain
Qinj: 30 pC
Feedback Capacitance [fF]
Gain
[mV/
pC]
0
2
4
6
8
10
12
14
16
18
20
0 200 400 600 800 1000 1200 1400 1600
Shaping time: 50 ns
High Gain
Qinj: 3 pC
Feedback Capacitance [fF]
Gain
[mV/
pC]
0
20
40
60
80
100
120
0 200 400 600 800 1000 1200 1400 1600
Figure 33: The gain of the ASIC is measured in both low and high gain modes
for 50 ns shaping time and for 30 pC and 3 pC of inje ted harge, respe tively.
14 Amplitude Dependen e on Shaping Time
The ee t of the shaping time value on the measured signal peaking amplitude
was investigated. The amplitude was measured operating the ASIC in low gain
mode for dierent values of the shaping time and for the feedba k apa itan e
value of 400 fF, Fig. 34. Dierently from what presented in Fig. 31, here a 20 dB
28
Shaping Time: 50 ns
Shaping Time: 75 ns
Shaping Time: 100 ns
Shaping Time: 150 ns
Feedback Capacitance: 400 fF Low Gain
Injected Charge [pC]
Outp
ut A
SIC
[mV]
Equivalent mips
0
50
100
150
200
250
300
0 5 10 15 20 25 30 35 40
0 5 10 15 20 25 30
Shaping Time: 50 ns
Shaping Time: 75 ns
Shaping Time: 100 ns
Shaping Time: 150 ns
Feedback Capacitance: 400 fF Low Gain
Injected Charge [pC]
Resid
uals
to li
near
ity [%
]
Equivalent mips
-100
-80
-60
-40
-20
0
20
40
60
80
100
0 5 10 15 20 25 30 35 40
0 5 10 15 20 25 30
Figure 34: Upper panel: The output signal from the ASIC is measured in low
gain mode for 400 fF feedba k apa itan e, and for dierent values of inje ted
harge and of shaping time. Bottom Panel: Residuals to linearity al ulated as
des ribed in the text. A 20 dB attenuator (10−1X) at the input line was used
during these measurements.
29
attenuator was used, to present results at small inje ted harge in ner binning.
Also, results are presented for harge values down to 1 pC.
The signal peaking amplitude appears to in rease with de reasing shaping
time, in agreement with simulations. The sets of data were linearly t in the
range 1-4 pC and the residuals to the linearity were al ulated dividing the
deviation of the measured points from the t results over the t values. A non
linearity up to 40% is observed for in reasing inje ted harge, bottom panel
of Fig. 34. In this region of inje ted harge values the non-linearity response
(due to the tra k and hold swit h) appears to be weakly dependent on the
hosen shaping time. Note that a dire t omparison with the results presented
in the bottom panel of Fig. 31 annot be done, being dierent both the region
onsidered in the linear t and the smallest values of inje ted harge onsidered
in these measurements.
15 SiPM Single-Pixel Spe tra
The possibility to operate the ASIC in auto-trigger mode during alibrations
was shown to be feasible due to the low trigger jitter time walk, smaller than 1and 7 ns, respe tively (see Se . 8). That possibility is onrmed by the followingmeasurement of the single-pixel spe trum.
A SiPM, ashed by an LED, was onne ted to the board, and the pro essed
output signal was investigated. The devi e was operated at overvoltage larger
(+1.7 V) than the nominal value, to in rease the ross-talk between the pixels
(whi h is, on the other side, not desirable for physi s mode operations). The
SiPM signal was measured using the auto-trigger mode des ribed in Se .7. After
properly setting a dis riminator threshold value, the generated trigger was used
to trigger an external pulse generator (HP 8082A). One signal from the pulser
was then used to open the gate of the external ADC module, and a se ond signal
was input to the SPIROC board to hold the analogue signal from the SiPM at
its peaking amplitude.
When the dis riminator threshold is set above the pedestal the ontribution
of the thermal noise dominates the measured spe trum, Fig. 35, due to its large
rate (typi ally around MHz).
In order to observe the ontribution of LED light indu ed events in the
spe trum, the dis riminator threshold was set to 480 DAC units, orresponding
to a value approximately above 3 pixels for a measured gain of 13 mV per
pixel (operating the SiPM at 64.7 V), Fig. 36. Also, the rate of the LED
ashes was in reased to 30 kHz from the initial 1 kHz. Although the thermal
noise ontribution appears to be still sizable in this experimental onguration
(dominating the spe trum rst peaks), the LED signal appears in the spe trum
at large amplitude values, and is also presented in the zoomed panel of the
pi ture. The results show the single-pixel stru ture, and suggest that a t of
the spe trum (either the thermal noise or the signal ontribution) might be
possible, although its quality annot be quantied at this stage of the analysis.
The above results were obtained for a quite large gain of the SiPM. To see
30
/ ndf 2χ 359.4 / 50Prob 0p0 41.2± 6699 p1 0.0± 12.6 p2 0.013± 2.676 p3 29.2± 3445 p4 0.02± 25.13 p5 0.027± 3.153 p6 18.2± 1497 p7 0.04± 38.03 p8 0.057± 3.545 p9 11.2± 668.5 p10 0.09± 51.16 p11 0.116± 3.733 p12 8.2± 312 p13 0.16± 64.54 p14 0.229± 4.529
Amplitude [mV]0 10 20 30 40 50 60 70 80 90 100
Yiel
d
0
1000
2000
3000
4000
5000
6000
7000 / ndf 2χ 359.4 / 50Prob 0p0 41.2± 6699 p1 0.0± 12.6 p2 0.013± 2.676 p3 29.2± 3445 p4 0.02± 25.13 p5 0.027± 3.153 p6 18.2± 1497 p7 0.04± 38.03 p8 0.057± 3.545 p9 11.2± 668.5 p10 0.09± 51.16 p11 0.116± 3.733 p12 8.2± 312 p13 0.16± 64.54 p14 0.229± 4.529
p.e.0 1 2 3 4 5
SiPM 711
: 12.8 mVp.e.
<gain>
DAC: 565
Voltage Bias: 64.7 V
Figure 35: Single-pixel spe trum for the thermal noise obtained by operating
the SiPM in high gain (13 mV per pixel) and for the dis riminator threshold
level above the pedestal. Superimposed is the gaussian t to the peak stru ture
of the spe trum.
the ee ts of a lower pixel gain value, the voltage bias applied to the devi e was
de reased to 63.0 V resulting in a gain around 8 mV per pixel, whi h orresponds
Amplitude [mV]0 50 100 150 200 250 300 350 400
Yiel
d
0
20
40
60
80
100
120
140
160
180310×
Amplitude [mV]160 180 200 220 240 260 280 300
Yiel
d
13000
13500
14000
14500
15000
15500
16000
16500
17000
SiPM 711 : 13.0 mVp.e.
<gain>
DAC: 480 Voltage Bias: 64.7 V
Figure 36: Single-pixel spe trum obtained by ashing the SiPM with LED light.
The devi e was operated in high pixel gain (13 mV per pixel) setting the SPIROC
dis riminator threshold level above the third pixel peak, and running the ASIC
in auto-trigger mode. The ontribution from the thermal noise and the LED
events dominates the rst peaks and the high tail of the spe trum, respe tively.
The peak stru ture of part of the spe trum for LED driven events is also pre-
sented in the zoomed panel for better visibility.
31
Amplitude [mV]0 20 40 60 80 100 120 140 160 180 200
Yiel
d
0
20
40
60
80
100
120
140
160
180310×
SiPM 711
: 8.0 mVp.e.
<gain>
DAC: 480
Voltage Bias: 63.0 V
Figure 37: Single-pixel spe trum obtained by ashing the SiPM with LED light.
The devi e was operated in low pixel gain (8 mV per pixel) setting the SPIROC
dis riminator threshold level above the fth pixel peak, and running the ASIC
in auto-trigger mode. Due to the lower devi e gain and to the high dis rimi-
nator threshold value the ontribution from the thermal noise is here strongly
suppressed, and the spe trum is mainly populated by LED driven events.
to approximately half a million ele trons. The dis riminator threshold value was
kept un hanged, orresponding at about ve pixels at this low pixel gain. The
resulting spe trum is presented in Fig. 37. Due to the lower devi e gain and to
the high dis riminator threshold value the ontribution from the thermal noise is
here strongly suppressed, and the spe trum is mainly populated by LED driven
events.
To see the quality of the noise spe trum for this low SiPM gain, the threshold
was set above the pedestal, Fig. 38. At this low pixel gain value, the single-pixel
stru ture of the thermal noise spe trum appears to be deteriorated, ompli ating
the possibility to perform a t of the pixel stru ture to alibrate the devi e. This
ompli ation might be over ome by operating the SiPM with a larger gain, as
shown in Fig. 35 .
As a omparison, the measurement was repeated using an external trigger to
hold the peaking amplitude and to open the gate of the ADC module, operating
the SiPM at low pixel gain and setting the dis riminator threshold value above
the pedestal. The LED intensity was de reased to have a lower number of pixels
ring, similarly to what is usually done alibrating a SiPM with an LED system.
The single-pixel spe trum, now without any ontribution from the thermal noise,
is presented in Fig. 39. The peaks appear to be well separated, allowing the
alibration of the devi e using an external light sour e system. Potentially, the
alibration of the photodete tor might be also performed running the SPIROC
in auto-trigger mode by analysing the thermal noise. In this ase, during the
alibration the SiPM should be operated at larger pixel gains, as shown above.
32
Amplitude [mV]0 20 40 60 80 100 120 140 160 180
Yiel
d
0
100
200
300
400
500
600
310×
Amplitude [mV]50 60 70 80 90 100 110 120
Yiel
d
25000
30000
35000
40000
45000
50000
55000
SiPM 711 : 8.0 mVp.e.
<gain>
DAC: 560 Voltage Bias: 63.0 V
Figure 38: Single-pixel spe trum obtained by ashing the SiPM with LED light.
The devi e was operated in low pixel gain (8 mV per pixel) setting the SPIROC
dis riminator threshold level above the pedestal, and running the ASIC in auto-
trigger mode. The ontribution from the thermal noise and the LED events
dominates the rst peaks and the high tail of the spe trum, respe tively. The
peak stru ture of part of the spe trum for LED driven events is also presented
in the zoomed panel for better visibility.
Amplitude [mV]0 20 40 60 80 100 120 140
Yiel
d
0
10000
20000
30000
40000
50000
60000
SiPM 711
: 8.0 mVp.e.
<gain>
DAC: 575
Voltage Bias: 63.0 V
External Trigger
Figure 39: Typi al SiPM single-pixel spe tra obtained by ashing the SiPM
with LED light. The devi e was operated in low pixel gain (8 mV per pixel)
setting the SPIROC dis riminator threshold level above the pedestal. Here, the
signal is held at its peaking amplitude by an external trigger given by the main
pulse generator.
33
16 Towards Real Data Taking Conditions
When the measurements presented in this note have been performed, the soft-
ware to operate the hip in auto-trigger mode (see Se . 7) was not fully im-
plemented. This limitation ould be somehow bypassed using the following
pro edure, thus testing the apability and the e ien y of the hip to perform
measurements in both physi s and auto-trigger mode at dierent trigger thresh-
old values, Fig. 40.
These measurements were performed using the signal from a SiPM (SiPM
number 758), thus simulating, as mu h as possible, real data taking onditions.
Spe tra suitable for tting the single-pixel stru ture of the signal were obtained
operating the high voltage supply at 64.6 V, orresponding to 59.4 V voltage
bias measured at the dynodes of SiPM by setting the input HV DAC tuning
to zero units (see Se . 9). Note that the nominal operation voltage for this
SiPM is 59.3 V, as de lared in the SiPM database. The main pulse generator
triggered the generation of a negative voltage pulse (via a Hewlett Pa kard
8130A pulse generator providing width, leading and trailing edges tunable down
to the nanose ond level) to an LED, opti ally oupled to a SiPM whose signal
was then dire tly input to the ASIC board, using the same high voltage line,
Fig. 21. The intensity of the LED, and in turns of the SiPM signal, ould be
then regulated by the hained pulser.
During test-ben h measurements the signal to open the ADC module gate
is typi ally provided by the pulse generator, for every generated voltage pulse.
A essing the trigger allows instead to generate the open-gate signal only in ase
ADC module
CAEN V785N
bufferamplifier1x or 9x
VME CAEN 8002
hold
ASICSiPM
+HV
pulse generator
STS DG 535
pulse generatortrigger
HP 8130A
generatorgate
STS DG 535
pulse generator
Figure 40: Test ben h setup used at DESY for the investigation of the e ien y
of the SPIROC 1B hip to perform measurements in physi s and auto-trigger
mode at dierent trigger threshold values.
34
DAC value Suppressed peak number
530 3510 4490 5470 6450 7430 8410 9390 10
Table 1: DAC values applied at the
signal dis riminator to suppress spe-
i peaks in the SiPM spe trum.
The obtained DAC values refer to
the hip operated in high gain mode
at 25 ns shaping time and 100 fF
feedba k apa itan e. One DAC
units orresponds to ≈ 1.9 mV in
the fast shaping line.
a pro essed signal (either from the thermal noise or from the LED) overshoots a
hosen threshold value in the dis riminator. The generated trigger was therefore
used as an external trigger to an additional pulse generator, whi h in turns
generated the signal to open the ADC module gate at a suitable time. The hold
signal was provided by the main pulser used to swit h the LED on.
As a rst step, the hip was operated in high gain mode in parallel with
low intensity LED light, while applying dierent threshold DAC values via the
LabView interfa e (the larger is the DAC value set, the smaller is the applied
threshold level value). Using the trigger only to open the ADC gate, but holding
the signal peaking amplitude via the external primary pulse generator allowed to
easily t the single-pixel stru ture of the spe trum orresponding to LED events,
for the purpose of this measurement, Fig. 41- 42. In ase a signal indu ed by
thermal noise overshoots the dis riminator threshold level then the ADC gate
is still opened by the generated trigger but the pro essed signal is not any more
syn hronised with the hold signal generated by the main pulser. This results in
deteriorating the single-pixel stru ture of the thermal noise ontribution, and
populating the spe trum towards the pedestal region (the re orded signal ampli-
tude is lower than the real peaking amplitude). This ontribution from thermal
noise to the spe trum is in reasingly suppressed with in reasing the threshold
value, as learly visible in Fig. 41. Although the number of suppressed peaks in
the spe trum in reases by in reasing the threshold level, the measurements show
that a remaining small ontribution from the peaks expe ted to be suppressed
is still present. This feature, possibly due to the experimental setup, has not
been furtherly investigated at this stage of the analysis, being not relevant for
the measurement presented here.
From the above measurements the threshold values to ut spe i spe trum
peaks an be determined resulting in approximative 20 DAC units per peak,
Tab. 1. This orresponds to a step of ≈ 37 mV in the fast shaping line (see
Fig. 14).
As a ross he k, a similar spe trum was taken using the pulse generator
to open the ADC gate, obtaining the same single-pixel peak lo ations, Fig. 43.
With the same setup, a mip signal was tentatively obtained tuning the LED
amplitude su h that the SiPM spe trum shows a maximum around the 15 pixel
peak amplitude, Fig. 44. Keeping the same LED amplitude, the mip-like signal
35
/ ndf 2χ 396 / 402Prob 0.5756p0 3.4± 306.1 p1 0.12± 20.55 p2 0.323± 4.078 p3 22.4± 254.2 p4 0.18± 29.15 p5 0.187± -2.443 p6 19.2± 291.3 p7 0.25± 36.18 p8 0.439± -3.118 p9 15.5± 253.7 p10 0.32± 44.34 p11 0.598± 3.423 p12 41.4± 113.3 p13 0.45± 51.68 p14 0.456± 2.558 p15 3.4± 190.2 p16 0.74± 59.38 p17 1.078± 6.613
Amplitude [mV]20 30 40 50 60 70 80 90 100 110
Yie
ld
0
100
200
300
400
500
600 / ndf 2χ 396 / 402
Prob 0.5756p0 3.4± 306.1 p1 0.12± 20.55 p2 0.323± 4.078 p3 22.4± 254.2 p4 0.18± 29.15 p5 0.187± -2.443 p6 19.2± 291.3 p7 0.25± 36.18 p8 0.439± -3.118 p9 15.5± 253.7 p10 0.32± 44.34 p11 0.598± 3.423 p12 41.4± 113.3 p13 0.45± 51.68 p14 0.456± 2.558 p15 3.4± 190.2 p16 0.74± 59.38 p17 1.078± 6.613
p.e.2 3 4 5 6 7 8
SiPM 758
: 7.4 mVp.e.
<gain>
DAC: 570
Voltage Bias: 64.6 V
/ ndf 2χ 424.5 / 402Prob 0.2112p0 3.6± 346.1 p1 0.09± 21.52 p2 0.198± 3.875 p3 16.0± 368.3 p4 0.11± 29.76 p5 0.118± -2.397 p6 20.7± 397.4 p7 0.16± 36.63 p8 0.243± -2.866 p9 34.0± 356.6 p10 0.28± 44.56 p11 0.385± 3.553 p12 40.7± 135.6 p13 0.28± 52.37 p14 0.318± -2.424 p15 3.9± 262 p16 0.82± 59.53 p17 1.420± 7.497
Amplitude [mV]20 30 40 50 60 70 80 90 100 110
Yie
ld
0
100
200
300
400
500
600 / ndf 2χ 424.5 / 402
Prob 0.2112p0 3.6± 346.1 p1 0.09± 21.52 p2 0.198± 3.875 p3 16.0± 368.3 p4 0.11± 29.76 p5 0.118± -2.397 p6 20.7± 397.4 p7 0.16± 36.63 p8 0.243± -2.866 p9 34.0± 356.6 p10 0.28± 44.56 p11 0.385± 3.553 p12 40.7± 135.6 p13 0.28± 52.37 p14 0.318± -2.424 p15 3.9± 262 p16 0.82± 59.53 p17 1.420± 7.497
p.e.2 3 4 5 6 7 8
SiPM 758
: 7.4 mVp.e.
<gain>
DAC: 560
Voltage Bias: 64.6 V
/ ndf 2χ 418.6 / 402Prob 0.2736p0 3.4± 326.9 p1 0.09± 21.17 p2 0.188± 3.871 p3 8.2± 453.5 p4 0.06± 29.72 p5 0.08± -2.43 p6 8.2± 518.9 p7 0.08± 36.67 p8 0.080± -2.707 p9 35.4± 449.8 p10 0.11± 44.31 p11 0.127± 3.309 p12 29.5± 177 p13 0.14± 51.89 p14 0.170± 2.498 p15 3.0± 334.1 p16 0.59± 59.11 p17 1.04± -8.06
Amplitude [mV]20 30 40 50 60 70 80 90 100 110
Yie
ld
0
100
200
300
400
500
600 / ndf 2χ 418.6 / 402
Prob 0.2736p0 3.4± 326.9 p1 0.09± 21.17 p2 0.188± 3.871 p3 8.2± 453.5 p4 0.06± 29.72 p5 0.08± -2.43 p6 8.2± 518.9 p7 0.08± 36.67 p8 0.080± -2.707 p9 35.4± 449.8 p10 0.11± 44.31 p11 0.127± 3.309 p12 29.5± 177 p13 0.14± 51.89 p14 0.170± 2.498 p15 3.0± 334.1 p16 0.59± 59.11 p17 1.04± -8.06
p.e.2 3 4 5 6 7 8
SiPM 758
: 7.4 mVp.e.
<gain>
DAC: 550
Voltage Bias: 64.6 V
/ ndf 2χ 394.6 / 402Prob 0.5942p0 3.2± 275.7 p1 0.11± 20.83 p2 0.295± 4.261 p3 13.5± 534.8 p4 0.1± 30 p5 0.088± 2.427 p6 20.0± 782.8 p7 0.11± 37.09 p8 0.138± 2.708 p9 16.7± 788.3 p10 0.10± 44.56 p11 0.237± 3.064 p12 69.9± 434.8 p13 0.24± 51.58 p14 0.245± -2.725 p15 5.9± 567.3 p16 0.38± 59.73 p17 0.573± 6.151
Amplitude [mV]20 30 40 50 60 70 80 90 100 110
Yie
ld
0
200
400
600
800
1000 / ndf 2χ 394.6 / 402
Prob 0.5942p0 3.2± 275.7 p1 0.11± 20.83 p2 0.295± 4.261 p3 13.5± 534.8 p4 0.1± 30 p5 0.088± 2.427 p6 20.0± 782.8 p7 0.11± 37.09 p8 0.138± 2.708 p9 16.7± 788.3 p10 0.10± 44.56 p11 0.237± 3.064 p12 69.9± 434.8 p13 0.24± 51.58 p14 0.245± -2.725 p15 5.9± 567.3 p16 0.38± 59.73 p17 0.573± 6.151
p.e.2 3 4 5 6 7 8
SiPM 758
: 7.4 mVp.e.
<gain>
DAC: 540
Voltage Bias: 64.6 V
/ ndf 2χ 425.4 / 412Prob 0.3143p0 1.61± 88.64 p1 0.20± 20.26 p2 0.428± 5.235 p3 4.5± 157.7 p4 0.09± 30.42 p5 0.098± 2.304 p6 5.2± 301.5 p7 0.09± 37.61 p8 0.116± 2.658 p9 11.1± 332.1 p10 0.13± 44.91 p11 0.181± 2.836 p12 5.0± 236.8 p13 0.45± 61.06 p14 0.490± 5.373 p15 28.9± 236 p16 0.17± 52.17 p17 0.324± 3.225
Amplitude [mV]20 30 40 50 60 70 80 90 100 110
Yie
ld
0
100
200
300
400
500
600 / ndf 2χ 425.4 / 412
Prob 0.3143p0 1.61± 88.64 p1 0.20± 20.26 p2 0.428± 5.235 p3 4.5± 157.7 p4 0.09± 30.42 p5 0.098± 2.304 p6 5.2± 301.5 p7 0.09± 37.61 p8 0.116± 2.658 p9 11.1± 332.1 p10 0.13± 44.91 p11 0.181± 2.836 p12 5.0± 236.8 p13 0.45± 61.06 p14 0.490± 5.373 p15 28.9± 236 p16 0.17± 52.17 p17 0.324± 3.225
p.e.2 3 4 5 6 7 8
SiPM 758
: 7.5 mVp.e.
<gain>
DAC: 530
Voltage Bias: 64.6 V
/ ndf 2χ 420.8 / 392Prob 0.1519p0 1.69± 84.12 p1 0.17± 20.49 p2 0.419± 3.551 p3 3.0± 101.6 p4 0.21± 30.46 p5 0.337± 3.065 p6 8.8± 305.6 p7 0.13± 38.28 p8 0.156± 2.613 p9 14.6± 434.4 p10 0.15± 45.59 p11 0.219± 2.787 p12 48.2± 371.5 p13 0.19± 52.58 p14 0.315± -2.841 p15 5.3± 373 p16 0.32± 60.91 p17 0.663± 4.378
Amplitude [mV]20 30 40 50 60 70 80 90 100 110
Yie
ld
0
100
200
300
400
500
600 / ndf 2χ 420.8 / 392
Prob 0.1519p0 1.69± 84.12 p1 0.17± 20.49 p2 0.419± 3.551 p3 3.0± 101.6 p4 0.21± 30.46 p5 0.337± 3.065 p6 8.8± 305.6 p7 0.13± 38.28 p8 0.156± 2.613 p9 14.6± 434.4 p10 0.15± 45.59 p11 0.219± 2.787 p12 48.2± 371.5 p13 0.19± 52.58 p14 0.315± -2.841 p15 5.3± 373 p16 0.32± 60.91 p17 0.663± 4.378
p.e.2 3 4 5 6 7 8
SiPM 758
: 7.5 mVp.e.
<gain>
DAC: 520
Voltage Bias: 64.6 V
Figure 41: The spe trum from SiPM nr.758 is measured in high gain mode ap-
plying dierent threshold DAC values at the signal dis riminator lo ated along
the fast shaping line. The hip is operated in high gain mode at 25 ns shaping
time and 100 fF feedba k apa itan e.
was then measured using the low gain mode of the hip, Fig. 45, for a shaping
time of 50 ns.
36
/ ndf 2χ 386.4 / 392Prob 0.5706p0 1.58± 79.15 p1 0.28± 20.25 p2 0.630± 4.267 p3 4.56± 73.28 p4 0.25± 30.24 p5 0.338± 2.917 p6 5.6± 302.6 p7 0.15± 38.95 p8 0.179± 2.907 p9 18.7± 499.5 p10 0.11± 45.83 p11 0.142± 2.433 p12 66.9± 459.4 p13 0.14± 52.38 p14 0.275± -2.814 p15 5.1± 503.5 p16 0.3± 60.9 p17 0.782± 4.994
Amplitude [mV]20 30 40 50 60 70 80 90 100 110
Yie
ld
0
100
200
300
400
500
600
/ ndf 2χ 386.4 / 392Prob 0.5706p0 1.58± 79.15 p1 0.28± 20.25 p2 0.630± 4.267 p3 4.56± 73.28 p4 0.25± 30.24 p5 0.338± 2.917 p6 5.6± 302.6 p7 0.15± 38.95 p8 0.179± 2.907 p9 18.7± 499.5 p10 0.11± 45.83 p11 0.142± 2.433 p12 66.9± 459.4 p13 0.14± 52.38 p14 0.275± -2.814 p15 5.1± 503.5 p16 0.3± 60.9 p17 0.782± 4.994
p.e.2 3 4 5 6 7 8
SiPM 758
: 7.5 mVp.e.
<gain>
DAC: 510
Voltage Bias: 64.6 V
/ ndf 2χ 426.8 / 396Prob 0.1379p0 1.67± 75.36 p1 0.16± 20.41 p2 0.313± 3.047 p3 1.58± 67.76 p4 0.19± 29.54 p5 0.350± 3.204 p6 4.2± 215.7 p7 0.18± 39.44 p8 0.190± 3.015 p9 21.0± 494.3 p10 0.10± 46.15 p11 0.108± 2.292 p12 36.0± 627.1 p13 0.15± 52.94 p14 0.216± 3.005 p15 7.8± 659.5 p16 0.19± 61.42 p17 0.369± 4.012
Amplitude [mV]20 30 40 50 60 70 80 90 100 110
Yie
ld
0
100
200
300
400
500
600
700
/ ndf 2χ 426.8 / 396Prob 0.1379p0 1.67± 75.36 p1 0.16± 20.41 p2 0.313± 3.047 p3 1.58± 67.76 p4 0.19± 29.54 p5 0.350± 3.204 p6 4.2± 215.7 p7 0.18± 39.44 p8 0.190± 3.015 p9 21.0± 494.3 p10 0.10± 46.15 p11 0.108± 2.292 p12 36.0± 627.1 p13 0.15± 52.94 p14 0.216± 3.005 p15 7.8± 659.5 p16 0.19± 61.42 p17 0.369± 4.012
p.e.2 3 4 5 6 7 8
SiPM 758
: 7.6 mVp.e.
<gain>
DAC: 500
Voltage Bias: 64.6 V
/ ndf 2χ 266.5 / 249Prob 0.2135p0 7.5± 460.1 p1 0.14± 47.08 p2 0.105± -3.043 p3 40.1± 719.8 p4 0.12± 53.75 p5 0.121± -2.411 p6 109.8± 717.4 p7 0.2± 60.2 p8 0.313± 3.073 p9 12.9± 773.7 p10 0.38± 68.83 p11 0.796± 4.916
Amplitude [mV]30 40 50 60 70 80 90 100 110
Yie
ld
0
100
200
300
400
500
600
700
800
900
/ ndf 2χ 266.5 / 249Prob 0.2135p0 7.5± 460.1 p1 0.14± 47.08 p2 0.105± -3.043 p3 40.1± 719.8 p4 0.12± 53.75 p5 0.121± -2.411 p6 109.8± 717.4 p7 0.2± 60.2 p8 0.313± 3.073 p9 12.9± 773.7 p10 0.38± 68.83 p11 0.796± 4.916
p.e.4 5 6 7 8
SiPM 758
: 7.7 mVp.e.
<gain>
DAC: 490
Voltage Bias: 64.6 V
/ ndf 2χ 224.2 / 249Prob 0.8686p0 9.4± 320.3 p1 0.21± 47.43 p2 0.148± 2.806 p3 17.5± 797 p4 0.09± 54.28 p5 0.13± -2.57 p6 82.9± 711.2 p7 0.12± 60.57 p8 0.180± -2.559 p9 6.3± 1078 p10 0.19± 68.74 p11 0.43± -5.57
Amplitude [mV]40 50 60 70 80 90 100 110
Yie
ld
0
200
400
600
800
1000
1200
/ ndf 2χ 224.2 / 249Prob 0.8686p0 9.4± 320.3 p1 0.21± 47.43 p2 0.148± 2.806 p3 17.5± 797 p4 0.09± 54.28 p5 0.13± -2.57 p6 82.9± 711.2 p7 0.12± 60.57 p8 0.180± -2.559 p9 6.3± 1078 p10 0.19± 68.74 p11 0.43± -5.57
p.e.5 6 7 8 9
SiPM 758
: 7.7 mVp.e.
<gain>
DAC: 480
Voltage Bias: 64.6 V
/ ndf 2χ 222.8 / 234Prob 0.6896p0 24.1± 244.9 p1 0.35± 62.06 p2 0.291± 2.571 p3 56.1± 410.9 p4 0.18± 69.11 p5 0.439± 3.057 p6 7.7± 461.6 p7 0.89± 83.44 p8 1.838± 6.836 p9 124.8± 249.1 p10 0.43± 75.77 p11 0.528± 2.649
Amplitude [mV]60 70 80 90 100 110
Yie
ld
0
100
200
300
400
500
600
/ ndf 2χ 222.8 / 234Prob 0.6896p0 24.1± 244.9 p1 0.35± 62.06 p2 0.291± 2.571 p3 56.1± 410.9 p4 0.18± 69.11 p5 0.439± 3.057 p6 7.7± 461.6 p7 0.89± 83.44 p8 1.838± 6.836 p9 124.8± 249.1 p10 0.43± 75.77 p11 0.528± 2.649
p.e.7.5 8 8.5 9 9.5 10 10.5 11 11.5
SiPM 758
: 7.6 mVp.e.
<gain>
DAC: 450
Voltage Bias: 64.6 V
/ ndf 2χ 219.9 / 181Prob 0.02573p0 12.2± 203 p1 0.23± 70.43 p2 0.214± 3.142 p3 37.6± 189.3 p4 0.17± 76.64 p5 0.218± -2.232 p6 4.0± 438.7 p7 0.17± 84.53 p8 0.6± 5.7
Amplitude [mV]65 70 75 80 85 90 95 100 105 110
Yie
ld
0
100
200
300
400
500
600
/ ndf 2χ 219.9 / 181Prob 0.02573p0 12.2± 203 p1 0.23± 70.43 p2 0.214± 3.142 p3 37.6± 189.3 p4 0.17± 76.64 p5 0.218± -2.232 p6 4.0± 438.7 p7 0.17± 84.53 p8 0.6± 5.7
p.e.8.5 9 9.5 10 10.5 11
SiPM 758
: 7.7 mVp.e.
<gain>
DAC: 430
Voltage Bias: 64.6 V
Figure 42: The spe trum from SiPM nr.758 is measured in high gain mode ap-
plying dierent threshold DAC values at the signal dis riminator lo ated along
the fast shaping line. The hip is operated in high gain mode at 25 ns shaping
time and 100 fF feedba k apa itan e.
Using again the generated trigger to open the ADC gate, and applying dif-
ferent threshold DAC values, the trigger e ien y with respe t to the signal
37
/ ndf 2χ 532.3 / 516
Prob 0.3006
Amplitude [mV]0 20 40 60 80 100
Yie
ld
0
100
200
300
400
500
600 / ndf 2χ 532.3 / 516
Prob 0.3006
p.e.0 2 4 6 8 10
SiPM 758
: 7.7 mVp.e.
<gain>
DAC: 400
Voltage Bias: 64.6 V
Peak 0: -0.89 +- 0.070Peak 1: 6.46 +- 0.051Peak 2: 14.19 +- 0.054Peak 3: 21.80 +- 0.058Peak 4: 29.36 +- 0.082Peak 5: 37.15 +- 0.088Peak 6: 44.36 +- 0.154Peak 7: 53.01 +- 0.232
Peak 0: -0.89 +- 0.070Peak 1: 6.46 +- 0.051Peak 2: 14.19 +- 0.054Peak 3: 21.80 +- 0.058Peak 4: 29.36 +- 0.082Peak 5: 37.15 +- 0.088Peak 6: 44.36 +- 0.154Peak 7: 53.01 +- 0.232
Peak 0: -0.89 +- 0.070Peak 1: 6.46 +- 0.051Peak 2: 14.19 +- 0.054Peak 3: 21.80 +- 0.058Peak 4: 29.36 +- 0.082Peak 5: 37.15 +- 0.088Peak 6: 44.36 +- 0.154Peak 7: 53.01 +- 0.232
Peak 0: -0.89 +- 0.070Peak 1: 6.46 +- 0.051Peak 2: 14.19 +- 0.054Peak 3: 21.80 +- 0.058Peak 4: 29.36 +- 0.082Peak 5: 37.15 +- 0.088Peak 6: 44.36 +- 0.154Peak 7: 53.01 +- 0.232
Peak 0: -0.89 +- 0.070Peak 1: 6.46 +- 0.051Peak 2: 14.19 +- 0.054Peak 3: 21.80 +- 0.058Peak 4: 29.36 +- 0.082Peak 5: 37.15 +- 0.088Peak 6: 44.36 +- 0.154Peak 7: 53.01 +- 0.232
Peak 0: -0.89 +- 0.070Peak 1: 6.46 +- 0.051Peak 2: 14.19 +- 0.054Peak 3: 21.80 +- 0.058Peak 4: 29.36 +- 0.082Peak 5: 37.15 +- 0.088Peak 6: 44.36 +- 0.154Peak 7: 53.01 +- 0.232
Peak 0: -0.89 +- 0.070Peak 1: 6.46 +- 0.051Peak 2: 14.19 +- 0.054Peak 3: 21.80 +- 0.058Peak 4: 29.36 +- 0.082Peak 5: 37.15 +- 0.088Peak 6: 44.36 +- 0.154Peak 7: 53.01 +- 0.232
Peak 0: -0.89 +- 0.070Peak 1: 6.46 +- 0.051Peak 2: 14.19 +- 0.054Peak 3: 21.80 +- 0.058Peak 4: 29.36 +- 0.082Peak 5: 37.15 +- 0.088Peak 6: 44.36 +- 0.154Peak 7: 53.01 +- 0.232
Figure 43: The SiPM single pixel
spe trum obtained operating the
hip in high gain mode at 25 ns
shaping time and 100 fF feedba k
apa itan e, and using the main ex-
ternal pulse generator to open the
ADC gate.
Amplitude [mV]20 40 60 80 100 120 140 160 180 200 220
Yie
ld
0
50
100
150
200
250
300
350
400
450
500
p.e.5 10 15 20 25
SiPM 758
Voltage Bias: 64.6 V
Figure 44: A mip-like signal mea-
sured operating the hip in high gain
mode at 25 ns shaping time and
100 fF feedba k apa itan e.
dis rimination level was investigated for two values of the feedba k apa itan e,
Fig. 46. In the plots, the threshold DAC values are presented in terms of num-
ber of photo-ele tron peaks whi h are ut by the sele ted threshold, a ording
to Tab. 1. By in reasing the DAC value (de reasing the trigger threshold) the
number of triggers generated by the noise in reases, resulting in a larger on-
tribution of pedestal events to the overall a umulated events in the spe tra.
Already at half a mip threshold the fra tional ontribution of SiPM signal events
is almost 100%, for both the investigated ASIC ongurations.
The preliminary results presented here verify the possibility to operate the
ASIC in auto-trigger mode (after the mentioned improvement of the tra k and
hold swit h) pro essing the physi s events at half a mip ut on the trigger
threshold, as forseen in the ILC appli ations.
38
Amplitude [ADC]
1100 1120 1140 1160 1180 1200
Yiel
d
0
20
40
60
80
100310×
SiPM 758
Voltage Bias: 64.6 V
mip-like signal
Amplitude [ADC]
1100 1120 1140 1160 1180 1200
Yiel
d
0
50
100
150
200
250
300
350
400310×
pedestal
Figure 45: A mip-like signal (left panel) and the pedestal (right panel) are
measured operating the hip in low gain mode at 50 ns shaping time and 200 fF
feedba k apa itan e.
Amplitude [ADC]1130 1140 1150 1160 1170 1180 1190 1200
Yie
ld
0
50
100
150
200
250
300
350
400310×
SiPM 758
50 ns shaping time
200 fF feedb. capacitance
Fraction of mip events2.0 p.e.: 0.159
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98611.0 p.e.: 0.999
12.0 p.e.: 1.000
2.0 p.e.: 0.159
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98611.0 p.e.: 0.999
12.0 p.e.: 1.000
2.0 p.e.: 0.159
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98611.0 p.e.: 0.999
12.0 p.e.: 1.000
2.0 p.e.: 0.159
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98611.0 p.e.: 0.999
12.0 p.e.: 1.000
2.0 p.e.: 0.159
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98611.0 p.e.: 0.999
12.0 p.e.: 1.000
2.0 p.e.: 0.159
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98611.0 p.e.: 0.999
12.0 p.e.: 1.000
Amplitude [ADC]1130 1140 1150 1160 1170 1180 1190 1200
Yie
ld
0
50
100
150
200
250
300
350
400310×
SiPM 758
50 ns shaping time
400 fF feedb. capacitance
Fraction of mip events2.0 p.e.: 0.158
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98510.0 p.e.: 0.998
12.0 p.e.: 0.999
2.0 p.e.: 0.158
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98510.0 p.e.: 0.998
12.0 p.e.: 0.999
2.0 p.e.: 0.158
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98510.0 p.e.: 0.998
12.0 p.e.: 0.999
2.0 p.e.: 0.158
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98510.0 p.e.: 0.998
12.0 p.e.: 0.999
2.0 p.e.: 0.158
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98510.0 p.e.: 0.998
12.0 p.e.: 0.999
2.0 p.e.: 0.158
3.5 p.e.: 0.4445.0 p.e.: 0.832
7.5 p.e.: 0.98510.0 p.e.: 0.998
12.0 p.e.: 0.999
Figure 46: The e ien y in dete ting a mip-like signal is measured at dierent
threshold values (in SiPM photo-ele tron units) operating the hip in low gain
mode at 50 ns shaping time, 200 fF and 400 fF feedba k apa itan e, left and
right panel, respe tively.
17 Con lusions
During 2008 and 2009 systemati studies have been performed to hara terise
the analogue omponent of the SPIROC ASIC, designed for the readout of the
analogue hadroni alorimeter for the international linear ollider proje t. The
more signi ant results are presented and des ribed in this report showing the
39
fullled requirements and the features whi h should be xed in the next ver-
sion of the hip. These measurements have been done on the SPIROC version
SPIROC 1B, whi h has the analogue pro essing of signals almost fully imple-
mented.
The ASIC was shown to handle the dynami range overed by the SiPMs
whi h are expe ted to be readout in both alibration mode for the maximum
ampli ation at 100 fF feedba k apa itan e, and physi s mode for values of
feedba k apa itan e above 400 fF, resulting non-saturated up to ≈ 80 and ≈ 8mips, respe tively. The values reported here refer to a SiPM with pixel gain of
order 0.5 ·106. In ase of SiPMs with highly varying pixel gain (as for the SiPMs
used in the past AHCAL test beam operations), the dynami range overed
by the photodete tor hanges, and the operation mode of the hip should be
hanged a ordingly, resulting in a hange of the signal over noise ratio.
The data a quisition is forseen to run in auto-trigger mode, being a tivated
by the SiPM signals, and the hip appears to full this requirement in the physi s
mode, rea hing 100% trigger e ien y for trigger threshold values above half
a mip. For these values the trigger time walk and jitter were found to be less
than 3 and 1 ns, respe tively. Quite remarkable, is the observed possibility to
t the thermal noise, opening the potentiality of self- alibrating the devi e.
The ele troni noise was investigated and found to be typi ally within one
millivolt, depending on the spe i shaping time and ampli ation setting. The
most sizable additional ontribution to the noise is indu ed by swit hing on the
tra k and hold omponent, approximately doubling the noise. When oupled to
an external signal sour e the noise dependen e on varying the oupling apa i-
tan e (as for real SiPMs) was found to be within 20% in the range 10-100 pF.
Comparing the 36 input hannels, the pedestals showed a spread of 2 mV,
and their deviation due to ross-talk was measured to be within ±0.5 mV in the
investigated range from one to 33 mips (40 pC).
Ea h input SiPM high voltage an be individually tuned via a DAC HV
adjustment dedi ated to ea h dete tor line. The DAC to volt alibration was
performed for all hannels showing a hannel to hannel average variation of
100 mV, and an average maximum deviation to linearity of 80 mV (for some
hannels up to 200 mV). The observed deviation from linearity appears to be
systemati ally reprodu ible, and ould be orre ted for via a proper alibration.
The high-low gain path oupling was studied and a sizable dependen e (up
to 10%) on the high gain ampli ation setting was measured for the physi s
mode readout.
Probably the most surprising feature of the hip was the observed in rease
of the signal peaking time with in reasing inje ted harge, related to properties
of the used tra k and hold swit h. Investigation with simulations by the hip
designers in Orsay is on-going, and a possible ure of the shown feature should
be available in the next generations of the ASIC.
The investigation of the digital omponent of the ASIC, implemented in the
version SPIROC 2, is on going and will be presented in a separate future note.
40
A knowledgments
We are deeply grateful to S. Callier, C. De La Taille, and L. Raux
of the OMEGA group at Orsay, and to F. Sefkow and E. Garutti at
DESY for useful dis ussions and suggestions.
Referen es
[1 J. Brau et al., International Linear Collider Referen e Design Report,
ILC-REPORT-2007-001 (2007).
[2 M. Bou hel et al., Pro . of the IEEE 2008 Nu lear S ien e Symposium,
Dresden, Germany, O tober 2008.
[3 M. Groll, Constru tion and Commissioning of a Hadroni Test-Beam
Calorimeter to Validate the Parti le-Flow Con ept at the ILC, PhD Thesis
2007, DESY-THESIS-2007-018.
[4 N. Feege, Sili on Photomultipliers: Properties and Appli ation in a Highly
Granular Calorimeter, Diploma Thesis 2008, DESY-THESIS-2008-050.
[5 W. R. Leo, Te hniques for Nu lear and Parti le Physi s Experiments,
Springer-Verlag.
[6 E. Kowalski, Nu lear Ele troni s, Springer Verlag.
[7 L. Raux, private ommuni ations.
[8 L. Raux, SPIROC ASIC Measurement, Presentation given at CALICE
ELECTRONICS meeting, Mar h 11, 2008.
41