SPIROC : second generation of Silicon PM Readout ASIC Michel Bouchel, Stéphane Callier, Frédéric...
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Transcript of SPIROC : second generation of Silicon PM Readout ASIC Michel Bouchel, Stéphane Callier, Frédéric...
SPIROC : second generation of SPIROC : second generation of Silicon PM Readout ASICSilicon PM Readout ASIC
SPIROC : second generation of SPIROC : second generation of Silicon PM Readout ASICSilicon PM Readout ASIC
Michel Bouchel, Stéphane Callier, Frédéric Dulucq, Julien Fleury, Jean-Jacques Jaeger, Gisèle Martin-Chassard, Christophe de La Taille, Ludovic Raux
IN2P3/OMEGA-LAL Orsay
France
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 2
Contents• SPIROC : an ILC dedicated Chip
– ILC calorimetry electronics requirements
• SPIROC, the second generation chip for SiPM readout: – SPIROC Description
• Chip measurements
• Summary and perspectives
Aachen, Deutschland
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 3
ILC Challenges for electronics• Requirements for ILC
calorimetry electronics– Large dynamic range (15 bits)– Auto-trigger on 1/3 MIP – On chip zero suppress– 108 channels– Front-end embedded in detector– Compactness– « Ultra-low power » : (25µW/channel)
• « Tracker electronics with calorimetric performance »
ATLAS LAr FEB 128ch 400x500mm : 1 W/chFLC_PHY3 18ch 10x10mm 5mW/ch ILC 25µW/ch
Sectorwall
Reflector Foil100µm
Polyimide Foil100µm PCB
800µm
Bolt with innerM3 threadwelded to bottomplate
SiPM
Tile3mm
HBU I nterface500µm gap
BottomPlate600µm
ASI CTQFP-1001mm high
Top Plate600µm steel
Component Area:900µm high
HBU height:6.1mm(4.9mmwithout covers => absorber)
AbsorberPlates(steel)
Spacer1.7mm
Top Platefixing
Sectorwall
Reflector Foil100µm
Polyimide Foil100µm PCB
800µm
Bolt with innerM3 threadwelded to bottomplate
SiPM
Tile3mm
HBU I nterface500µm gap
BottomPlate600µm
ASI CTQFP-1001mm high
Top Plate600µm steel
Component Area:900µm high
HBU height:6.1mm(4.9mmwithout covers => absorber)
AbsorberPlates(steel)
Spacer1.7mm
Top Platefixing
DESY
integratedM.Reinecke (DESY)
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 4
CALICE AHCAL testbeam physics prototype
• SPIROC is the second generation for SiPM readout
• The first generation FLC_SiPM was designed to equip the Analog H-Cal physics prototype for the ILC: 1 cubic meter, 38 layers, 2cm steel plates
• 8000 tiles with SiPM fabricated by MePHY group
Mechanics and front end boards: DESYFront end ASICs: LAL
FLC_SiPMASIC Mephy SiPM
Also used withW/Sci SiPM
japanese ECALwith MPPCs
Mardi 21 septembre 2010 Ludovic Raux – ID 62 – SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 5
The front-end ASICs : the ROC family chips
SPIROCAnalog HCAL(SiPM)36 ch. 32mm²
HARDROCDigital HCAL(RPC, µmegas or GEMs)64 ch. 16mm²
SKIROCECAL(Si PIN diode)64 ch. 60mm²
• Technological prototypes : full scale modules (~2m)
• ASIC designed within the CALICE collaboration and EUDET (EU funding 2006-2010)
• ECAL, AHCAL, DHCAL
E-CAL
H-CAL
(analog or digital)
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 6
SPIROC saga….• 200 chips SPIROC 1 produced in Nov 2007
– Package PQFP240– Good analog performance– Bug in ADC ramp : no digital data out
• 50 chips SPIROC 2 produced in June 2008 to equip AHCAL and ECAL EUDET modules
– EUDET milestone– Package TQFP208– Difficult slow control loading
• Full CALICE production run : April 2010 (Chip delivery Sept. 2010)
– SPIROC 2a (1200 chips) : conservative prototype in which the major bugs of SPIROC 2 are fixed
– SPIROC 2b (1200 chips) : more agressive prototype in which the major bugs of SPIROC 2 are also fixed and some interesting improvements are added (in particular the independent gain adjustment channel by channel)
– SPIROC A (3600 chips) : “light” analog version of SPIROC users who don’t need the digital core.
• Others applications using SPIROC chips– astrophysics PEBS experiment (Aachen University), – medical imaging (Roma, Pisa, INMC Orsay, Valencia, etc.)– Nuclear physics (IPNO, KEK)– Vulcanology: Muon radiography of geological structures (INFN
Napoli)
©W. Karpinski (Aachen)
PEBS PEBS experimentexperiment
Aachen Aachen UniversityUniversity
SPIROC ASPIROC AFabricated in SiGe AMS 0.35 µm Submitted in September 2009Delivered in December 2009
Chip area: 17 mm² (4.2 mm ×4.1 mm)
MU-RAY MU-RAY projectprojectINFN INFN NapoliNapoli
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 7
ILC beam structure and SPIROC running modes
Acquisition
1ms (.5%)
A/D conv..5ms (.25%)
DAQ.5ms (.25%)
1% duty cycle
IDLE MODE
99% idle cycle
198ms (99%)
time
Time between two trains: 200ms (5 Hz)
Time between two bunch crossing: 337 ns
Train length 2820 bunch X (950 µs)
Acquisition
1ms (.5%)
A/D conv..5ms (.25%)
DAQ.5ms (.25%)
1% duty cycle
IDLE MODE
99% idle cycle
198ms (99%)
time
Time between two trains: 200ms (5 Hz)
Time between two bunch crossing: 337 ns
Train length 2820 bunch X (950 µs)
Two orders of magnitude saved on the consumption by using the ILC beam structure and the power pulsing
Acquisition A/D conv. DAQ IDLE MODEChip 0
Chip 1 Acquisition DAQ IDLE MODEIDLE
Chip 2 Acquisition IDLE MODEIDLE
Chip 3 Acquisition IDLE MODEIDLE
Chip 4 Acquisition IDLE MODEIDLE DAQ
A/D conv.
A/D conv.
A/D conv.
A/D conv.
Acquisition A/D conv. DAQ IDLE MODEChip 0
Chip 1 Acquisition DAQ IDLE MODEIDLE
Chip 2 Acquisition IDLE MODEIDLE
Chip 3 Acquisition IDLE MODEIDLE
Chip 4 Acquisition IDLE MODEIDLE DAQ
A/D conv.
A/D conv.
A/D conv.
A/D conv.Chip 0 Chip 1 Chip 2 Chip 3 Chip 4
5 ev
ents
3 ev
ents
0 ev
ent
1 ev
ent
0 ev
ent
Data bus
• Readout based on token ring mechanism initiated by DAQ
• One data line activated by each chip sequentially
• Readout rate few MHz to minimize power dissipation
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 8
SPIROC main features• 36-Channel ASIC
• Internal input 8-bit DAC (0-5V) for individual SiPM gain adjustment
• Energy measurement : 14 bits– 2 gains (1-10) + 12 bit ADC : 1 pe 2000 pe– Variable shaping time from 25 ns to 175 ns – pe/noise ratio : ~11
• Auto-trigger on MIP or on single photo-electron– pe/noise ratio on trigger channel : ~24– Fast shaper : ~10 ns– Auto-Trigger on 1/3 pe (50fC)
• Time measurement : – 12-bit Bunch Crossing ID (coarse time)– 12-bit step~1 ns TDC->TAC (fine time)
• Other features:– Analog memory for time and charge measurement : depth = 16– Low consumption : ~25 µW per channel (in power pulsing mode)– Individually addressable calibration injection capacitance– Embedded features (bandgap, 10-bit DAC, etc.)– Multiplexed analog output for physics prototype DAQ– 4kbytes internal memory and daisy chain readout
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 9
SPIROC : One channel schematic
IN test 50 -100ns
50-100ns
Gain selection
4-bit threshold adjustment
10-bit DAC
15ns
DAC output
HOLD
Slow Shaper
Slow Shaper
Fast Shaper
Time measurement
Charge measurement
TDC ramp
300ns/5 µs
12-bit Wilkinson
ADC
Trigger
Depth 16
Depth 16
Depth 16
Common to the 36 channels
8-bit DAC
0-5V
Low gain Preamplifier
High gain Preamplifier
Analog memory
15pF
1.5pF
0.1pF-1.5pF
Conversion
maximum
time : 80 µs
READ
Variable delay
0.1pF-1.5pF
IN
Discri
Gain
Flag TDC
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 10
SPIROC general block scheme
DAQSPIROC ASIC
Chip ID register 8 bits
gain
Trigger discri Output
Wilkinson ADC Discri output
gain
Trigger discri Output
Wilkinson ADC Discri output
..…
OR36
EndRamp (Discri ADC Wilkinson)
36
36
36
TM (Discri trigger)
ValGain (low gain or high Gain)
ExtSigmaTM (OR36)
Channel 1
Channel 0
ValDimGray 12 bits
…
Acquisition
Readout
A/D conversion
+
RAM Writing
RAM
FlagTDC
ValDimGray
12
8
ChipID
Hit channel register 16 x 36 x 1 bits
TDC rampStartRampTDC
BCID 16 x 8 bits
ADC rampStartrampb (wilkinson
ramp)
16
16ValidHoldAnalogb
RazRangN
16ReadMesureb
Rstb
Clk40MHz
SlowClock
StartAcqt
StartConvDAQb
StartReadOut
NoTrig
RamFull
TransmitOn
OutSerie
EndReadOut
Chipsat
Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 11
SPIROC layout
Fabricated in SiGe AMS 0.35 µmSubmitted in june 2007
Chip area : 32 mm² (4.2mm × 7.2mm)
Mardi 21 septembre 2010
36 8-bit
5V DAC
36x16 Analog
memory
36 PreampShapersdiscris
36Wilkinson
ADC
SRAMReadout
ADC wilkinson Ramp
TDC RampBandgap Dual DAC
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 12
SPIROC Input DAC
• Input DAC to optimize SiPM bias voltage
• 8-bit DAC, 5V range• LSB=20mV• 36 DAC (one per channel)• Ultra low power (<1µW) : no
power pulsing• Can sink 10 µA leakage current• Linearity : ± 1%• DAC uniformity between the 36
channels : ~3%
+HV
Si PM
8-bit DAC
ASICHigh voltage on the cable
shielding
DAC linearity on the 36 channels
+1%
-1% DAC linearity residuals on the 36 channels
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 13
Trigger and gain selection DAC measurements
• Threshold 10-bit DAC linearity : typical ±0.2%
y = -0,00198623x + 2,32465620
R2 = 0,99996616
0
0,5
1
1,5
2
2,5
0 200 400 600 800 1000
-0,01
-0,008
-0,006
-0,004
-0,002
0
0,002
0,004
0,006
0,008
0,01
0 200 400 600 800 1000-0,004
-0,003
-0,002
-0,001
0
0,001
0,002
0,003
0,004
0 200 400 600 800 1000
Linearity
y = -0,0019918454x + 2,3253901509
R2 = 0,9999969857
0
0,5
1
1,5
2
2,5
0 200 400 600 800 1000
Trigger DAC Gain selection DAC
Residuals (V)
1 LSB = 2 mV
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 14
Low noise charge preamplifier capacitively coupled = voltage preamplifier
Preamp noise : 1.4 nV/sqrt(Hz)Power : 2 mW (unpulsed)
SPIROC charge measurement
High gain channel linearity
Linearity better than 1%
Charge measurement at different preamp gain
680fC ( ~4 pe @SiPM gain=106) in SPIROC
Charge measurement
Auto trigger
High gain channel output
Vout=30mV
Noise=1mV
Gain=45mV/pC
pe/noise~7 (expected ~11)Set up:
Cf=400fF
Tau=50ns
0.15
0.10
0.05
0.00
Vo
ut (V
)
500400300200100
Time (x10-9
s)
Cf=100fF Cf=100fF Cf=200fF Cf=300fF Cf=400fF Cf=500fF Cf=600fF Cf=700fF Cf=800fF Cf=900fF Cf=1pF Cf=1.1pF Cf=1.2F Cf=1.3pF Cf=1.4pF Cf=1.5pF
High gain charge output at different Cf Qinj= 1.5pC
©W.Shen (Heidelberg)
15pF 0.1pF-1.5pF
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 15
• Very low electronic cross-talk : 0.3% (long distance cross talk due to slow shaper voltage reference: If this voltage decoupled with 100µF, it becomes negligible ~0.04%)
Other measurements• Pedestal uniformity
– Mean= 1.16V; RMS = 1.8 mV
• Gain uniformity
– RMS 1%; 45 mV/pC (Cf=0.2pF, τ=50ns)
Gain uniformity
43,5
44
44,5
45
45,5
46
46,5
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
Channel
Vo
ut
(mV
)
SPIROC Test board
1,15
1,155
1,16
1,165
1,17
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
DC
vo
lta
ge
(V
)
Channel
pedestal
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 16
Trigger efficiency
• S-curves : Trigger efficiency versus Threshold (1 LSB = 2 mV)– Good uniformity between channels
• Trigger at 50fC matched (1/3 photon-electron at 106)
Pedestal
Qinj (fC)
50 fC
50fC injected
50 % Trigger efficiency point vs Qinj36-channel S-curves
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 17
Time considerations : Trigger jitter and trigger time-walk
• Time walk: ~10ns
• Trigger jitter: ~100ps
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 18
Single photoelectron spectrum
0 pe
1 pe
2 pe 4 pe 6 pe 8 pe
3 pe 5 pe 7 pe 9 pe
Setup: Autotrigger mode and internal ADC
Response with different injected charge
©R. Honda
MIP response in DESY 6 GeV electron testbeam
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 19
MIP response
Spectrum obtained with the LED calibration system
©I. Polák (ASCR Prague)
©M. Reinecke (DESY)
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 20
Summary and perspectives
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 21
Thank you for your attention !!!
If you have questions or comments…
Backup slides
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 22
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 23
SPIROC A main features• Spiroc 0 motivations :« light » analog version for
users who don’t need the digital core
• 32-Channel ASIC
• Internal input 8-bit DAC (0-5V) for individual SiPM gain adjustment
• Energy measurement : 14 bits– 2 gains (1-10) 1 pe 2000 pe– Variable shaping time from 25ns to 175ns – pe/noise ratio : 11– 2 Multiplexed outputs for low gain and high gain
• Trigger output– pe/noise ratio on trigger channel : 24– Fast shaper : ~10ns– Trigger on 1/3 pe (50fC)– 32 trigger outputs– OR 32 output– Trigger latch for each channel and multiplexed
output
• Individually addressable calibration injection capacitance
• Embedded features (power pulsing, new bandgap, 10-bit DAC, possibility to disable each stage to save power when unused, high impedance outputs when inactive)
Fabricated in SiGe AMS 0.35 µm Submitted in September 2009Delivered in December 2009
Chip area: 17 mm² (4.2 mm × 4.1 mm)
V a ria ble L owG a in P A (4 b its )
H o ldR e a d
L o w G ai nM ul t i p l e xe dO utput
C h3 1 _ tr i g
C hanne l 0
C o m m o n to the 3 2 c ha nne ls
C hanne l 3 1
V a ria ble H ighG a in P A (4 b its )
+
V_ thL atc h
R S
C hanne l 0 _ tr i g g e r
D isc ri
O R 3 2
S lo w S h a p e r2 5 - 1 7 5 n s
L G S lo w S h ap erVar iab le S h ap in g
T im e ( 3 b its )
1 5 n s
R e a d Tr i g g e rM ul t i p l e xe dO utput
L o w Ga inP r e A m p .
H G S low S ha pe rV a ria ble S ha ping
T im e (3 b its )
0 .1 p F - 1 .5 p F
1 .5 p F
1 0 -bi tD AC
R S o r D is cri
0 .1 p F - 1 .5 p F
1 5 p F
H igh Ga inP r e A m p .
H o ldR e a d
H i g h G ai nM ul t i p l e xe dO utput
+
S lo w S h a p e r2 5 - 1 7 5 n s
2 p F
Cte s t
2 p F
in_ c a lib
B ip o la r F a s t S h a p e r8 -bi t D AC
0 -5 V
INC h0
O Nc 15p
Mardi 21 septembre 2010 Ludovic Raux – ID 62 - SPIROC: SiPM readout ASIC TWEPP 2010 – Aix-la-Chapelle 24
Engineering run• Reticle size : 18x25 mm2
– 50-55 reticles/Wafer– 25 wafers needed
• Final arrangement:
– « Calice » chips produced:• 7 Hardroc 2b => ~9000 chips• 1 Spiroc 2a => ~1200 chips• 1 Spiroc 2b => ~1200 chips• 1 Skiroc 2 => ~1200 chips
– Additionnal chips produced:• 1 Spaciroc : JEM EUSO experiement => ~1200 chips• 1 Maroc 3 : for PMT readout => ~1200 chips• 3 Spiroc 0 => ~3600 chips
• Production run launched in April 2010
• Delivery in September 2010