Second generation Front-end Second generation Front-end chipchip for H-Cal SiPM for H-Cal SiPM readout :readout :

SPIROCSPIROC

DESY Hamburg – le 13 février 2007

M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux

LAL Orsay IN2P3-CNRS – Université Paris-Sud – B.P. 34 – 91898 Orsay cedex – France

First generation chip for SiPM : short reminder

18-channel 8-bit DAC (0-5V) 18-channel front-end readout :

Variable gain charge preamplifier (0.67 to 10 V/pC) Variable tine constant CRRC2 shaper (12 to 180 ns)

Track and hold 1 multiplexed output Power consumption : ~200mW (supply : 0-5V)

Technology : AMS 0.8 m CMOS Chip area : ~10mm²

Package : QFP-100

Second generation chip for SiPM : SPIROC

- A-HCAL read out

- Silicon PM detector

- 36 channels

- Compatible with new DAQ

- Many SKIROC, HARDROC, and MAROC features re-used

SPIROC submission expected on 11th june

Skiroc layout : ~20mm²

Technology : AMS 0.35 m SiGe

SPIROC main features 36-channel readout chip Internal input 8-bit DAC (0-5V) for SiPM gain adjustment Energy measurement :

2 gains / 12 bit ADC 1 pe 2000 pe Variable shaping time from 50ns to 100ns pe/noise ratio : 11

Time measurement : 1 TDC (12 bits) step~100 ps pe/noise ratio on trigger channel : 24 Fast shaper : ~15ns Auto-Trigger on ½ pe

Analog memory for time and charge measurement : depth 16 Power pulsing integrated Low consumption : ~25µW per channel (in power pulsing mode) Calibration injection capacitance Embedded bandgap for voltage references Embedded DAC for trigger threshold Compatible with physic prototype DAQ

Serial analogue output External “force trigger”

Probe bus for debug 12-bit Bunch Crossing ID SRAM with data formatting 2 x 2kbytes = 4kbytes Output & control with daisy-chain

SPIROC: One channel schematic

50 -100ns

50-100ns

Gain selection

8-bit threshold adjustment

Reference voltage

T

15ns

DAC output

Q

HOLD

Slow Shaper

Slow Shaper

Fast Shaper

Time measurement

Charge measurement

Fast ramp

300ns

12-bit Wilkinson

ADC

Trigger

Depth 16

Depth 16

Depth 16

Common to the 36 channels

8-bit DAC

0-5V

Low gain Preamplifier

High gain Preamplifier

Analog memory

50pF

5pF

0.1pF-1.5pF

Conversion 80 µs

READ

Variable delay

0.1pF-1.5pF

IN

IN test

Discri

Block scheme of SPIROC

Bunch crossing

Ch. 0

Ch. 1

Analog channel Analog mem.

36-channel12 bit

WilkinsonADC

for charge and time

measurement

Analog channel Analog mem.

Ch. 35 Analog channel Analog mem.

12-bit counterTime

digital mem.

Eventbuilder

Memorypointer

Triggercontrol

MainMemory

SRAM

Commodule

HC

AL

SLA

B

Expressions

0 .250 .500 .750 1.0time (us)

2.5

0

-2.5

-5.0

-7.5

-10.0

Y0

(mV

)Y

0 (m

V)

.2500

-.250-.500-.750

-1.0-1.25

Y1

(mV

)Y

1 (m

V)

150100

50.00

-50.0-100-150

Y2

(mV

)Y

2 (m

V)

10.0

7.5

5.0

2.5

0

-2.5

Y3

(mV

)Y

3 (m

V)

1.251.0

.750

.500

.2500

-.250

Y4

(mV

)Y

4 (m

V)

out_pa_hg

out_pa_lg

out_fs

out_ssh_hg

out_ssh_lg

time (us)

User: raux Date: Feb 9, 2007 Time: 2:34:15 PM CET

SPIROC : Photoelectron response simulation

High gain Preamplifier response

Low gain Preamplifier response

Fast shaper

High gain Slow shaper

Low gain Slow shaper

Tp=15ns

Tp=50ns

Tp=50ns

Noise/pe ratio = 25

Noise/pe ratio = 11

Noise/pe ratio = 31mV/pe

10mV/pe

120mV/pe

Simulation obtained with SiPM gain = 106 _ 1 pe = 160 fC

SPIROC : RAM Mapping

Time Measurement

Charge Measurement

1168

15 0

.....................

.....................

0

.....................

16

16x36

16x36

Time stamp (BCID)

Chip ID (8 bits)0 0 0 0

0 0 0 00 0 0 0

0 0 0 0

0 0 0 00 00 0

0 0

0 0 0 0

7

Time stamp (12 bits)

TDC measurement (12 bits)

ADC measurement (12 bits)

Gain (1 bit)Hit (1 bit)

TDC measurement (12 bits)

Time stamp (12 bits)

Time stamp (12 bits)

TDC measurement (12 bits)

ADC measurement (12 bits)

ADC measurement (12 bits)

SPIROC : Acquisition mode

Store up to 16 events in RAM Stop acquisition when ram_full signal asserted

Common collector bus for ram_full signal

36 36

SPIROC : Readout mode

Based on daisy chain mechanism initiated by DAQ Possibility to bypass a chip by slow control

One data line activated by each chip sequentially Readout rate few MHz to minimize power dissipation With 500 pF bus capacitance, power dissipation is

~10µW/chip i=CdV/dt = 1 mA => 1 mW for up to 100 chips on bus Readout time max (ram full) 20kbits x 1 µs = 20 ms/chip

Time considerations

time

Time between two trains: 200ms (5 Hz)

Time between two bunch crossing: 337 ns Train length 2820 bunch X

(950 us)

Acquisition

1ms (.5%)

A/D conv..5ms (.25%)

DAQ.5ms (.25%)

1% duty cycle

IDLE MODE

99% duty cycle

199ms (99%)

analog detectorsonly

Schedule

First Prototype submission : 11th june 2007

Expected delivery : September 2007

SPIROC Characterization : End of Year

Conclusion SPIROC designed for SiPM A-HCAL : second generation ASICs

Many SKIROC, HARDROC, and MAROC features re-used for SPIROC : power pulsing, bandgap, daisy chain mechanism, etc.

New features embedded : Time measurement, low consumption input DAC, etc.

Compatible with new DAQ

Complexity is increasing

Submission in june 2007 and first prototype expected in September 2007