Trends in high speed ADC design - ??2007.10.27 ASICON A. Matsuzawa 1 Matsuzawa Okada Lab. Trends in...

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Transcript of Trends in high speed ADC design - ??2007.10.27 ASICON A. Matsuzawa 1 Matsuzawa Okada Lab. Trends in...

  • 2007.10.27 ASICON A. Matsuzawa

    1

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Trends in high speed ADC design

    Akira Matsuzawa

    Department of Physical Electronics

    Tokyo Institute of Technology

    donsauerText Box more links at end

  • 2007.10.27 ASICON A. Matsuzawa

    2

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Contents

    Introduction

    Technology scaling and performance of pipelined ADCs Performance model of pipelined ADC

    Design challenge of high speed ADCs Pipelined ADCs

    Optimization of OpAmp

    Comparator controlled Current sourcein stead of OpAmp

    Sub-ranging ADC

    Successive approximation ADCs

    Delta-sigma ADC

  • 2007.10.27 ASICON A. Matsuzawa

    3

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Speed and power

    High Speed ADC[Sampling Freq. VS Power]

    1

    10

    100

    1000

    10000

    1 10 100 1000 10000

    Sampling Freq.[MSps]

    Power[

    mW

    ]

    12Bit(Paper)

    10Bit(Paper)

    12Bit Products

    10Bit Products.

    JSSC,ISSCC,VLSI,CICC,ESSCC

    & Products

    (10Bit,

    10MSps)1995-2006

    MHzmWbit /3.0:10

    MHzmWbit /1:12

    10b12b

    Conversion speed has saturated at 200 MHz Smaller mW/MHz is needed for low power operation.0.3mW/MHz for 10bit and 1mW/MHz for 12bit are the bottom lines.

    200MHz

    ISSCC 2007

  • 2007.10.27 ASICON A. Matsuzawa

    4

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Pipelined ADC

    1st stage

    2nd Stage

    SampleAmp.

    SampleAmp.

    Sample Amp. Sample Amp.

    Transfer characteristics

    Hold Sample Amplify

    -Vref

    +Vref

    -Vref

    +Vref

    0 1

    -Vref

    +Vref

    -Vref

    +Vref

    0 1 0 1

    1st Stage 2nd Stage

    Folding I/O characteristics makes higher resolution along with pipeline stages.

  • 2007.10.27 ASICON A. Matsuzawa

    5

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    M5

    Vbp2

    Vbp1

    VoutnVoutp

    Vbn1

    Vbn2

    Vdd

    VinpVinn

    Vbp1

    Technology scaling for analog

    M5

    Vbp2

    Vbp1

    VoutnVoutp

    Vbn1

    Vbn2

    Vdd

    VinpVinn

    Vbp1

    elVsig arg:

    SignalCap.

    ParasiticCap.

    ParasiticCap.

    ParasiticCap.

    ParasiticCap. Parasitic

    Cap.

    ParasiticCap.

    smallVsig :

    SignalCap.

    Technologyscaling

    Technology scaling can reduce parasitic capacitances.

    However signal capacitance will increase to keep the same SNR atlower voltage operation.

    Parasitic capacitance smallerOperating voltage lowerSignal swing lower

    Signal capacitance largerVoltage gain lower

  • 2007.10.27 ASICON A. Matsuzawa

    6

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Performance model for pipelined ADC

    Cf

    Cs Cpi gm Cpo COLRL21

    1

    p

    s

    +

    OpAmpofpoleSecond

    ceresisOutputR

    cecapaciLoadC

    cecapaciparaciticputputinputCC

    loopfeedbackforcecapaciSignalCC

    stageinputofcecTranscondug

    p

    L

    oL

    popi

    fs

    m

    :

    tan:

    tan:

    tan&:,

    tan:,

    tan:

    2

    L

    mclose

    C

    gGBW

    2_ =

    pisf

    f

    CCC

    C

    ++=

    ( )pisf

    pisf

    oLpoLCCC

    CCCCCC

    ++

    +++=

    2

    fs

    oL

    CCC

    += oLfso CCCC ===

    OpAmp

    ++

    +

    +

    =

    ++

    +

    +

    =

    o

    dspi

    o

    dspo

    o

    dspieffo

    ds

    o

    pi

    o

    po

    o

    pio

    mclose

    C

    I

    C

    I

    C

    IVC

    I

    C

    C

    C

    C

    C

    CC

    gGBW

    112

    1

    112

    1

    2_

    A. Matsuzawa, Analog IC Technologies for Future Wireless Systems, IEICE, Tan on Electronics, Vol. E89-C, No.4, pp. 446-454, April, 2006.

    We have developed the performance model for pipeline ADC that can treat technology scaling.

  • 2007.10.27 ASICON A. Matsuzawa

    7

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Scaling and analog device and circuit parameters

    ds2

    effox

    IVC

    L2W =

    (b)Cpi_N, Cpi_P,Cpo[fF/mA],p2_N,p2_P[GHz]

    (a)WN,WP[m/mA],VA_N, VA_P[V]

    D

    G

    S

    B

    gdC dbC

    gsC sbC

    dbC

    dsI

    Veff=0.175V

    DR

    DR

    L[m]0.1 0.2 0.3 0.4 0.51

    10

    100

    1000

    Cgd

    Cgs

    Cap

    . [f

    F/m

    A],

    f T[G

    Hz]

    W[

    m/m

    A]

    fT

    W

    2/1 S S: Scaling factor

    Gate width and capacitances decrease with technology scaling.

  • 2007.10.27 ASICON A. Matsuzawa

    8

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Determination of signal capacitance

    2

    19 21066.1

    sig

    N

    oV

    C

    DR[m]

    0.001

    0.01

    0.1

    1

    10

    100

    1000

    0.1 0.50.05

    Co[p

    F]

    8bit

    10bit

    12bit

    14bit

    Vin+vout-vout

    +

    2Veff

    Vdd-4V

    eff

    2V

    eff

    Vin-

    Vdd

    Output signal range

    Gain Boost

    amp.

    Larger resolution requires larger signal capacitance.Furthermore, Voltage lowering increases signal capacitance more.

    5.2V3.6V2.2V1.6V1.0VVsig_pp

    3.3V2.5V1.8V1.5V1.2VVdd

    0.35m0.25m0.18m0.13m90nm

    5.2V3.6V2.2V1.6V1.0VVsig_pp

    3.3V2.5V1.8V1.5V1.2VVdd

    0.35m0.25m0.18m0.13m90nm

  • 2007.10.27 ASICON A. Matsuzawa

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    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    10

    100

    1000

    10000

    0.01 0.1 1 10

    Ids[mA]

    fc[MHz]

    90nm 0.13m 0.18m 0.25m 0.35m

    Performance curve

    CoC

    po,C

    pi

    ds

    effo

    dsclose I

    VC

    IGBW

    3

    1_

    Cpi

  • 2007.10.27 ASICON A. Matsuzawa

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    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Performance summary

    12bit

    1

    10

    100

    1000

    10000

    0.01 0.1 1 10

    Ids[mA]

    fc[MHz]

    90nm 0.13m 0.18m 0.25m 0.35m

    bit

    1

    10

    100

    1000

    10000

    0.01 0.1 1 10

    Ids[mA]

    fc[MHz]

    90nm 0.13m 0.18m 0.25m 0.35m

    10bit

    0.1

    1

    10

    100

    1000

    0.01 0.1 1 10

    Ids[mA]

    fc[MHz]

    90nm 0.13m 0.18m 0.25m 0.35m

    12bit0.01

    0.1

    1

    10

    100

    0.01 0.1 1 10

    Ids[mA]

    fc[MHz]

    90nm 0.13m 0.18m 0.25m 0.35m

    14bit

    Scaled CMOS is effective for just low resolution ADC.Scaled CMOS is not effective for high resolution ADC.

  • 2007.10.27 ASICON A. Matsuzawa

    11

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Optimization of OpAmp in Pipelined ADC

    M. Yoshioka, M. Kudo, T. Mori, and S.

    Tsukamoto

    A 0.8V 10b 80MS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing,

    ISSCC, Dig. Tech. paper, pp. 452-453, 2007.

    90nm CMOS, near sub-threshold operation, and SC level-shifthave realized 10bit 80MHz ADC with 0.8V operation and small power of 6.5mW

  • 2007.10.27 ASICON A. Matsuzawa

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    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Results

    30

    40

    50

    60

    0.6 0.7 0.8 0.9 1 1.1 1.2 1.3

    SN

    DR

    [d

    B]

    30

    40

    50

    60

    0.6 0.7 0.8 0.9 1 1.1 1.2 1.3S

    ND

    R [

    dB

    ]

    Fclk=80MS/s, Fin=11MHz

    Ta=273K Ta=373K

    Slow/Slow

    Fast/Fast

    Supply Voltage [V]

    1P10M 90nm CMOSwith MIM Capacitors

    10bit 80MS/s

    0.8V

    55.0dB @2MHz51.4dB @41MHz

    6.5mW

    1.18mm x 0.54mm

    < 1.0LSB< 0.8LSB

    Technology

    ResolutionConversion Rate

    Supply Voltage

    SNDR

    Total Power Consumption

    Active Area

    INLDNL

    1.2Vp-p DifferentialInput Range1.2V

    56.9dB @2MHz55.6dB @41MHz

    13.3mW

    < 0.5LSB< 0.4LSB

    FoM=0.2pJ/step 0.08mW/MHz

  • 2007.10.27 ASICON A. Matsuzawa

    13

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Optimization of Veff

    Veff [V]Ids [mA]

    f c[M

    Hz]

    I ds[m

    A]

    Veff [V]

    f c[M

    Hz]

    12 bit, 0.18um CMOS 10 bit

    Blue: 0.18um

    Red: 90nm

    Optimum Veff is a function of resolution, current, and design rule.

    The lower Veff is recommended for scaled CMOS technology.

  • 2007.10.27 ASICON A. Matsuzawa

    14

    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Challenge to realize pipelined ADC without OpAmp

    Vx is reaching the virtual ground voltage asymptotically

    Conventional OpAmp

    Vx is reaching the virtual ground voltage with constant rate

    Comparator controlledcurrent source

    T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H. Lee, Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies, IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574-575. Feb. 2006.

    Comparator controlled current source can realize the virtual ground.

    Now challenge for not use of OpAmp in ADC design has started.

  • 2007.10.27 ASICON A. Matsuzawa

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    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Realistic comparator controlled current source

    I2

  • 2007.10.27 ASICON A. Matsuzawa

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    Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

    Results

    10b ADC FoM =0.3pJ/step, 0.3mW/MHz

    Small FoM, however not amazingly