Trends in high speed ADC design - · PDF file2007.10.27 ASICON A. Matsuzawa 1 Matsuzawa &...
Transcript of Trends in high speed ADC design - · PDF file2007.10.27 ASICON A. Matsuzawa 1 Matsuzawa &...
2007.10.27 ASICON A. Matsuzawa
1
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Trends in high speed ADC design
Akira Matsuzawa
Department of Physical Electronics
Tokyo Institute of Technology
2007.10.27 ASICON A. Matsuzawa
2
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Contents
• Introduction
• Technology scaling and performance of pipelined ADCs– Performance model of pipelined ADC
• Design challenge of high speed ADCs– Pipelined ADCs
• Optimization of OpAmp
• Comparator controlled Current sourcein stead of OpAmp
– Sub-ranging ADC
– Successive approximation ADCs
– Delta-sigma ADC
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Speed and power
High Speed ADC[Sampling Freq. VS Power]
1
10
100
1000
10000
1 10 100 1000 10000
Sampling Freq.[MSps]
Power[
mW
]
12Bit(Paper)
10Bit(Paper)
12Bit Products
10Bit Products.
JSSC,ISSCC,VLSI,CICC,ESSCC
& Products
(≧10Bit,≧
10MSps)1995-2006
MHzmWbit /3.0:10
MHzmWbit /1:12
10b12b
Conversion speed has saturated at 200 MHz Smaller mW/MHz is needed for low power operation.0.3mW/MHz for 10bit and 1mW/MHz for 12bit are the bottom lines.
200MHz
ISSCC 2007
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Pipelined ADC
1st stage
2nd Stage
SampleAmp.
SampleAmp.
Sample Amp. Sample Amp.
Transfer characteristics
Hold Sample Amplify
-Vref
+Vref
-Vref
+Vref
0 1
X2
-Vref
+Vref
-Vref
+Vref
0 1 0 1
X2
1st Stage 2nd Stage
Folding I/O characteristics makes higher resolution along with pipeline stages.
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
M5
Vbp2
Vbp1
VoutnVoutp
Vbn1
Vbn2
Vdd
VinpVinn
Vbp1
Technology scaling for analog
M5
Vbp2
Vbp1
VoutnVoutp
Vbn1
Vbn2
Vdd
VinpVinn
Vbp1
elVsig arg:
SignalCap.
ParasiticCap.
ParasiticCap.
ParasiticCap.
ParasiticCap. Parasitic
Cap.
ParasiticCap.
smallVsig :
SignalCap.
Technologyscaling
Technology scaling can reduce parasitic capacitances.
However signal capacitance will increase to keep the same SNR atlower voltage operation.
Parasitic capacitance ���� smallerOperating voltage ���� lowerSignal swing ���� lower
Signal capacitance ����largerVoltage gain ����lower
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Performance model for pipelined ADC
Cf
Cs Cpi gm Cpo COLRL2
1
1
p
s
ω+
OpAmpofpoleSecond
ceresisOutputR
cecapaciLoadC
cecapaciparaciticputputinputCC
loopfeedbackforcecapaciSignalCC
stageinputofcecTranscondug
p
L
oL
popi
fs
m
:
tan:
tan:
tan&:,
tan:,
tan:
2ω
βπ L
mclose
C
gGBW
2_ =
pisf
f
CCC
C
++=β
( )pisf
pisf
oLpoLCCC
CCCCCC
++
+++=
2
fs
oL
CCC
+= oLfso CCCC ===
OpAmp
++
+
+
=
++
+
+
=
o
dspi
o
dspo
o
dspieffo
ds
o
pi
o
po
o
pio
mclose
C
I
C
I
C
IVC
I
C
C
C
C
C
CC
gGBW
ααα112
1
112
1
2_
ππ
A. Matsuzawa, “Analog IC Technologies for Future Wireless Systems,” IEICE, Tan on Electronics, Vol. E89-C, No.4, pp. 446-454, April, 2006.
We have developed the performance model for pipeline ADC that can treat technology scaling.
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Scaling and analog device and circuit parameters
μ
ds2
effox
IVC
L2W =
(b)Cpi_N, Cpi_P,Cpo[fF/mA],ωp2_N,ωp2_P[GHz]
(a)WN,WP[μm/mA],VA_N, VA_P[V]
D
G
S
B
gdC dbC
gsC sbC
dbC
dsI
Veff=0.175V
DR
DR
L[μm]0.1 0.2 0.3 0.4 0.51
10
100
1000
Cgd
Cgs
Cap
. [f
F/m
A],
f T[G
Hz]
W[μ
m/m
A]
fT
W
2/1 S S: Scaling factor
Gate width and capacitances decrease with technology scaling.
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Determination of signal capacitance
2
19 21066.1
×≥ −
sig
N
oV
C
DR[μm]
0.001
0.01
0.1
1
10
100
1000
0.1 0.50.05
Co[p
F]
8bit
10bit
12bit
14bit
Vin+
vout-vout+
2Veff
Vdd-4V
eff
2V
eff
Vin-
Vdd
Output signal range
Gain Boost
amp.
Larger resolution requires larger signal capacitance.Furthermore, Voltage lowering increases signal capacitance more.
5.2V3.6V2.2V1.6V1.0VVsig_pp
3.3V2.5V1.8V1.5V1.2VVdd
0.35μμμμm0.25μμμμm0.18μμμμm0.13μμμμm90nm
5.2V3.6V2.2V1.6V1.0VVsig_pp
3.3V2.5V1.8V1.5V1.2VVdd
0.35μμμμm0.25μμμμm0.18μμμμm0.13μμμμm90nm
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
10
100
1000
10000
0.01 0.1 1 10
Ids[mA]
fc[MHz]
90nm 0.13μm 0.18μm 0.25μm 0.35μm
Performance curve
①Co≫C
po,C
pi
)(・π
ds
effo
dsclose I�
VC
IGBW ∝≈
3
1_
②Cpi
<Co<C
po
) (α
・π
tConsVC
GBWoeffo
close tan3
11_
+≈
③Co<C
po、C
o<C
pi
)(αα
・π dsdsoieffo
closeI
�IVC
GBW1
3
11_ ∝
+≈
①
③②fFCo 50=
Performance exhibits convex curve.There is the peak conversion frequency and the optimum current. Current increase results in increase of parasitic capacitances and decrease of conversion frequency in the higher current region.
α++
α+
α+
=
o
dspi
o
dspo
o
dspieffo
dsclose
C
I
C
I
C
IVC
IGBW
112
1_
π
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Performance summary
12bit
1
10
100
1000
10000
0.01 0.1 1 10
Ids[mA]
fc[MHz]
90nm 0.13μm 0.18μm 0.25μm 0.35μm
8bit
1
10
100
1000
10000
0.01 0.1 1 10
Ids[mA]
fc[MHz]
90nm 0.13μm 0.18μm 0.25μm 0.35μm
10bit
0.1
1
10
100
1000
0.01 0.1 1 10
Ids[mA]
fc[MHz]
90nm 0.13μm 0.18μm 0.25μm 0.35μm
12bit0.01
0.1
1
10
100
0.01 0.1 1 10
Ids[mA]
fc[MHz]
90nm 0.13μm 0.18μm 0.25μm 0.35μm
14bit
Scaled CMOS is effective for just low resolution ADC.Scaled CMOS is not effective for high resolution ADC.
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Optimization of OpAmp in Pipelined ADC
M. Yoshioka, M. Kudo, T. Mori, and S.
Tsukamoto
“A 0.8V 10b 80MS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing,”
ISSCC, Dig. Tech. paper, pp. 452-453, 2007.
90nm CMOS, near sub-threshold operation, and SC level-shifthave realized 10bit 80MHz ADC with 0.8V operation and small power of 6.5mW
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Results
30
40
50
60
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3
SN
DR
[d
B]
30
40
50
60
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3S
ND
R [
dB
]
Fclk=80MS/s, Fin=11MHz
Ta=273K Ta=373K
Slow/Slow
Fast/Fast
Supply Voltage [V]
1P10M 90nm CMOSwith MIM Capacitors
10bit 80MS/s
0.8V
55.0dB @2MHz51.4dB @41MHz
6.5mW
1.18mm x 0.54mm
< 1.0LSB< 0.8LSB
Technology
ResolutionConversion Rate
Supply Voltage
SNDR
Total Power Consumption
Active Area
INLDNL
1.2Vp-p DifferentialInput Range1.2V
56.9dB @2MHz55.6dB @41MHz
13.3mW
< 0.5LSB< 0.4LSB
FoM=0.2pJ/step 0.08mW/MHz
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Optimization of Veff
Veff [V] Ids [mA]
f c[M
Hz]
I ds[m
A]
Veff [V]
f c[M
Hz]
12 bit, 0.18um CMOS 10 bit
Blue: 0.18um
Red: 90nm
Optimum Veff is a function of resolution, current, and design rule.
The lower Veff is recommended for scaled CMOS technology.
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Challenge to realize pipelined ADC without OpAmp
Vx is reaching the virtual ground voltage asymptotically
Conventional OpAmp
Vx is reaching the virtual ground voltage with constant rate
Comparator controlledcurrent source
T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H. Lee, “Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574-575. Feb. 2006.
Comparator controlled current source can realize the virtual ground.
Now challenge for not use of OpAmp in ADC design has started.
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Realistic comparator controlled current source
I2<< I1
T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H. Lee, “Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574-575. Feb. 2006.
Time delay (Vx ���� Vo) causes voltage offset. Small inverse current source has been introduced. The offset voltage can be reduced and does not effect the conversion linearity.
10b, 8MHz ADC has been developed.Pd=2.5mW. Lowest Pd/MHz
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Results
10b ADC FoM =0.3pJ/step, 0.3mW/MHz
Small FoM, however not amazingly
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Sub-ranging ADC
7]Y. Shimizu, S. Murayama, K. Kudoh, H. Yatsuda, A. Ogawa, “ A 30mw 12b 40MS/s Subranging ADC with a High-Gain Offset-Canceling Positive-Feedback Amplifier in 90nm Digital CMOS,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 222-225. Feb. 2006.
Sub-ranging ADC also doesn't require OpAmp and suitable for LV operation.However it requires low offset voltage comparators.
Use of positive feedback technique has realized low offset voltage.
Positive Feedback
CKT
Pd/MHz =0.75mW/MHz which is lowest value!!
Technology revival has been found.
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Results
Attain high ENOB of 10.5-11.030mW at 40MHz 90nm CMOS 1V Operation
0.4pJ/step
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Successive approximation ADC
C C2
C4
C8
C16
C16
Vin Vref
C C2C2
C4C4
C8C8
C16C16
C16C16
Vin Vref
Binary weighted Capacitor array Comparator
D. Draxelmayr, “A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS,” IEEE, ISSCC 2004, Dig. of Tech. Papers, pp. 264-265, Feb. 2004.
Eight interleaved SA-ADCs with 90nm CMOSattain 600MHz operation.
Successive approximation ADC
SA-ADC
Successive approximation ADC has been used long time as a low power and low speed ADC. It doesn’t require OpAmp but capacitor array and comparator. Thus this architecture looks suitable for scaled and low voltage CMOS.
Now challenge for renewal of this conventional architecture has started.
2007.10.27 ASICON A. Matsuzawa
20
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Improvement of SA-ADC
Tracking
Phase
Tracking
Phase
MSB MSB-1 MSB-2 LSB
MSB MSB-1 MSB-2 LSB
Synchronous
Conversion Phase
Asynchronous
Conversion Phase
Sampling Instants
Sampling Instants
α
β+= 1radix
βα+=β 1
S. W. M. Chen and R. W. Brodersen, “A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13um CMOS,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574-575. Feb. 2006.
6bit 600MHz 5.3mW ADC has been realized with 0.13um CMOS
Asynchronous clock increases conversion frequency.Use of proper radix reduces capacitance.
Capacitor ladder with some radix number
Asynchronous clock
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Newest SAR ADC
DDi
Ui
REF VC2Q ⋅⋅⋅⋅==== ∑∑∑∑
Sample
VTP
Track Reset Comp
Result
B[0..N-1]
INp
Pre-
charge
cncp
CU
M=2N-1
421
INn
CLK cp[0..N-2]
cn[0..N-2]
VQP
VQNVTN
CSP
CSN
CTP
CTN
SAR Controller
J. Craninckx and G. Van der Plas,
“A 65fJ/Conversion-Step 0-to-0.7mW 9b Charge-
Sharing SAR ADC in 90nm Digital CMOS,” IEEE
ISSCC 20007, Dig. of Tech. Papers, pp.246-247,
Feb. 2007.
SAR ADC must be one of the good solution for scaled analog technology.No OPamp is needed.
No static power consumption.Higher signal swing and small capacitance
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Analog operation with capacitances
Precharge
TrackSample
VQp
VQn
Compare
c0pc0n
Precharge
CSP
VQP
CSN
c0n
c0p
c0p
c0nVQN
128CU
DDUINS VC128V
2
CQ ××××⋅⋅⋅⋅−−−−××××====
Precharge
...
VC64
VC128
V2
CQ
DDU
DDU
INS
±±±±
××××⋅⋅⋅⋅++++
××××⋅⋅⋅⋅−−−−
××××====
Capacitances can realize analog operation for SAR ADC.No static current is required and higher signal swing can be used.
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Results
1k 10k 100k 1M 10M
6
7
8
9
Input frequency [Hz]
EN
OB
Fs = 50MS/sP = 725µW
-YesYes650.297.820CS----SARThis work
-YesNo2202.655.3300SAR31.5
---1602.53.71250Flash31.1
---510159.250PL12.7
-NoNo1700.02510.50.1SAR12.5
---7602.58.77.9PL-CBSC12.4
---4403010.450Subr.12.3
---570399.4100PL12.1
NoNo-50013.812.64.4∆Σ3.4
YesYes-300501240CT∆Σ3.1
Dec.ClockRef.
FoM includesFoM
[fJ]
P
[mW]ENOB
Fs
[MS/s]Arch.
ISSCC06
Paper #
-YesYes650.297.820CS----SARThis work
-YesNo2202.655.3300SAR31.5
---1602.53.71250Flash31.1
---510159.250PL12.7
-NoNo1700.02510.50.1SAR12.5
---7602.58.77.9PL-CBSC12.4
---4403010.450Subr.12.3
---570399.4100PL12.1
NoNo-50013.812.64.4∆Σ3.4
YesYes-300501240CT∆Σ3.1
Dec.ClockRef.
FoM includesFoM
[fJ]
P
[mW]ENOB
Fs
[MS/s]Arch.
ISSCC06
Paper #
Amazing small FoM=65fJ/step has been attained.
8bit, 0.3mW at 20MHz
J. Craninckx and G. Van der Plas,
“A 65fJ/Conversion-Step 0-to-0.7mW 9b Charge-
Sharing SAR ADC in 90nm Digital CMOS,” IEEE
ISSCC 20007, Dig. of Tech. Papers, pp.246-247,
Feb. 2007.
2007.10.27 ASICON A. Matsuzawa
24
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
High resolution and high speed SAR ADC
To increase the resolution, a pre-amplifier is located in front of a comparator
M. Hesener, A. Hanneberg, D. Herbison, F.
Kuttner, and H. Wenske, “A 14b 40MS/s
Redundant DAR ADC with 480MHz Clock in
0.13um,” IEEE ISSCC 20007, Dig. of Tech.
Papers, pp.248-249, Feb. 2007.
Segmented capacitor array
2007.10.27 ASICON A. Matsuzawa
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Results
66mW66mW66mW66mWTotal power Total power Total power Total power 17mWDigital power49mWAnalog power
480MHzInternal clock frequency
40MHzSample frequency
±0.9V diff.Input range1.5VSupply voltage
66mW66mW66mW66mWTotal power Total power Total power Total power 17mWDigital power49mWAnalog power
480MHzInternal clock frequency
40MHzSample frequency
±0.9V diff.Input range1.5VSupply voltage
0.13um CMOS
FoM=0.14pJ/stepHigh ENOB of 13.5bit has been attained
High
High conversion rate of 40MS/s and low power of 66mW have been attained
2007.10.27 ASICON A. Matsuzawa
26
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Delta-sigma ADC
4
6
8
10
12
14
16
18
0.01 0.1 1 10 100 1000
FlashSubrangingpipelinedSARfolding
Delta-sigma
Nyquist ADC:
2
sigCVSNR ∝
Delta-sigma ADC:
α⋅∝ MCVSNR sig
2
In delta-sigma ADC, higher operating frequency can increase SNR.For higher resolution ADC, the delta-sigma method must be vital.
2007.10.27 ASICON A. Matsuzawa
27
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Wide-band delta-sigma ADC
50mW (analog), 6mW (digital)Power consumption
1.2VSupply voltage
71dB / 69dBPeak SNR / SNDR*
0.2pJ/conv. (FOM=P/(2^enob*2*BW))Figure-of-merit (FOM)
77dB (97dB @ 200kHz, 115dB @ 3kHz)Dynamic range*
0.5mm2Active chip area
>55dB (for -1MHz input tone)Image rejection
1Vp (differential)Max. input voltage
20MHz @ 10.5MHz IFBandwidth
340MHzSampling frequency
CT quadrature cascaded Σ∆ modulator (2-2, 4b)Architecture
90nm CMOS, 1P6MTechnology
50mW (analog), 6mW (digital)Power consumption
1.2VSupply voltage
71dB / 69dBPeak SNR / SNDR*
0.2pJ/conv. (FOM=P/(2^enob*2*BW))Figure-of-merit (FOM)
77dB (97dB @ 200kHz, 115dB @ 3kHz)Dynamic range*
0.5mm2Active chip area
>55dB (for -1MHz input tone)Image rejection
1Vp (differential)Max. input voltage
20MHz @ 10.5MHz IFBandwidth
340MHzSampling frequency
CT quadrature cascaded Σ∆ modulator (2-2, 4b)Architecture
90nm CMOS, 1P6MTechnology
(*1MHz input signal, signal bandwidth is 20MHz)
90nm CMOS、、、、BW=20MHz, DR(=SNR)=77dB, 50mmW, FoM=200fJ/conv.A
DC
1i
AD
C2
i
DAC2iDAC1i DAC3i
DAC1q
AD
C1
q
DAC2q DAC3q
AD
C2
q+
+-
- +
+-
- +
+-
- +
+-
-
+
+-
-+
+-
-+
+-
-+
+-
-
R2iR1i R3i R4i
R5i R6i R7i R8i
R5q R6q R7q R8q
R2qR1q R3q R4q
C1i C2i C3i C4i C5i C6i
C1q C2q C3q C4q C5q C6q
4b 4b
4b 4b
Vpi
Vmi
Vpq
Vmq
Y1i Y2i
Y1q Y2q
AD
C1
i
AD
C2
i
DAC2iDAC1i DAC3i
DAC1q
AD
C1
q
DAC2q DAC3q
AD
C2
q+
+-
- +
+-
- +
+-
- +
+-
-
+
+-
-+
+-
-+
+-
-+
+-
-
R2iR1i R3i R4i
R5i R6i R7i R8i
R5q R6q R7q R8q
R2qR1q R3q R4q
C1i C2i C3i C4i C5i C6i
C1q C2q C3q C4q C5q C6q
4b 4b
4b 4b
Vpi
Vmi
Vpq
Vmq
Y1i Y2i
Y1q Y2q
L. J. Breems, et., al.
“A 56mW CT Quadrature Cascaded SD Modulator
with 77dB in a Near aero-IF 20MHz Band.
ISSCC 2007, pp. 238-239.
Delta sigma ADCs have emerged as a strong rival to high resolution nyquist ADCs
2007.10.27 ASICON A. Matsuzawa
28
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Summary
• Technology issues due to technology scaling• Low voltage operation ���� small headroom
• Reducing voltage gain
• Small voltage swing ���� larger signal capacitance
• Difficult to realize high resolution ADCs
• Design challenges of ADCs
– Pipelined ADC
• Optimization of OpAmp
• Comparator controlled current source
– Revival of ADC architectures--- No use of OpAmps ----
• Sub-ranging ADC
• SAR ADC
– Delta-sigma ADC is increasing signal bandwidth
FURTHER READING
Click any one of the following links to be taken to a website which contains the following documents.
The following are some recent examples of Asynchronous ADC activity off the web.
6 bit Asynchronous December 2006Asynchronous ADC In CAD Mentor GraphicsAsynchronous Data Processing System ASYNCHRONOUS PARALLEL RESISTORLESS ADCFlash Asynchronous Analog-to-Digital ConverterNovel Asynchronous ADC ArchitectureLEVEL BASED SAMPLING FOR ENERGY CONSERVATION IN LARGE NETWORKSA Level-Crossing Flash Asynchronous Analog-to-Digital ConverterWeight functions for signal reconstruction based on level crossingsAdaptive Rate Filtering Technique Based on the Level Crossing SamplingAdaptive Level–Crossing Sampling Based DSP Systems A 0.8 V Asynchronous ADC for Energy Constrained Sensing Applications Spline-based signal reconstruction algorithm from multiple level crossing samplesA New Class of Asynchronous Analog-to-Digital ConvertersEffects of time quantization and noise in level crossing sampling stabilization
Here is some more background information on Analog to Digital converters.
A 1-GS/s 6-bit 6.7-mW ADCA Study of Folding and Interpolating ADCFolding_ADCs_Tutorialshigh speed ADC designInvestigation of a Parallel Resistorless ADC
Here are some patents on the subject.
4,291,299_Analog_to_digital_converter_using_timed4,352,999_Zero_crossing_comparators_with_threshold4,544,914_Asynchronously_controllable_successive_approximation4,558,348_Digital_video_signal_processing_system_using5,001,364_Threshold_crossing_detector5,315,284_Asynchronous_digital_threshold_detector_5,945,934_Tracking_analog_to_digital_converter6,020,840_Method_and_apparatus_for_representing_waveform6,492,929_Analogue_to_digital_converter_and_method6,501,412_Analog_to_digital_converter_including_a_quantizers6,667,707_Analog_to_digital_converter_with_asynchronous_ability6,720,901_Interpolation_circuit_having_a_conversio26,850,180_SelfTimed_ADC6,965,338_Cascade_A_D_converter7,133,791_Two_mean_level_crossing_time_interval
11.19.10_1.20PM [email protected] Sauer