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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Numerical Analysis of Asymmetric Differential Inductors
Masaki Kanemaru, Daisuke Imanishi, Kenichi Okada, and Akira Matsuzawa
Tokyo Institute of Technology, Japan
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Contents
●Background
●Matrix-Decomposition Technique
●Simulation & Measurement Results
●Summary
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Background Miniaturization of CMOS process →Difficulty of characterize on-chip inductors
Degradation of circuit performances
●On-chip differential inductor Used for LC-VCO, differential LNA, Mixer… Mismatch between left and right halves degrades circuit performances.
Accurate modeling of on-chip symmetric inductor → Extract of asymmetric parameters
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Symmetric inductor analysis
•3-port symmetric inductor analysis in various operation modes [1] -Circuit parameters are extracted by numerical optimization -Symmetry is assumed in the parameters
•Asymmetric properties are estimated from Y11 and Y22 [2] -The difference is involved in only difference in shunt parasitic components
)Re( )Im()Im(1 )()(
)(2
diff
diff diffdiffdiff
222113121123
1323
diff
diff diff
Z ZQZL
YYYYYY YY
I VZ
==∴
−−− +
==
ω
[1] K. Okada, et al., EuMC, Oct. 2007, pp. 520– 523. [2] Y. Aoki, et al., EuMC, Oct. 2007, pp. 339–342.
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Proposed method by Matrix-Decomposition Technique
Extract π−type equivalent circuit3port S-parameter
port3(C.T.)
port1 port2
・Physically reliable parameters can be extracted. ・The mismatch can be accurately evaluated.
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Contents
●Background
●Matrix-Decomposition Technique
●Simulation & Measurement Results
●Summary
2008/12/18 M. Kanemaru, Tokyo Tech.
7
Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Overview subcmeas YYY +=
vYYi meas 3
2
1
meas
3
2
1 =
⎟⎟ ⎟
⎠
⎞
⎜⎜ ⎜
⎝
⎛ =
⎟⎟ ⎟
⎠
⎞
⎜⎜ ⎜
⎝
⎛ =
v v v
i i i
1 2
sub1 sub3 sub2
1 2
3
1 2
3
1 2
3
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Yc: Inductor core
Ysub: Interlayer-dielectric and Si substrate
●All ports have common voltages Yc can be ignored → Ysub is calculated from Ymeas
●Yc is calculated from Ymeas and Ysub ●Zcore is derived from Yc by converting matrix
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Calculation of Ysub Voltages of each port are equal
⎟⎟ ⎟
⎠
⎞
⎜⎜ ⎜
⎝
⎛ +
⎟⎟ ⎟
⎠
⎞
⎜⎜ ⎜
⎝
⎛ =
⎟⎟ ⎟
⎠
⎞
⎜⎜ ⎜
⎝
⎛ =
⎟⎟ ⎟
⎠
⎞
⎜⎜ ⎜
⎝
⎛
a
a
a
sub
a
a
a
c
a
a
a
meas
3
2
1
v v v
v v v
v v v
i i i
YY
Y
meas33meas32meas31sub3 yyyy ++=
Ymeas
Yc
Ysub
→No current flows through zn
=0
⎟⎟ ⎟
⎠
⎞
⎜⎜ ⎜
⎝
⎛ =
sub3
sub2
sub1
sub 00
00 00
y y
y Y
meas13meas12meas11sub1 yyyy ++=
meas23meas22meas21sub2 yyyy ++=
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Conversion of matrix Yc to Zcore subsmeac YYY −= ′
Matrix Yc is converted into matrix Zcore
zcorez 212
121 core iZvZ =⎟⎠
⎞ ⎜ ⎝ ⎛ −
−= zMj Mjz
ω ω
cY
⎟ ⎠ ⎞
⎜ ⎝ ⎛=⎟
⎠ ⎞
⎜ ⎝ ⎛=⎟
⎠ ⎞
⎜ ⎝ ⎛
− −=⎟
⎠ ⎞
⎜ ⎝ ⎛=
2
1
2
1 z
32
31
2
1 z i
i i i
vv vv
v v
z
z
z
z iv
vYYi c 3
2
1
c
3
2
1 =
⎟⎟ ⎟
⎠
⎞
⎜⎜ ⎜
⎝
⎛ =
⎟⎟ ⎟
⎠
⎞
⎜⎜ ⎜
⎝
⎛ =
v v v
i i i
Obtain converting matrix A and B
e.g.) 1 2
1 23
z1 z2
1 23
1 23
z1 z2
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Define Zcore by 2×2 matrix
⎟ ⎠ ⎞⎜
⎝ ⎛=⎟
⎠ ⎞⎜
⎝ ⎛
− −= 0
0 1 0
0 1
1 1
1 0
0 1 BA
BT can be A* AA*=I
BiiAvv == zz
1 ccore *)(
−= ABYZ c
c
BYZA vBYZBiZAv
core
corecore
=
==
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Contents
●Background
●Matrix-Decomposition Technique
●Simulation & Measurement Results
●Summary
2008/12/18 M. Kanemaru, Tokyo Tech.
11
Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Mismatch of ground loop
1
3
2
GND
1 2
GND
3
Even
Odd
Flux loss: Only half side Flux loss: Both sides
The inductance mismatch depends on the number of turns.
Each loss is different Mismatch
Each loss is almost equal Mismatch
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Simulation model
・Inductance mismatches are evaluated by the proposed method. ・The mismatches are plotted as a function of ∆x.
x
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Simulation Result
∆x (µm)
0 0 50 100 150
2
4
6
8
10
12
L m
is m
at ch
(% ) 1 turn
2 turn
200
3 turn
・The mismatch of 2-turn is smaller than 1- and 3-turn ・Increasing ∆x, mismatch decreases
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Measurement
Line width:9µm, Line space:2µm Inner diameter:100µm, Turn:3
0.18 µm Si-CMOS
AsymmetricSymmetric
VNA : 4port 10MHz-67GHz E8361A+N4421BH67(Agilent)
Probe : I67-D-GSGSG-150 (Cascade) I67-GSG-150 (Cascade)
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Measurement Result
1.0 0.5
0.6
0.7
0.8
Frequency [GHz]
In du
ct an
ce [n
H ]
0.5
0.6
0.7
0.8
In du
ct an
ce [n
H ]
10 20 1.0 Frequency [GHz]
10 20
left-half right-half
left-half right-half
Mismatch1.5% 4.0%
Symmetric Asymmetric
・ Influence of asymmetric ground loop is extracted ・Other reasons to cause asymmetry exist
2008/12/18 M. Kanemaru, Tokyo Tech.
16
Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Contents
●Background
●Matrix-Decomposition Technique
● Simulation & Measurement Results
●Summary
2008/12/18 M. Kanemaru, Tokyo Tech.
17
Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Summary
The numerical analysis using the matrix-decomposition technique is proposed
・Physically reliable parameter can be extracted ・The mismatch can be accurately evaluated
Proposed method is applied to 1-, 2-, and 3-turn differential inductors
Influence of asymmetric ground loop can be accurately extracted
2008/12/18 M. Kanemaru, Tokyo Tech.
18
Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Q factor
AsymmetricSymmetric
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.
Extract Ymeas’ Ymeas
・Zshort and Yopen are removed by Open-Short de-embedding 1
openshort 1
openmeassmea )()( −−
′ −−