A Fractional-N Sub-Sampling PLL using a Pipelined Phase ... · Matsuzawa & Okada Lab. A...

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Matsuzawa & Okada Lab. A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator aided DTC T.N. Aravind , M. Katsuragi, K. Kimura, K. Okada, and A. Matsuzawa Tokyo Institute of Technology, Japan

Transcript of A Fractional-N Sub-Sampling PLL using a Pipelined Phase ... · Matsuzawa & Okada Lab. A...

Page 1: A Fractional-N Sub-Sampling PLL using a Pipelined Phase ... · Matsuzawa & Okada Lab. A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator aided DTC T.N. Aravind,

Matsuzawa& Okada Lab.

A Fractional-N Sub-Sampling PLL using a Pipelined

Phase-Interpolator aided DTC

T.N. Aravind, M. Katsuragi, K. Kimura,K. Okada, and A. Matsuzawa

Tokyo Institute of Technology, Japan

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Contents

Motivation Conventional Architectures Proposed Technique Noise Considerations Measurement Conclusion

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Wireless carrier generation requires fractional-N PLL.

Fractional operation introduces additional noise.

Conventional synthesizer architectures:

CP Based: Poor close-in phase noise.

TDC Based: Power-jitter trade-off.

Injection Locking: Large spurious.

Sub-sampling: Power-jitter tradeoff.

Motivation

Aim: Low-power high-purity fractional-N PLL

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Matsuzawa& Okada Lab.[K. Raczkowski, RFIC 2014][Po-Chun Huang, ISSCC 2014]*[G. Marucci, ISSCC 2014]

Fractional-N SS-PLL: Prior Art

DTC in reference path enables fractional operation

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DTC with large dynamic range is required

DTC Only Architecture: Challenges

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Dynamic range requirements are relaxed

Proposed Technique

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Matsuzawa& Okada Lab.[A. Abidi, JSSCC 2006]

DTC

Phase-Interpolator

Jitter Considerations

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Large Dynamic Range [d.r.], Fine Resolution [res.]

Power-Jitter-Resolution trade-off.

Large d.r. and Fine res. => ‘∆C’ must be large enough to assure PVT robustness.=> ‘I’ needs to be kept high for low jitter.

Intuitive Analysis: DTC Only

𝝉𝝉d.r.

𝝉𝝉res.

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Small Dynamic Range [d.r.], Fine Resolution [res.]

Small d.r. and Fine res. => Small ‘𝝉𝝉d.r.’=> ‘I’ can be kept acceptably high for lower jitter.

Intuitive Analysis: PI assisted DTC

𝝉𝝉d.r.

𝝉𝝉res.

Proposed architecture reduces dynamic range and hence jitter.

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Proposed Fractional-N SSPLL

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Chip Micrograph

Stacked capacitors are used for area reduction[PSL: Phase Switch Logic] [SSL: Sub-sampling Loop] [PI: Phase Interpolator]

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Measurement Results

Division ratio for fractional-N: 50.163

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Comparison with SOA

This work [1] [2] [3]Architecture SSPLL SSPLL MDLL TDCFreq. [GHz] 4.1-5.1 2.2-2.4 1.6-1.9 2.412-2.484

4.915-5.825 Power [mW] 3.8 17.3 3 9.5Area [mm2] 0.2 0.75 0.4 0.3

Phase Noise (in-band)

-112@400kHz

-112@50kHz

-112@100kHz

-106@100kHz

Integrated Jitter 254.4fs 266fs 1.4ps 173fs

FoM [dB] -246.1 -239.1 -233.76 -245.5

CMOS Tech. 65nm 180nm 130nm 28nm FDSOI

•[1] Po-Chun Huang, ISSCC 2014 [2] G. Marucci, ISSCC 2014 [3] X. Gao, ISSCC 2015

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Conclusion

• A fractional-N SSPLL architecture is presented. • The proposed architecture uses a combination

of DTC and phase-interpolator

– Reduces intrinsic jitter from the multi-phase generator.

– Power-jitter-resolution tradeoff is mitigated.

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Worst case jitter is much smaller in phase-interpolator.

Digital-to-TimeConverter

PhaseInterpolator

[A. Abidi, JSSCC 2006]

Jitter Considerations

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Matsuzawa& Okada Lab.[X. Gao, ISSCC 2009]

Lower N implies lower close-in noise. Operation is limited to Integer-N.

•Rad

ians

2 / H

z

f

Sub-Sampling PLL: An Overview


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