Ultra-long MicroStrip Gas Counter for Spallation Neutron Source Facilities
Timing Requirements for Spallation Neutron Sources
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Transcript of Timing Requirements for Spallation Neutron Sources
Timing Requirements for Spallation Neutron Sources
• Timing system clock synchronized to the storage ring’s revolution frequency.– LANSCE: 2.7951389 MHz (1/72 of the 201.25 MHz Acclerator RF
frequency)
– SNS: Variable. 1.027323 - 1.097502 MHz. Not derived from the Accelerator RF.
Timing Requirements for Spallation Neutron Sources
• The end of the cycle is more important than the beginning of the cycle.– Large, high inertia, “T0” neutron choppers define when the
beam is extracted from the ring. Most of the other important timing signals (beam and RF gates) end at the “Extraction Time” and derive their starting times by working backwards from the Extraction Time.
– Multiple beam lines require multiple choppers to be synchronized by the timing system.
– Compromise between keeping a stable “Extraction” reference signal for the choppers and not drifting too far away from the AC line phase for the RF system.
Basic Characteristics of SNS Timing System
• Event System.– 256 events possible. 25 events currently in use.
• ~5 millisecond machine cycle. 60 Hz.– Option to go to 120 Hz. when second target added.
• 10 second super-cycle.• Clock synchronized with ring RF.
– Ring RF is 1.057767 Mz at 1 GeV
– Clock is 32 X Ring RF
Timing System Components of SNS Timing System
Ring RF
TimingReferenceGenerator
NeutronChoppers
ACLine
SNS EventLink
Master
X32 PLL(33 MHz)
SNS RealTime Data
LinkMaster
10 MHzCrystal
Osc.
TimingSlave
(V124S)
MachineProtection
System
ICS IOC'sSNS Utility
Module
LEBTChopper
*4 PLL(64 MHz)
ExperimentalHalls
Diagnostics
RTDLEventLink
MasterTiming IOC
GPS
SNS Time StampsBeam data
RF GatesExtraction KickersTxHV Gates
High resolution timestampsMachine Modes
SNS TimestampsRemote ResetSynchronous ISR’s
Beam DelayBeam PhaseMicro pulse widthMacro pulse width
SNS Time stampsDelaysGatesTriggers
Timing SystemHardware
Timing System Users Experimental Systems
Subsystem Hardware
Two SNS Transmission Links
• Event Link– Transmits the timing events that define a machine cycle.– Each event is 8 bits plus parity (256 events maximum).– Clock is variable and derived from the ring revolution
frequency (32 * Frev).– Events 0 – 63 are generated by the timing system hardware.– Events 64 – 255 are generated by software (no fixed times).
• Real-Time Data Link (RTDL)– Transmits machine parameters and data prior to every new
cycle.– 128 frames possible (expandable to 255).– Each frame contains an 8-bit frame number, 24-bits of data,
and an 8-bit CRC.– Clock is 10 MHz.
Sample SNS RTDL Data Frames
Frame Number Data1 – 3 Time of day
4 Event link period 5 MPS mode 6 60 Hz phase error
7 Beam Width15 IOC Reset Address17 Pulse Flavor
18-21 RF Gate Widths24 Previous Pulse
Status25 Cycle
255 24-bit CRC (calculated)
Real-TimeData Link
(RTDL)
ExtractMPS FPAR
EventLink
End Injection
SNS Machine Cycle Timeline
0 2 ms1 ms 6 ms4 ms 7 ms5 ms 8 ms3 ms
AnytimeAnytime
Informational Events, non critical timingTime Critical Events, (soft events disabled)
RTDLTransmit
Snapshot, 1Hz, 6Hz,
etc… RTDL Valid
RTDL parameter transmission
(for next cycle)
RF & High Voltage Events
MPS FPL
System xxx Trigger Events
(Alternate) Cycle Start
Machine
+60 Hz ZeroCrossing
-60 Hz ZeroCrossing
Line-SynchReference
Clock
Beam OnCycle Start
Mostly Stable Triggers Beam On Range
Allowed Range for Variable Triggers
Extraction Kicker Charge
beam accumulation
Basic Characteristics of LANSCE Timing System
• “Gate” rather than “Event” driven system.
• 96 independent timing gates 82 gates in use.
• 8.3 millisecond machine cycle (120 Hz).
• 1 second super-cycle.
• Clock synchronized with ring RF.
– 2.7951389 MHz.
Current Architecture of LANSCE Timing System
• Star configuration
• 4 redundant gate generator sets in 2 CAMAC crates.
• Gate generators are loaded by Master Timer computer, then run independently.
• Master Timer computer checks the output of the gate generators and automatically switches to another set when a discrepancy is seen.
RICE
CAMAC
ISS DATACONCENTRATOR
RICE
CAMAC
ISS DATACONCENTRATOR
Master Timer
MUX
TimingDistribution
Timing Gates
TimingGate
Generators