990 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39. NO. 4, APRIL 1992

The Effect of Temperature on Lateral DMOS Transistors in a Power IC Technology

Gary M . Dolny, Senior Member, IEEE, Gerald E. Nostrand, Member, IEEE, and Kevin E. Hill, Member, IEEE

Abstract-A systematic study of the effects of elevated tem- perature on the lateral DMOS power transistors in a power integrated circuit technology is presented. A eomprehensive ex- perimental characterization of the important LDMOS electri- cal parameters over the temperature range 30-300°C is re- ported. Simple, analytic models are used to explain the observed behavior and to offer physical insight into the effects of tem- perature on LDMOS performance. A novel test structure is uti- lized to unambiguously separate channel-region effects from drift-region effects. Using this structure it is shown that the LDMOS channel mobility follows a T - 2 temperature depen- dence, which is significantly more severe than the T - ' depen- dence of conventional CMOS channel mobility. Other key tem- perature-dependent parameters include the threshold voltage, on-state resistance, saturation current, breakdown voltage, and leakage current, which is shown to place a fundamental limi- tation on the high-temperature operation of the LDMOS tran- sistor.

I. INTRODUCTION WER integrated circuits which combine high-per- p" formance digital CMOS, bipolar analog components,

and power DMOS output devices offer considerable ad- vantages over conventional designs in discrete or hybrid form. These include improved system performance, re- duced size and weight, simplified circuit design, and po- tentially improved reliability.

Numerous applications for power integrated circuits are emerging, which require operation at high temperatures. The most important of these are automotive and aircraft controls, where ambient temperatures may be consider- ably higher than the conventional 125 "C requirement. While the high-temperature behavior of low-voltage CMOS and bipolar transistors has received considerable attention in the literature [ 11-[9], there has been little data published regarding the high-temperature characteristics of lateral DMOS power transistors, which are an impor- tant element of power IC's. Recent work [lo] has begun to address this need, but thus far has been limited to the modeling of only a few electrical parameters over a rela- tively narrow temperature range, without extensive ex- perimental verification. Clearly, a more complete and

Manuscript received September 26, 1990; revised August 1, 1991, The

G. M. Dolny and G. E. Nostrand are with the David Sarnoff Research

K. E. Hill is with General Electric Company, Aerospace Control Sys-

IEEE Log Number 9105922.

review of this paper was arranged by Associate Editor T. P. Chow.

Center, CN 5300, Princeton, NJ 08543-5300.

tems Department, Binghamton, NY.

00 18-9383/92$03

systematic understanding of the effects of high tempera- tures on the electrical characteristics of LDMOS power transistors is required.

This paper presents a comprehensive study of the ef- fects of temperature on LDMOS devices both theoreti- cally and experimentally. New experimental data on the temperature dependence of the key LDMOS electrical pa- rameters such as threshold voltage, mobility, on-state re- sistance, breakdown voltage, and leakage current over the range of 30-300°C are reported. Simple, analytic models are used to explain the observed data and offer insight into the physical origin of LDMOS temperature behavior. The data and models are valid at normal operating tempera- tures as well as in the high-temperature regime. Finally, the consequences of these results on the design and per- formance of power integrated circuits for high-tempera- ture applications are discussed.

11. DEVICE FABRICATION AND CHARACTERIZATION A cross-sectional view of the LDMOS devices under

study is shown in Fig. 1. The devices were fabricated on p-type substrates using a junction-isolated, twin-well, power IC technology, the details of which have been pre- sented elsewhere [ 111.

The LDMOS device depicted in Fig. 1 can be consid- ered as an enhancement-mode MOSFET (active channel) in series with a bulk resistance (drift region). At the high gate voltages necessary to invert the channel, there is also an accumulation layer beneath the extension of the poly- silicon gate over the lightly doped drift region. At low drain voltages typical of the LDMOS in its on-state, this accumulation layer acts like an equipotential source for electrons [ 121.

To properly characterize the temperature behavior of the LDMOS device it is necessary to unambiguously sep- arate channel-region effects from drift-region effects. This is accomplished with the aid of the test structure shown in Fig. 2. This structure was fabricated on the same wafer as the high-voltage LDMOS devices by self-aligning the n+ drain implant to the polysilicon gate thus eliminating the n-type drift region. Since the structure of Fig. 2 uses the identical gate oxidation and p-body processing as the power LDMOS, its electrical characteristics will accu- rately replicate those of the power LDMOS channel re- gion. The temperature characteristics of the drift region were obtained independently of those in the channel from

.OO 0 1992 IEEE

DOLNY ef al.: EFFECTS O F TEMPERATURE ON LATERAL DMOS TRANSISTORS 99 1

POLY GATE SOURCE

P-BODY N- DRIFT REGION

DOUBLE-DIFFUSED CHANNEL REGION

P- SUBSTRATE

Fig. I . Cross section of lateral DMOS device structure used for tempera- ture characterization. The p + source-body short is not shown.

The temperature dependence of the intrinsic concentra-

(3)

In the temperature range under consideration, the vari- ation of the energy gap with temperature is small, and negligible error is introduced by assuming ER is indepen- dent of temperature [15].

The variation of the DMOS threshold voltage with tem- perature is found by combining (1)-(3) and differentiat- ing, which yields

tion ni is given by [14]

n,(T) = 3.87 X 10'6T3/2e-Ex/2kT.

POLY GATE SOURCE DRAIN

P-WELL P-BODY

Fig. 2. Cross section of test structure used to isolate channel-region effects from drift-region effects.

measurements made on four-terminal resistors fabricated in the n-well material in which the drift region was formed. In addition to those described above, the test ve- hicle contained a variety of bipolar, diode, CMOS, resis- tor, and capacitor structures to allow a complete charac- terization of all phases of the technology.

A Hewlett-Packard model 4 145 semiconductor param- eter analyzer controlled by a Hewlett-Packard model 9000 computer was used to measure the device characteristics presented in this paper. A Wentworth Laboratories probe station provided means for electrical connection to the de- vices while a Wentworth Laboratories model TClOO Tempchuck system controlled the wafer temperature to an accuracy of k1"C. A custom designed enclosure pro- vided shielding from stray electrical noise and ambient light. A UNIX workstation with software written for this installation provided the capabilities for controlling the test, analyzing and displaying device characteristics, and organizing the information derived from the measure- ments.

111. DEVICE PERFORMANCE A. Threshold Voltage

The threshold voltage of a DMOS device 1131

J2E4",(4 Wf 1 vth(T) = +m + 2+f + c ox

where Nmax(x) I s the maximum net dopant concentration in the p-body region.

The temperature dependence of (1) comes about pri- marily through the Fermi potential which is written as

(4) Fig. 3 plots both the measured and calculated threshold

voltage of a typical n-channel LDMOS device over the temperature range of 30-300°C. The data show a thresh- old voltage variation of -5.2 mV/"C, which is signifi- cantly higher than the variation typically observed in con- ventional CMOS. This is due to the heavier doping in the double-diffused channel, which gives rise to a higher value of +f compared to conventional CMOS.

B. Channel Mobility The DMOS channel mobility was deducted from a first-

order one-dimensional model in the linear mode which is applicable for small drain voltages [ 161.

The DMOS mobility measurements were made on the device structure of Fig. 2 so that the channel-region ef- fects could be separated from those of the drift region. Fig. 4 plots the experimental data for the DMOS structure along with similar data from a conventional CMOS struc- ture on the same wafer which utilized identical gate oxi- dation and polysilicon gate processing.

Fig. 4 shows that the temperature dependence of the channel mobility can be modeled as

where m = 2.5 for the DMOS device and 1.5 for the CMOS.

The T-2 .5 temperature dependence observed for the DMOS channel mobility is significantly more severe than the T-'.' dependence commonly observed in conven- tional CMOS [7], [ 171-[ 191. Since the two devices were processed identically, the difference in mobility variation cannot be attributed to differences in processing condi- tions. The -2.5 power dependence of the LDMOS is equal to the normal bulk-mobility temperature depen- dence which results from acoustic, intervalley, and opti- cal-phonon scattering.

992 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 4, APRIL 1992

Tempemlure (C)

Fig. 3 . Variation o f n-channel LDMOS threshold voltage with tempera- ture. Measured values obtained from zero-current extrapolation o f linear region characteristics.

Fig. 5 . Variation of DMOS channel resistance with temperature. V,.\ = 6 V.

10

Temp (K)/300

Fig. 4. Temperature dependence of channel mobility for n-channel LDMOS and conventional CMOS devices. The LDMOS shows a T - * ' temperature variation while the NCMOS shows a T - ' ' behavior.

The higher than expected temperature dependence of DMOS mobility may be explained by the diffuse-scatter- ing model of Baccarini et a l . [19]. This model predicts that the temperature dependence of the inversion-layer mobility is a consequence of the simultaneous variation of both the carrier relaxation time, which varies as T - 2 . 5 , and the Fermi level. The experimental data imply that in the DMOS structure, the carrier mobility is dominated by the relaxation time, while in the conventional CMOS the Fermi level term plays a greater role. This is possibly due to the higher peak-doping concentration and graded do- pant profile in the double-diffused channel of the DMOS device.

C. On-State Resistance The on-state resistance of the LDMOS transistor can be

written as the sum of a channel component and a drift- region component.

Rdson = Rch -k &rif t . (7)

The channel component can be written as

reduce Rch. For the large gate-to-source voltages typical of the LDMOS in the on-state, the mobility term domi- nates and the channel resistance exhibits a positive tem- perature coefficient. This can be seen from Fig. 5 , which plots the channel resistance measured from the device structure of Fig. 2 along with the values computed from (8) as a function of temperature.

The drift region resistance of the LDMOS has been modeled as [20]

where Ll is the effective length of the drift region, rl is the effective radius of the current source at the end of the channel, and r2 is the effective radius of the current sink at the n+ contact. The only temperature-dependent term in (9) is the resistivity which, for the lightly doped drift regions typical in power LDMOS devices, exhibits a pos- itive temperature coefficient due to the decrease in bulk mobility with temperature.

For large gate voltages corresponding to strong inver- sion, the mobility effects dominate and (7)-(9) predict an increase in on-state resistance with temperature. This in- crease is shown in Fig. 6 which plots the measured on-state resistance of the LDMOS structure of Fig. 1.

At a sufficiently high temperature, the intrinsic carrier concentration from (3) becomes equal to the net n-type impurity concentration in the n-type drift region. This de- fines the so-called intrinsic temperature of the material. For temperatures higher than this, the drift-region resis- tance will decrease, due to the exponential increases in the number of thermally generated carriers. Although for the devices under study the intrinsic temperature is out- side of the 30-300°C range, this effect must be consid- ered for higher voltage structures which may incorporate lighter drift-region dopings.

D. Saturation Current The measured, room-temperature, LDMOS drain char-

acteristic curves are shown in Fig. 7. The data show that for the bias range of interest the drain-to-source saturation current fits a simple square-law relationship

L (8)

For a fixed value of gate voltage, the temperature de- pendence of the channel resistance is determined by two competing mechanisms. Decreases in channel mobility with increasing temperature tend to increase the channel resistance while the decreases in threshold voltage tend to

wpeff(T)cox(vgs - vth(T)) ', Rch =

(10) peff(T)Cox W

( v g s - vth(T>)2. 2L Ids =

DOLNY el ul EFFECTS OF TEMPERATURE ON LATERAL DMOS TRANSISTORS 993

3000 7

t I 0-

100 200 300 Temp (C)

Fig. 6 . Variation of LDMOS on-state resistance with temperature. =

10 v.

vds

Fig. 7 . Room-temperature LDMOS drain characteristic curves indicating square-law dependence of saturation current on gate voltage. V8$ = 6, 5 , 4, and 3 V.

The measured square-law relationship indicates that the saturation current is not limited by velocity saturation for these structures in the bias range of interest.

Differentiating (10) with respect to temperature yields

(11) 1 %eff Laid.---- -

I</., aT l e f i aT ( V g . ~ - Vth) aT For an n-channel LDMOS both the effective mobility

and threshold voltage have negative temperature coeffi- cients while the V,s,y - Vth term is positive. Thus depend- ing on the relative magnitude of the two terms, the tem- perature coefficient of the saturation current may be positive, negative, or zero. For small values of gate volt- age and correspondingly small values of drain current, the threshold-voltage term dominates, and the saturation cur- rent exhibits a positive temperature coefficient. For larger gate voltages, the mobility term dominates and the satu- ration current decreases with increased temperature. For the special case in which

the drain-to-source current remains constant with temper- ature defining the so-called zero-temperature-coefficient bias condition. This is illustrated experimentally in Fig. 8, which plots I',,, versus gate voltage as a function of tem- perature for the LDMOS structure of Fig. 1. The data show the expected behavior, with the zero-temperature- coefficient point at gate-to-source potential of approxi- mately 4.0 V .

8, I

!P 2 3 4 5 6 7

- 30 -+- 125 - 175 --b 250

vg, ( v o w

Fig. 8. LDMOS saturation drain current as a function of temperature and gate voltage showing zero-temperature-coefficient bias point at V<,, =

4.0 V .

E. Leakage Current It is well known that the leakage current across a re-

verse-biased p-n junction consists of a generation com- ponent and a diffusion component and can be written as 121, p. 911

In (13), A is the total area of the reverse-biased drain junction. For a high-voltage LDMOS in a junction-iso- lated technology, the area is the sum the n- /p-body junc- tion defining the edge of the channel, and the n-drift-re- gion/p-substrate isolation junction.

The leakage current increases exponentially with tem- perature with the generation component increasing as exp ( - E R / 2 k T ) and the diffusion component increasing as exp ( - E / k T ) . This behavior is shown in the measured data of Fig. 9 in which, as expected, the generation component dominates for temperatures lower than 150°C while the diffusion component dominates for temperatures above this value.

The exponential increase in leakage current imposes a fundamental restriction on the maximum temperature of operation of the power LDMOS device. At sufficiently high temperature, the leakage current becomes compara- ble to the on-state current. This prevents any reasonable turn-off of the device and, for high voltages, leads to very high power dissipation in the off-state. This is illustrated by Fig. 10 which plots the subthreshold characteristics of the high-voltage LDMOS device of Fig. 1. From Fig. 10 it is seen that for temperatures above 250°C the on-state current is less than an order of magnitude larger than the leakage current.

To increase the maximum operating temperature the drain leakage current must be reduced. This can be ac- complished by reducing the junction area. For typical power LDMOS structures, the high-temperature leakage is dominated by the n-/p-substrate junction, which can be significantly larger than the n-/p-body junction. Use of a dielectric isolation technology will eliminate the n- /p-substrate junction, resulting in significant improve- ment to the high-temperature leakage characteristics.

994 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 4, APRIL 1992

:T C l Diffusion Limited

Generation Limited

10“

25 30 35

Generation Limited

10“

25 30 35 l/kT

Fig. 9. LDMOS drain leakage current as a function of temperature.

1 .04

1 . 0 5

1.04

1 .07

1 . o - ~

1.0.”

1.0’2

3 2 1.04 -75

-100 -125 -150 -175 -200 -225 -250 -275

0.0 1.0 2.0 3.0 4.0

“w

Fig. 10. LDMOS subthreshold characteristics as a function of tempera- ture. The curves show that for sufficiently high temperature the leakage currents (Vx, = 0) become comparable to the drive current (Vq$ = 4.0 V).

F. Breakdown Voltage The geometry of the LDMOS transistor is such that a

two-dimensional numerical analysis is necessary for ac- curate simulation of the drain-to-source breakdown volt- age. This is mainly due to depletion-layer curvature, field shielding due to overlap of the polysilicon gate electrode over the lightly doped drift region, and charge-sharing ef- fects in RESURF-type structures. For the case of thick epitaxial layers, an approximate expression has been de- rived for the breakdown voltage [22] as given by

Equation (14) can be used to qualitatively understand the temperature dependence of the LDMOS drain-to- source breakdown voltage. Carriers accelerated by an electric field lose energy through collisions with optical phonons. As the temperature increases, the mean free path decreases, requiring a higher field to allow the carriers to obtain sufficient energy to initiate impact ionization [2 1 , pp. 106-1071. On this basis, the LDMOS drain-to-source breakdown voltage is expected to exhibit a small positive temperature coefficient. This behavior is observed exper- imentally in Fig. 1 1 .

IV. CONCLUSION A comprehensive study of the effects of high tempera-

tures on the electrical characteristics of LDMOS transis- tors used in a power IC technology has been presented.

- BVd&Volts) g 100

40 20

100 200 300

Temp (C)

Fig. 1 1. LDMOS drain-to-source breakdown voltage as a function of tem- perature.

The results of this study indicate that the major limitation to the maximum operating temperature of the LDMOS de- vice is the exponential increase in drain-to-source leakage current, which can become comparable to the drive cur- rent at sufficiently high temperature, leading to excessive power dissipation in the off-state. This effect can be some- what alleviated by the use of dielectric isolation technol- ogy to eliminate the large-area drift-region-to-substrate junction, which is a major source of the leakage current. The DMOS channel mobility was shown to exhibit a T-2.5 temperature dependence, which is comparable to that of normal bulk mobility which is dominated by acoustic, in- tervalley, and optical phonon scattering. This variation is much more severe than the T - ‘ . 5 dependence commonly observed in conventional CMOS. The threshold voltage was shown to decrease monotonically with temperature, while for high gate voltages typical of switching in the on-state the resistance monotonically increased with tem- perature. Conditions for zero-temperature-coefficient biasing, in which the drain saturation current is insensi- tive to temperature variations were derived and demon- strated experimentally

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Gary M. Dolny (S’81-M’81-SM’91) was born in Nanticoke, PA. He received the B.S. degree in physics from Haverford College in 1977 and the M.S. and Ph.D. degrees in electrical engineering from the University of Pittsburgh in 1978 and 1981, respectively.

From 1981 to 1985 he was a member of the fac- ulty o f the Department of Electrical and Materials Engineering at Wilkes College. Wilkes-Bane, PA, where he taught courses on solid-state physics. semiconductor device fabrication. and integrated

circuit design. During this time he also worked with the RCA Solid State Division at Mountaintop, PA, where he developed computer-aided tech- niques for the analysis and design of high-voltage transistor structures and participated in various process development and yield enhancement proj- ects. In 1985 he joined RCA Laboratories David Sarnoff Research Center (since 1987 a subsidiary of SRI International) as a Member of the Technical Staff in the Advanced Silicon Technology Group. His responsibilities there have included BiCMOS process development for both signal processing and power IC applications, silicon-on-insulator technology, investigations of the device physics and process technology of polysilicon thin-film tran- sistors, computer modeling and semiconductor device simulation, high- temperature electronics, and integrated circuit failure analysis and yield improvement. This work has resulted in approximately 30 published papers and 2 US patents.

Dr. Dolny has served as Vice-chairman of the IEEE Princeton Section of the Electron Device Society, and was the Publication Chairman of the 1990 and 1991 International Electron Devices Meeting.

Gerald E. Nostrand (M‘81) received the B.S. degree in physics from Wagner College in 1970. From 1970 to 1972 he performed graduate work in Physics at the Florida Institute of Technology.

In 1972 he joined RCA Laboratories David Sarnoff Research Center, Princeton, NJ, initially working in the area of integrated optics. From 1972 through 1985 he held a variety of research assignments in the areas of liquid-crystal dis- plays, thin-film photovoltaics, and automotive electronics. Since 1985 he has been responsible

for the development of automated testing procedures for a variety of semi- conductor technologies. He is author or co-author o f several publications and has been awarded 2 U.S. patents.

Kevin E. Hill (M’90) received the B S degree in electrical engineering from the University of Buf- talo in 1984 and the M S degree in electrical en- gineering from Syracuse University in 1987

He joined the General Electric Aerospace Con- trol Systems Department. Binghamton, NY. in 1984 At GE, he is concerned with circuitisystem design of ddvanced full-authority digital-engine controls This work includes developments in

cynchronouq Eampling vibration tracking architec- tures, PWB designs. thick-film hybrid design. and

high-voltage IC design He I \ presently project engineer for the develop- ment and application ot the power BiCMOS IC technology and high-tem- perature IC’s

Mr Hill IS a graduate of the General Electric Advdnced Course in En- gineering and a member of Tau Betd Pi

’