InGaAs/InP DHBTs in a planarized, etch-back technology for base contacts
Technology Development & Design for 22 nm InGaAs/InP-channel MOSFETs
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Transcript of Technology Development & Design for 22 nm InGaAs/InP-channel MOSFETs
Technology Development & Design for 22 nm InGaAs/InP-channel MOSFETs
[email protected] 805-893-3244, 805-893-5705 fax
2008 Indium Phosphide and Related Materials Conference, May, Versailles, France
M. RodwellUniversity of California, Santa Barbara
C. Palmstrøm, E. Arkun, P. SimmondsUniversity of Minnesota
P. McIntyre, J. Harris, Stanford University
M. V. Fischetti, C. Sachs University of Massachusetts Amherst
M. Wistey, U. Singisetti, G. Burek, A. Gossard, S. Stemmer, R. Engel-Herbert, Y. Hwang, Y. Zheng, C. Van de WalleUniversity of California Santa Barbara
P. Asbeck, Y. Taur, A. Kummel, B. Yu, D. Wang, Y. Yuan,University of California San Diego
Specific Acknowledgements ( Device Team )
Greg Burek
Uttam Singisetti Dr. Mark Wistey
Lead: Device DevelopmentMBE Regrowth
Dr. Erdem Arkun
Prof. Chris PalmstrømCBE Regrowth
Why III-V CMOS ?
Why Develop III-V MOSFETs ? Silicon MOSFETs continue to scale...
...22 nm is feasible in production ( or so the Silicon industry tells us...)
...16 nm ? -- it is not yet clear
If we can't make MOSFETs yet smaller,instead move the electrons faster:
III-V materials→ lower m*→ higher velocitiesId / Wg = qnsv Id / Qtransit = v / Lg
Serious challenges:High-K dielectrics on InGaAs channels, InGaAs growth on SiTrue MOSFET fabrication processes
Designing small FETs which use big (low m*) electrons
Simple FET ScalingGoal: double transistor bandwidth when used in any circuit
→ reduce 2:1 all capacitances and all transport delays→ keep constant all resistances, voltages, currents
All lengths, widths, thicknesses reduced 2:1
S/D contact resistivity reduced 4:1
oxgm TvWg /~/
oxgggs TLWC /~/
~/, gfgs WC
subcgsb TLWC /~/
If Tox cannot scale with gate length,
Cparasitic / Cgs increases,
gm / Wg does not increase
hence Cparasitic /gm does not scale
~/ ggd WC
All lengths, widths, thicknesses reduced 2:1
S/D contact resistivity reduced 4:1
FET scaling: Output Conductance & DIBL )states of densityfinite a of effectthe neglects expression ( gsC
gchd WC ~
dschdgsgsd VCVCQQI where/
/~ oxgggs TLWC
transconductance
→ Keep Lg / Tox constant as we scale Lg
output conductance
Well-Known: Si FETs No Longer Scale Perfectly
Effective oxide thickness is no longer scaling in proportion to Lg
(ITRS roadmap copied from Larry Larson's files)
delay gate dominate ll...soon wislowly only improving is /
degrading is econductancOutput
rapidly increasingnot isdensity ecapacitanc Gate
) area / ecapacitanc ( acheivable limits interlayer SiO :sdielectric gateK -High
parasitic
2
dIC
Highly Scaled MOSFETs: What Are Our Goals ?
Low off-state current (10 nA/m) for low static dissipation→ minimum subthreshold slope→ minimum Lg / Tox
low gate tunneling, low band-band tunneling
Low delay CFET V/I d in gates where transistor capacitances dominate. Parasitic capacitances are 0.5-1.0 fF/m
→ while low Cgs is good, high Id is much better
Low delay Cwire V/Id in gates where wiring capacitances dominate. large FET footprint → long wires between gates→ need high Id / Wg ; target ~6 mA/m
short transit time alone (low Cgs, int Vgs/Id ) is not sufficient
III-V MOSFETs:Drive Current and
CV/I delay
III-V CMOS: The Benefit Is Low Mass, Not High Mobility
Id
VgsVth
: thresholdabovefar ate,nondegener theory,diffusion -drift Simple
low effective mass → high currents
/ginjectionLvV
)/(~ where 1/2*mkTvv thermalinjection )( VVVvWcI thgsinjectiongoxD
mobilities above ~ 1000 cm2/V-s of little benefit at 22 nm Lg
mV 700
that Ensure
~
)( thgs VVV
Low Effective Mass Impairs Vertical Scaling
Shallow electron distribution needed for high gm / Gds ratio, low drain-induced barrier lowering.
.2*2 /~ wellTmL
Only one vertical state in well. Mimimum ~ 5 nm well thickness.→ Hard to scale below 22 nm Lg.
For thin wells, only 1st state can be populated.For very thin wells, 1st state approaches L-valley.
Energy of Lth well state
Density-Of-States Capacitance
Two implications:
- With Ns >1013/cm2, electrons populate satellite valleys - Transconductance dominated by finite state density
and n is the # of band minima
)//( * 22 nmnEE swellf
2*2 2/ nmqcdos where
dosswellf cVV /
Fischetti et al, IEDM2007
Solomon & Laux , IEDM2001
Drive Current in the Ballistic & Degenerate Limits
More careful analyses by Taur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007
Drive Current in the Ballistic & Degenerate Limits
2/3*
,
2/1*2/3
)/()/(1 where,
V 1m
mA84
ooxodos
othgs
mmncc
mmnK
VVKJ
0
0.05
0.1
0.15
0.2
0.25
0.3
0.01 0.1 1
K
m*/mo
1 nm
0.6 nm
EOT=0.2 nm
0.4 nm
n=1
Inclusive of non-parabolic band effects, which increase cdos , InGaAs & InP have near-optimum mass for 0.4-1.0 nm EOT gate dielectrics
eot includes the electron wavefunction depth
Rough Projections From Simple Ballistic Theory
Channel EOT drive current intrinsic(700 mV overdrive) gate capacitance
InGaAs 1 nm 6 mA/m 0.2 fF/mInGaAs 1/2 nm 8.5 mA/m 0.25 fF/m
Si 1 nm 2.5-3.5 mA/m 0.7 fF/mSi 1/2 nm 5-7 mA/m 1.4 fF/m
22 nm gate length
InGaAs has much less gate capacitance 1 nm EOT → InGaAs gives much more drive current 1/2 nm EOT → InGaAs & Si have similar drive currentInGaAs channel→ no benefit for sub-22-nm gate lengths
0.5-1.0 fF/m parasitic capacitances
Device Structure&
Process Flow
Device Fabrication: Goals & Challenges
III-V HEMTs are built like this→ Source Drain
Gate
....and most III-V MOSFETs are built like this→
K Shinohara
Device Fabrication: Goals & Challenges
r
InGaAs well
barrier
InP well
r
TiWN+ drainregrowth
N+ sourceregrowth
Yet, we are developing,at great effort,a structure like this →
Why ?
Source DrainGate
K Shinohara
Why not just build HEMTs ? Gate Barrier is Low !
Tunneling through barrier→ sets minimum thickness
Source DrainGate
Ec
Ewell-
EF
Ec
Ewell-
EF
Gate barrier is low: ~0.6 eV
Emission over barrier→ limits 2D carrier density
K Shinohara
eV 6.0~)( ,cm/10At 213cfs EEN
Ec
Ewell-
EF
N+ caplayer
Why not just build HEMTs ?
low leakage: need high barrier under gate
Source DrainGate
Ec
Ewell-
EF
Gate barrier also lies under source / drain contacts
low resistance: need low barrier under contacts
widegap barrier layer
N+ layer
K Shinohara
substrate
barrier
sidewall
metal gate
quantum well / channel
gate dielectric
N+ source N+ drain
source contact drain contact
The Structure We Need
no gate barrier under S/D contacts
high-K gatebarrier
Overlap between gateand N+ source/drain
-- is Much Like a Si MOSFET
How do we make this device ?
substrate
barrier
metal gate
InGaAs quantum well
drain contact
implantation
source contact
implantation
Source/Drain Implantation Does Not Look Easy
Annealing can't fix this.Implantation will intermix InGaAs well & InAlAs barrier
Implanted structures have not shown the necessary low contact resistivity.
Incommensurate sublimation of III vs. V elements during anneal
Need ~ 5 nm implant depth & ~ 6*1019 /cm3 doping
So, We Are Forming the Source/Drain By Regrowth
Process selected to meet 22 nm ITRS targets
substrate
barrier
sidewallmetal gate
InGaAs quantum well
gate dielectric
N+ source N+ drain
source contact drain contact
substrate
barrier
metal gate
InGaAs quantum well
substrate
barrier
metal gate
InGaAs quantum well
substrate
barrier
sidewallmetal gate
InGaAs quantum wellN+ source N+ drain
But...
unlike HEMT process flows,fully established in 1980's...
...most process steps hereare completely new
The technology is aggressive and challenging
substrate
barrier
sidewall
metal gate
quantum well / channel
gate dielectric
N+ source N+ drain
source contact drain contact
The Required Performance is Formidable~5 nm thick well 1 nm Insulator EOT
Target ~7 mA/m @ 700 mV gate overdrive
m 10
mV. 70
current, driveon impact 10% For
s
SD
R
RI m 2)square/ 100( extension) N nm 02(
m 10)contact widenm 25/( )m 25.0( 2
Process Development
Process Flow with MBE Source/Drain Regrowth
Process Flow with MBE Source/Drain Regrowth
Gate Dielectrics
ALD Al2O3 from IBM (D. Sedana) & Stanford (P. McIntyre)
ALD ZrO2 from Intel (S. Koveshnikov et al, DRC 2008)
Al2O3 is more robust in processing.
→ initial process development
Process modules being developed for ZrO2 .
Gate Definition: Challenges
Must scale to 22 nm
Dielectric cap on gate for source/drain regrowth
Metal & Dielectric etch must stop in 5 nm channel
Semiconductor etch must not etch through 5 nm InP subchannel
Process must leave surfaces ready for S/D regrowth
barrier
InGaAs well
r
(starting material) recess etchnonselective regrowthin-situ S/D metal
planarize etch strip planarizationmaterial
InP well
r
r
r
r
well well well well
barrier
InP well
barrier
InP well
barrier
InP well
barrier
InP well
r
r
r
r
r
non-selective-area S/D regrowth
r
well
barrier
InP well
r
electroplateS/D metal
barrier
r
(starting material)
barrier
well
r
r
r
barrier
well
r
r
CBE in-situ etch CBEselective-arearegrowth
InGaAs well
InP well InP well InP well
selective-area S/D regrowth
barrier
well
r
r
in-situ S/Dmetaldeposition
InP well
barrier
well
r
r
planarize& etch
InP well
electroplateS/D metal
barrier
well
r
r
InP well
Gate Stack: Multiple Layers & Selective Etches
Key: stop etch before reaching dielectric, then gentle low-power etch to stop on dielectric
(starting material)
barrier
well
r
barrier
well
r
barrier
well
r
r
r
r
PECVD Si3N4 ICP RIE etchCF4 / O2PECVD SiN sidewall deposition,
low power anisotropic RIE etch
...sidewall etch must not damage the channel
Sidewall Formation
Clean, Undamaged Surface Before Regrowth
undamaged InP subchannel
(after Al2O3 dielectric etch & InGaAs recess etch )
Two Source/Drain Regrowth Processes
barrier
InGaAs well
r
(starting material) recess etchnonselective regrowthin-situ S/D metal
planarize etch strip planarizationmaterial
InP well
r
r
r
r
well well well well
barrier
InP well
barrier
InP well
barrier
InP well
barrier
InP well
r
r
r
r
r
non-selective-area S/D regrowth
r
well
barrier
InP well
r
electroplateS/D metal
barrier
r
(starting material)
barrier
well
r
r
r
barrier
well
r
r
CBE in-situ etch CBEselective-arearegrowth
InGaAs well
InP well InP well InP well
selective-area S/D regrowth
barrier
well
r
r
in-situ S/Dmetaldeposition
InP well
barrier
well
r
r
planarize& etch
InP well
electroplateS/D metal
barrier
well
r
r
InP well
barrier
InGaAs well
r
(starting material) recess etchnonselective regrowthin-situ S/D metal
planarize etch strip planarizationmaterial
InP well
r
r
r
r
well well well well
barrier
InP well
barrier
InP well
barrier
InP well
barrier
InP well
r
r
r
r
r
non-selective-area S/D regrowth
r
well
barrier
InP well
r
electroplateS/D metal
barrier
r
(starting material)
barrier
well
r
r
r
barrier
well
r
r
CBE in-situ etch CBEselective-arearegrowth
InGaAs well
InP well InP well InP well
selective-area S/D regrowth
barrier
well
r
r
in-situ S/Dmetaldeposition
InP well
barrier
well
r
r
planarize& etch
InP well
electroplateS/D metal
barrier
well
r
r
InP well
selective area S/D regrowth by Chemical Beam Epitaxy: Palmstrøm / Arkun
non-selective area S/D regrowth by Molecular Beam Epitaxy: Wistey
barrier
r
(starting material)
barrier
well
r
r
r
barrier
well
r
r
CBE in-situ etch CBE in-situselective-area regrowth
InGaAs well
InP well InP well InP well
barrier
well
r
r
InP well
electroplateS/D metal
barrier
InGaAs well
r
(starting material) recess etchnonselective regrowthin-situ S/D metal
planarize etch strip planarizationmaterial
InP well
r
r
r
r
well well well well
barrier
InP well
barrier
InP well
barrier
InP well
barrier
InP well
r
r
r
r
r
non-selective-area S/D regrowth
selective-area S/D regrowth
non-selective regrowth
Recess Etch & Regrowth: Inter-Relationships
InGaAs/InP composite channelpermits selective InGaAs wet-etch, stopping on InPregrowth initiated on InP (desirable ?)
If regrowth can extend laterally under sidewall, sidewall can be thicker
barrier
InGaAs well
r
(starting material) recess etchnonselective regrowthin-situ S/D metal
planarize etch strip planarizationmaterial
InP well
r
r
r
r
well well well well
barrier
InP well
barrier
InP well
barrier
InP well
barrier
InP well
r
r
r
r
r
non-selective-area S/D regrowth
r
well
barrier
InP well
r
electroplateS/D metal
barrier
r
(starting material)
barrier
well
r
r
r
barrier
well
r
r
CBE in-situ etch CBEselective-arearegrowth
InGaAs well
InP well InP well InP well
selective-area S/D regrowth
barrier
well
r
r
in-situ S/Dmetaldeposition
InP well
barrier
well
r
r
planarize& etch
InP well
electroplateS/D metal
barrier
well
r
r
InP well
selective CBE regrowth
or
substrate
InP sub-channel
sidewall
metal gate
InGaAs channel
gate dielectric
N+ source N+ drain
source contact drain contact
barrier
Regrowth interface resistance
In addition to the contact & link resistances
resistance at the regrowth interfaces is also of concern...
Contact & Regrowth Interface Resistance
r
well
barrier
InP well
r
barrier
well
r
r
InP well
Nonselective-Wistey
Selective-Arkun
0
2
4
6
8
10
12
14
0 5 10 15 20 25 30
Re
sist
anc
e (
)
Pad Spacing (m)
TLM A
TLM B
N+ RG
Mo contact Mo contact
N+ InGaAs
SI InP
2m- 5.0
2m- 8.0
N+ RG
Mo contact Mo contact
N+ InGaAs
SI InP
TEM of Regrowth: InGaAs on InGaAs (Mark Wistey)
InGaAs n+
HRTEM
Interface
HAADF-STEM`
2 nm
Interface
InGaAs n+ regrowth
Images of MBE Regrowth (dummy sample)
TiW
Oxide
lateral regrowth under gate: good !
growth on sidewall: bad ! to suppress, grow hotter
Regrowth process is still being de-bugged
Planarization / Etch-Back Process
Ashed-back PR covers S/D contacts Mo etched in SF6/Ar dry etch PR strip removes polymers. Mo protects semiconductor from descum plasma.
Images of Completed Device
Results & Status
1st working devices: (ISCS submission)MBE S/D regrowthincomplete S/D growth under gate→ high access resistance→ low drive current (1 A/m !)
Cause of Problems related to regrowth on InP subchannelhas impacted both MBE & CBE regrowth
...and is now resolved
New devices now in fabrication...stay tuned
InGaAs/InP Channel MOSFETs for VLSI
Low-m* materials are beneficial only if EOT cannot scale below ~1/2 nm
Devices cannot scale much below 22 nm Lg→ limits IC density
Little CV/I benefit in gate lengths below 22 nm Lg
Gate dielectrics, III-V growth on Si: also under intensive development
Need device structure with very low access resistance radical re-work of device structure & process flow