STAR HPTDC Prototyping
description
Transcript of STAR HPTDC Prototyping
![Page 1: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/1.jpg)
STAR HPTDC Prototyping
Lloyd Bridges, Geary Eppley, Ted Nussbaum, Jo Schambach
![Page 2: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/2.jpg)
HPTDC Workshop, 13. May 2003
2
RHIC at BNL
![Page 3: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/3.jpg)
HPTDC Workshop, 13. May 2003
3
TOF Tray Design
![Page 4: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/4.jpg)
HPTDC Workshop, 13. May 2003
4
RPCDETECTOR
AMPLIFIERDISCRIMINATOR
TDRC
TRIGGER
BUFFER
TRAY LEVEL DATA PROCESSING
TRAY LEVEL MULTIPLICITY
DATA FORMATTINGDATA TRANSFER
24
24 channels RPC + 1 TFEE + 1 TDIG
FIBER LINK
MULTIPLICITY
COMMANDS
TIMING
DATA + COMMAND FORWARDING
STAR TOF: TOP LEVEL ELECTRONICS
PC
24 channels RPC + 1 TFEE + 1 TDIG
24 channels RPC + 1 TFEE + 1 TDIG
24 channels RPC + 1 TFEE + 1 TDIG
24 channels RPC + 1 TFEE + 1 TDIG
24 channels RPC + 1 TFEE + 1 TDIG
24 channels RPC + 1 TFEE + 1 TDIG
TDC DATA
MULTIPLICITY
CONFIG/STATUS
TFEE
TDIG TCPU
TMIT
DAQ
SERIAL BUS
![Page 5: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/5.jpg)
HPTDC Workshop, 13. May 2003
5
FRONT END ELECTRONICS( 1 OF 24 CHANNELS )
PREAMP
PREAMP
ADC AMPTHS4502
DISCRIM.MAX9601
THRESHOLD(common to allchan., bipolar)
RPCTO TDC AND TRIGGER
FROM THRESHOLD DAC
CAMAC
PREAMP BYPASS
PREAMP:MAX3760 “ORIGINAL”MAX3664 < PWR, COSTMAX3266 HIGHER SPEED
POWER:~ 385 mW / ch@ +4.5V, -8.5V
TEMERATURE SENSOR
![Page 6: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/6.jpg)
HPTDC Workshop, 13. May 2003
6
![Page 7: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/7.jpg)
HPTDC Workshop, 13. May 2003
7
PROTOTYPE TDC ELECTRONICS
INTEGRATOR(4 CHAN)
THRESHOLDDAC
HPTDC 1
HPTDC 2
ADC(4 CHAN)
Multiplicity Input
CAN BUS
TEMPERATURE(TDC, FEE)
MICROPIC18F8720
PLDEP20K200
RS-232
JTAG
8 LVDS CHANNELS FROMFEE DISCRIMINATOR
4 DIFF. ANALOG CHANNELSFROM BUFFER AMP
INTERNAL /EXT OSC
POWER AT 6VREGULATED@ 5.0V, 3.3V,2.5V
MULTIPLICITYDAISY CHAIN
SERIAL BUS
![Page 8: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/8.jpg)
HPTDC Workshop, 13. May 2003
8
![Page 9: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/9.jpg)
HPTDC Workshop, 13. May 2003
9
0
5000
10000
15000
20000
25000
30000
35000
40000
0 500 1000 1500 2000
Bin #
Eve
nt
cou
nt
Code Density Data @ 25ps, 20M points
![Page 10: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/10.jpg)
HPTDC Workshop, 13. May 2003
10
Integral Non-Linearity @ 25 ps
-20
-15
-10
-5
0
5
0 200 400 600 800 1000
Bin #
INL
co
rrec
tio
n (
Bin
s)
![Page 11: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/11.jpg)
HPTDC Workshop, 13. May 2003
11
Time Difference Measurement Test SetupPULSERwithINTERNALTRIGGER
40 MHZCLOCK
HPTDC
DELAY
TDC PROTOTYPE
Output
Output
“Delay”
HP8131A
![Page 12: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/12.jpg)
HPTDC Workshop, 13. May 2003
12
Raw Time Difference
0200400600800
10001200140016001800
480 490 500 510 520
Cable delay, (Bin #)
Eve
nt
cou
nts
![Page 13: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/13.jpg)
HPTDC Workshop, 13. May 2003
13
INL Corrected Time Difference
0
500
1000
1500
2000
2500
3000
480 485 490 495 500 505 510 515 520
Cable delay, INL-corrected (Bin #)
Eve
nt
cou
nts
rms = 32.2 ps
![Page 14: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/14.jpg)
HPTDC Workshop, 13. May 2003
14
RMS of Time Difference Measurements
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
0 10 20 30 40 50 60
Cable delay (ns)
rms p
eak w
idth
(p
s)
Mean RMS = 33.9 ps
Implies Single Channel RMS = 24.0 ps
![Page 15: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/15.jpg)
HPTDC Workshop, 13. May 2003
15
Raw Time Difference with FEE
0
50
100
150
200
250
140 145 150 155 160 165 170 175 180
Cable delay w/ FEE, Relative Delay (Bin #)
![Page 16: STAR HPTDC Prototyping](https://reader036.fdocuments.net/reader036/viewer/2022062809/5681598c550346895dc6d3f8/html5/thumbnails/16.jpg)
HPTDC Workshop, 13. May 2003
16
INL-Corrected Time Difference with FEE
0
100
200
300
400
500
600
700
800
140 145 150 155 160 165 170 175 180
Cable delay w/ FEE, INL-corrected Relative Delay (Bin #)
rms = 40.3ps