Spike anneal optimization for digital and analog high ... · PDF fileSpike anneal optimization...

1E.Josse and al. – ESSDERC’02 – Firenze, Italy

Spike anneal optimizationSpike anneal optimization for digitalfor digitaland analog highand analog high performance 0.13µm performance 0.13µm

CMOSCMOS platformplatform

E.E.JosseJosse, F.Arnaud, F., F.Arnaud, F.WacquantWacquant, D., D.LenobleLenoble, O., O.MenutMenut, E., E.RobilliartRobilliart

STMicroelectronicsSTMicroelectronics, Central R&D, Crolles, France, Central R&D, Crolles, France


Outline

Motivation for spike anneal

Impact on 0.13 µm pMOSFET

Impact on 0.13 µm nMOSFET

CMOS optimization for digital and analog applications

Conclusions


Motivation for spike anneal : thermal ramps profile

350

450

550

650

750

850

950

1050

1150

0 20 40 60 80

Time (sec)

Tem

pera

ture

(°C

)Ramp-up

Ramp-down

Peak

High peak temperature : maximize dopant activation

Aggressive ramp-up : minimize dopant diffusion

Aggressive ramp-down : minimize dopant deactivation


Motivation for spike anneal : simulated 2D MOSFET profiles

Standard RTA : 1025°C 15s Spike RTA at 1113°C

Simulated : 0.13 µm pMOSFET with either a standard RTA (1025°C 15s) or a spike RTA at 1113°C

motivation for spike RTA : reducing Boron diffusion

challenge : optimizing the spike RTA temperature and ramps to obtain both reduced Boron diffusion and high level of Boron and Arsenic activation


Motivation for spike anneal : experimental

Context : 0.13 µm CMOS flow (Lg=0.11 µm and tox=20Å)

nMOS junction : As at 2 keV + double pocket (Indium + Bore)

pMOS junction : BF2 at 4 keV + double pocket (Arsenic + Phosphorus)

Demo done with an industrial Lamp-based RTP (AMAT CENTURA XE+)

Various spike anneal T° and ramps conditions are compared with a standard RTA 1025°C 15s :

XXXX1150°C

XXXX1113°C

XXXX1075°C

100 / 100 75 / 100 100 / 75 75 / 75 Ramp : up / down [°C/s]


Outline





Conclusions


Impact on 0.13 µm pMOSFET : Vt-L plots

-0.7

-0.65

-0.6

-0.55

-0.5

-0.45

-0.4

-0.35

-0.30.1 1 10

Lg [µm]

Vt [V

]

75/75 75/100100/75 100/100

ramp (up and down) slope in °C/s

1113°C

1150°C

RTA 1025°C 15s

1075°C

1st order player is temperature :

Aggressive ramps are not required

Compared to reference RTA :

T=1150°C : SCE not corrected

T=1075°C : SCE inverted = RSCE

T=1113°C : flat Vt-L profile

Major impact of the final RTA temperature on Vt-L plots at pMOS side :

Boron diffusion is driven by the spike temperature


Impact on 0.13 µm pMOSFET : Boron activation

10

100

1000

1000 1025 1050 1075 1100 1125 1150 1175 1200

spike temperature [°C]

sq. r

esis

tanc

e [o

hm/s

q]

P+ S/D extension

P+ deep S/D

P+ poly gate

1025°C 15s

Boron activation

No impact from ramp-up and down

(not presented here)


T=1150°C : higher B activation

T=1075°C : lower B activation

T=1113°C : same B activation

Major impact of final RTA temperature step on Boron activation :

T=1113°C is the best trade-off between Boron diffusion and activation


Impact on 0.13 µm pMOSFET : Boron penetration

0.9

0.91

0.92

0.93

0.94

0.95

0.96

-1.3 -1.25 -1.2 -1.15 -1.1

Vgate [V]

Cga

te/C

max spike 1113°C

spike 1075°C

spike 1150°C

RTA 1025°C 15s

C-V plot : zoom on gate depletion

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.8 0.85 0.9 0.95 1 1.05

Vgate [V]

Cga

te/C

max

increased B penetration

12

34

1. spike 1075°C2. spike 1113°C3. RTA 1025°C 15s4. spike 1150°C

C-V plot : zoom on VFB shift

Spike RTA 1113°C compared to reference RTA 1025°C 15s:

Both gate depletion and Boron penetration reduced : improved gate stack


Outline





Conclusions


Impact on 0.13 µm nMOSFET : Vt-L plots

0.25

0.27

0.29

0.31

0.33

0.35

0.37

0.39

0.1 1 10Lg [µm]

Vt [

V]

75/75 75/100100/75 100/100

ramp (up and down) slope in °C/s

1075°C1113°C

1150°CRTA 1025°C 15s

No significant impact of the final RTA on Vt-L plots at nMOS side :

Arsenic diffusion is not driven by the spike temperature


Impact on 0.13 µm nMOSFET : Arsenic activation

10

100

1000

1000 1025 1050 1075 1100 1125 1150 1175 1200

spike temperature [°C]

sq. r

esis

tanc

e [o

hm/s

q]

N+ S/D extension

N+ deep S/D

N+ poly gate

1025°C 15s

Arsenic activation

No impact from ramp-up and down

(not presented here)


T=1150°C : higher As activation

T=1075°C : lower As activation

T=1113°C : same As activation

Major impact of final RTA temperature step on Arsenic activation :

T=1150°C is the best trade-off between Arsenic diffusion (none) and activation


Impact on 0.13 µm nMOSFET : performance

-9.5

-9

-8.5

-8

-7.5

-7

-6.5

350 400 450 500 550 600 650 700 750Ion [µA/µm]

Ioff

[logA

/µm

]

spike 1075°Cspike 1113°Cspike 1150°CRTA 1025°C 15s

0.9

0.91

0.92

0.93

0.94

0.95

0.5 1 1.5

Vgate [V]

Cga

te/C

max

spike 1113°C

spike 1075°C

spike 1150°C

RTA 1025°C 15s

Major impact of final RTA temperature step on performance :

• T=1150°C : reduced gate depletion and enhanced performance

• T=1113°C : gate depletion and performance are the same than with ref. RTA


Within wafer uniformity : full sheet Rs mapping

RTA 1025°C 15s Spike RTA at 1113°C

-95.0

-65.0

-35.0

-5.0

25.0

55.0

85.0

95.0

75.0

55.0

35.0

15.0

-5.0

-25.

0

-45.

0

-65.

0

-85.

0

110.5111.2111.9112.6

Rs map

111.9-112.6

111.2-111.9

-95.0

-70.0

-45.0

-20.0

5.0

30.0

55.0

80.0

95.0

75.0

55.0

35.0

15.0

-5.0

-25.

0

-45.

0

-65.

0

-85.

0

110.7111.4112.1112.8113.5114.2

Rs map

113.5-114.2

112.8-113.5

112.1-112.8

111.4-112.1

1 color = 1°C variation

Activation uniformity is not significantly degraded when compared to thestandard RTA 1025°C 15s, except on the extreme edge of the wafer


Outline





Conclusions


CMOS optimization : spike RTA selection

nMOS pMOS

=+=+1150°C+===1113°C

++-=-1075°C

diffusionactivationdiffusionactivationTemp. [°C]

compared to reference RTA 1025°C 15s : + better / = same / - worse

1113°C : CMOS optimum for SCE control enhancement

1150°C : CMOS optimum for performance enhancement

Aggressive ramps not needed (1st order is temperature) : 75°C/s is enough


CMOS optimization : device optimization (1/2)

Device optimization : for both digital and analog applications

Reference RTA 1025°C 15s

Digital (short channel)

strong pocket dose neededpoor voltage gain (long channel)

poor matching (short channel)

Analog

Spike RTA at 1113°C

Digital (short channel)

low pocket dose neededimproved voltage gain (long channel)

improved matching (short channel)

Analog


CMOS optimization : device optimization (2/2)

0

20

40

60

80

100

120

140

160

180

200

0.1 1

Lmask [µm]

gain

As 4.2e13 + RTA 1025°C 15sAs 1.9e13 + spike 1113°CAs 2.2e13 + spike 1113°CAs 2.5e13 + spike 1113°CAs 2.8e13 + spike 1113°C

Vds=-0.6V and Vgt=-0.2V

-0.6

-0.55

-0.5

-0.45

-0.4

-0.35

-0.3

-0.25

-0.20.1 1 10

Lg [µm]

Vt [

V]

As 4.2e13 + RTA 1025°C 15sAs 1.9e13 + spike 1113°CAs 2.2e13 + spike 1113°CAs 2.5e13 + spike 1113°CAs 2.8e13 + spike 1113°C

Spike RTA at 1113°C allows As pocket dose lightenning (from 4.2e13 to 1.9e13)

Flat pMOS Vt-L is obtained thanks to Boron diffusion freeze-out

Volatge gain for long channel is significantly improved

No impact on pMOS performance nor on nMOS performance and SCE


Outline





Conclusions


Conclusions

It is demonstrated that using a spike RTA instead of a classical few-seconds RTA improves the trade-off between Boron activation and diffusion

Under our process condition, the prevalent player for this trade-off is the spike temperature. « Slow » ramps (75°C/s) are then enough to take thefull advantage of the spike RTA concept

Based on the spike RTA integration within a 0.13 µm CMOS flow, we demonstrated that the MOSFET architecture can be optimized for bothdigital and analog applications : this is made possible because the Borondiffusion freeze-out is traded for a lighter pocket dose

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