SOI High Aspect Ratio Micromachining

SOI High Aspect Ratio Micromachining

Dr. Joël COLLETSenior Engineer

www.tronics.eu

1. TRONICS Microsystems introduction


Your strategic manufacturer of custom MEMS

Facts & Figures

Activity: Developer and contract manufacturer of custom MEMS components for demanding applications

Creation: Spun-off from CEA-LETI in 1997

Locations: Crolles, France, manufacturing facility

Facilities: 1350m² with 750m² for production, packaging and testIncl. 400m² clean rooms, 6’’ wafers

Funding: 15 M€ in 4 rounds

Revenues: 6.2M€ in 2005, amongst the 200 fastest growing EMEA company

Staff: 46 (26 prod., 12 R&D, 8 sales & admin.)

Expertise: Custom high performance SOI-MEMS manufacturing


Business model

Developer and Contract Manufacturer of high value-add

MEMS-based custom components for demanding applications

Customization/industrialization of existing solutions/platforms

» from the customer

» from third parties

» from our own

Contract manufacturing of custom components

Your Strategic Manufacturer of Custom MEMS components


End-to-end development and manufacturing service

Design for manufacturing, modelling and simulation

Expert services for the industrialization of your custom MEMS product

Process developmentand qualification

Industrialization and Supply chain management

ASIC development support and/or management

Packaging development and optimization

Testing, characterizationreliability and quality control


Market FocusCustom MEMS components for demanding applications

ME

MS

Val

ue-

add

ed

1

10

100/

Telecom networks

Instrumentation

Volume (pieces/year)10 K

Automotive

Life Sciences BioMedical

Through partnerships

Building automation

Aerospace/Défense

IT, mobile and consumer products

100 K 1 M 10 M 100 M


Pioneer of Custom SOI MEMS Manufacturing

Resonating Gyrometers

Geophone, extreme resolution accelerometer

16 bits, High performanceAcceleration sensors

Miniature accelerationtransducer

Unique Generic Industrial SOI Technology Platform

For High Performance Custom MEMS Components

DRIE on Thick SOISacrificial/Cavity release

Wafer Level Packaging

2. From bulk µmachining to SOI-HARM



History of the introduction of MEMS on SOI

R&D Manufacturing

1980s piezoresistive pressure sensor (Kulite)

1990’s first capacitive accelerometer (LETI) 1st piezoresistive pressure sensor (Kulite, Honeywell)

1995-2001 wide use of SOI in sensors designs (acceleration, pressure, force, gyros)

1998 1st capacitive sensors on SOI (Tronics)

1998 integrated inertial sensors design on SOI/CMOS (IMI purchased by ADI)

1998 Micro-pump on SOI (Debiotech SA)

2000 Optical MEMS on SOI (Bookham, IMT, XRoss, FhG IPMS, Tronics)

Nippon Denso automotive accelerometers

2000 Thermal inclinometer for automotive (IMIT/VOGT)

Piezo automotive pressure sensors (First Sensor)

2001 Sercalo 2x2 optical switch

2002 LETI/Freescale R&D on capacitive accelerometers for automotive

Geophones (seismic sensors) for oil exploration (Tronics)

Draper Lab gyro on SOI

2006 Honeywell gyro on SOI (automotive version)Tronics gyro on SOI (industrial and tactical)


Silicon Bulk Micromachining: The 80s

Typical piezo-resistive pressure sensor process

B+ Ion implantation

Thermal annealing & hole openingMetal deposition and patterning

Back side KOH etching

Si/Glass Anodic Bonding

vacuum

Implanted strain gauge

Single crystal Si Batch processing techniques, simple technologies = > Low cost Design limitation => large components, high cost Big masses, beams and membranes = > High Performance possible


Silicon Surface Micromachining: The 90s

Deposition of SiO2 Deposition of Poly-Si

Thickness = Few µ-meters

Photolitho of pattern

Etching of Poly-Si

Selective etching of SiO2 as

“Sacrificial layer”

Typical surface micromachining process

Sandia Lab

High integration and miniaturization = > Low cost Limitation on active layer thickness (<15µm) = > Performance limitation

Perfect candidate for low cost / low perf / high volume applications

Resistance to long term mechanical fatigue ?


SOI surface micromachining and HARM: The 21st century

High integration and miniaturization => Low cost Very thick layer (10µm < x < 150µm) => High performance Single crystal silicon: High reliability Simplified process: higher yield SOI wafers: expensive material

Perfect candidate for high performance/medium volume applications

3. SOI HARM – The technology and its capabilities


An industrial environment for training and innovation

SOI-HARM with hermetic package

HF release

Si = 300µm

Hermetic Sealing

Si = 60µm

Gold contacts

DRIE > 1:20Min. gap: 3µmMin. Feat.: 4µm

BOX=2µm

Opening for light, fluids, gas or vacuum

Low vacuum sealed cavity

Si = 450µm


SOI-HARM capabilities and applications

Electrostatic structure (Univ. of Strathclyde)

Capacitive structure (TRONICS)

Microfluidic structure (CEA-Leti/Biochiplab)

Resonating structure (ESIEE)

Gyrometer (CSRI Elektropribor)

Accelerometer (FhG ISiT)

Pressure sensor (Schlumberger)

Mechanical structure (CNRS LAAS)


SOI Wafer Process flow

BSOI wafer, P type doped, 10-20 mOhm.cm, 60 µm/2µm/450 µm

Deposit metalPattern seal and contact area

HARM etching

Sacrificial etching


Cap Wafer Process flow

Si wafer, P type doped, 10-20 mOhm.cm, 300 µm

Thermal oxidationOxide etching (cavity pattern)

Etch oxide backDeposit and pattern cap contactDeposit metal

pattern seal area


Assembly Process flow

Wafer preparation for sealingApply pressure and temperature

Pattern the VIAEtch thermal oxide

Final device with hermetic and non hermetic contact


Key design rules

L

lg

r

L

l

bf

a

bf

lm

A

B

beam width lb lb > 4µm beam length Lb Rule T finger width lf lf> 5µm gap between fingers g G > 3µm over-range gap r r >3µm etch opening a a=10µm seismic mass lm Rule S active area AxB Rule Q

4. SOI HARM – Key processes involved


SOI HARM

Deep DRIE: High Aspect Ratio Micromachining

Principles

• Use the faculty of some gases mixtures in plasma to perform etching (mainly isotropic) or deposition

• By alternating deposition (C4F8 gases) and etching (SF6 gases) phases (so-called Bosch process) it is possible to perform anisotropic vertical etching with high aspect ratio feature (over 1:20)


SOI HARM

0 1 2 1 2 1 1

mask (resist, oxide) plasma SF6 plasma SF6 plasma C4F8 plasma C4F8 plasma SF6 plasma SF6

Deep Etcher description

Principle description


SEM view of a Silicon patterned with HARM

SOI HARM


SOI HARM

Typical DRIE profile in Bulk Silicon

With Depth Depending on Trench Width

Typical DRIE profile in SOI

With Special process in order to avoid over etching of pattern’s feet


Typical DRIE Trench Profile Typical DRIE Pattern Profile

ETCHING DEFINITION

Form Factor : 20:1

With over-etching and scalloping

SOI HARM


Sacrificial etching

Principles

• Use the faculty of concentrated HF (10 to 50%) to etch oxide over a very long distance in very narrow trenches

• By drying the structure once released with special process using solvents (avoid sticking due to capillarity)

Release by Sacrificial Etching


Patterning (HARM) of beam Partial etching. Etch sacrificial SiO2 Total release

Principle description



IR view of a released beam and a sticked beam


Sticking Effect One of the main issues for MEMS yield in releasing process.

Capillarity forces pull the structures to the substrate.


Wet process.Specific rinsing and drying. Sublimation process (cyclohexane, CO2) lowering the surface tensions lowering of capillarity effects Dry processEtching with HF vapours End of the releasing with resist no capillarity effects• Design optimisation •Ratio between surface and gapAnti sticking bumps increasing the stiffness



Metallic bonding

Metallic bonding

Principles

• Use the faculty of some metals to form « low temperature » alloy (Au +Si, Au +Sn) or their softness (Au, Cu) to be thermocompressible

• By applying pressure and temperature in a vacuum chamber during a certain amount of time, sufficient to ensure the bonding of the two wafers.


Metallic bonding

Bonding equipment


Metallic bonding

Bonding description, schematic

Heat, pressure, time


Metallic bonding

SEM and optical view of a metallic seal

5. SOI-HARM – Design Kit

Dr. Joël COLLET

Senior Engineer


Complete Design Rules Manual

DRM available on request


Standard cells available to ease the design

8mm

7mm

8mm

7mm

Base cell for the external layout Base cell hermetic sealing view

Pads cells (hermetic and open)


Supported by a software kit on CoventorWare

Use process emulation file and

Material properties database

Create 2D and 3D designs

following design rules

Schematic from parametric cells

Device behaviour simulation Extract GDSII/CAT

for submission

Design Kit available on request


CoventorWare Design Kit for Tronics HARMCoventorWare Design Kit for Tronic’s SOI-HARM Process

CoventorWare modules are configured for Tronic’s SOI-HARM process in order to easily design with confidence into an established

process

Schematic-driven design and behavioral modeling / simulation,for Saber (Cadence

coming soon)

Schematic-driven design and behavioral modeling / simulation,for Saber (Cadence

coming soon)

Physical design: extracted or manual 2D layout to 3D solid

model ,GDSIImask export to fab

Physical design: extracted or manual 2D layout to 3D solid

model ,GDSIImask export to fab

Auto meshing, detailed 3D physics

analysis with FEM/BEM solvers,

3D visualization

Auto meshing, detailed 3D physics

analysis with FEM/BEM solvers,

3D visualization

6 DOF macromodel extraction for use in system verification and to complement

ARCHITECT

6 DOF macromodel extraction for use in system verification and to complement

ARCHITECT

ARCHITECT ™ DESIGNER TM ANALYZER TM INTEGRATOR TM

Materials’Properties

Process Parameters

Tronic’ s Manufacturing Process

Fabrication

CoventorWare modules are configured for Tronic’s SOI-HARM process in order to easily design with confidence into an established

process


CoventorWare Design Kit for Tronic’s SOI-HARM Process

Deliverables:

Materials Property database (*.mpd) of Tronic’s characterized materials

Process emulation file (*.proc) for Tronic’s SOI-HARM process

Layout template file (*.cat, *.gds) Library of parametric and non-parametric elements

supporting schematic and physical design Validated design handbook including process

description and design rules Available at Tronic’s at no charge Enabled by DESIGNER TM

Supports complete CoventorWare TM design flow


Design Kit Enables 2D Layout to 3D Solid Model

2D Layout

GDSII output for mask generation

Input from schematic

Import GDSII, CIF, or DXF files

Use process info as template

Process, material data

Extract layout from schematic automatically or draw layout manually

Perform Design Rule Checks Combine 2D Layout with process description

to build a 3D Solid Model and perform FEA Output masks to be used for fabrication

3D Model


Design Kit Supports Schematic Driven Design

• Tronic’s materials and Process data are shared between schematic and physical design part

• Create device schematic from library of MEMS-specific “parametric elements”

• Simulate device behavior within sub-system rapidly and accurately

• Perform Monte-Carlo and Sensitivity analyses to optimize design

Schematic of accelerometer, composed of parametric building blocks representing beams, electrostatic combs and mass – based on Tronic’s

process


CoventorWare Design Kit for the SOI-HARM

Key benefits:

Easy and low risk entry into MEMS design and prototype development

Validated in fab runs Offers inn combination with MPW low cost prototyping Compatible with CoventorWare standard modules - stable and

most widely installed MEMS design tool Design MEMS with confidence into Tronic’s established and

characterized fabrication process Accelerate Time-To-Market

6. SOI-HARM – Masks Levels

Dr. Joël COLLET

Senior Engineer

Masks Levels


SOI Wafer

Lithography level name

GDS layer Number

Layer name (coventor)

Field type

Purpose Operations

SOI Wafer

GND 0 GND NA Define the edge of the die, used only for the designer, no masks generated from

this level

NA

MARKS 1 ALIGN Dark Alignment patterns for subsequent operations

None

METAL1 2 METAL1 Clear Metallization level for the SOI (contact pads, seal))

None

DRIE 4,5 SILICONHOLE

Clear Mask for the HARM process, definition of the sensing element

4 minus 5

Reminder:

Dark Field means that the data you draw are rendered clear (glass) on the mask

Clear Field means that the data you draw are rendered dark (chromium) on the mask


Cap Wafer


GDS layer

Number

Layer name

(coventor)

Field type

Purpose Operations

Cap Wafer

MARKS 1 ALIGN Dark Alignment patterns for subsequent operations

None

CAVITY 6 CAVITY Clear Define the cavity area above the sensing element

None

METAL2 7 METAL2 Clear Metalization for the Cap wafer (seal) None

METALCAP 9 METCAP Clear Metalization to have an electrical access to the cap wafer itself

None


Final device (assembly)


GDS layer

Number

Layer name

(coventor)

Field type

Purpose Operations

Assembly

VIA1 10 VIA1 Dark Opening in the cap wafer None

VIA2 11 VIA2 Dark Enlargement of the VIA1 pattern (mandatory)

None

7. SOI-HARM – Design Rules

Dr. Joël COLLET

Senior Engineer


Nomenclature

Design rules defines the minimum feature sizes and spaces for all the levels you are allowed to work on and minimum overlap and spacing between relevant levels

- Minimum line widths and spaces are mandatory rules. They are given to ensure that all layouts will remain compatible with TRONIC’S Microsystems lithographic process tolerance.

a

Minimum width


Nomenclature

b

L ayer L 1

L ayer L 2

Minimum space

c

Minimum Notch (the minimum spacing

between two patterns of a same boundary )

- Minimum spacing between levels guarantees that features of two different levels can be delineated by photolithography and etch.


Nomenclature

Minimum enclosure (When a boundary B1

in layer L1 surround a boundary B2 in layer L2, a minimum distance between the edge of the boundary B1 and the edge of the boundary B2 can be defined )

Minimum cut-inside (This dimension

defines the minimum amount that a layer 1 feature can overlap a layer 2 feature)

Minimum cut-outside (This dimension

defines the minimum amount that a layer 1 feature can extend beyond a layer 2 feature.)

d L ayer L 1

L ayer L 2

e

L ayer L 1

L ayer L 2

L ayer L 1

L ayer L 2

f

- Minimum overlap requirements are related to the precision of the alignment between different levels and reduce the effect of large topographies.


Design rules in the level

Lithography Level Name Rule letter Nominal width (µm)Nominal space

(µm)Minimum width

(µm)Minimum space

(µm)

METAL1 A 230 30 90 20

METAL2 B 230 30 90 20

SILICON C 6 5 4 3

HOLE SI D 10 25 10 20

VIA1 E 210 310 150 100

VIA2 F 550 110 350 -100*

CAVITY G 250 30 110 20

* negative value means that you can have overlap between two feature


Generic design rules

Rule Rule LetterNominal

valueMinimum

value

SILICON enclose HOLESI H 10 5

SILICON enclose CAVITY I 20 15*

CAVITY enclose METAL2 J 20 5

METAL1 enclose CAVITY K 20 5

METAL1 enclose METAL2 L 20 0

METAL1 enclose VIA1 M 35 15

CAVITY space to METAL1 N 20 15

SILICON enclose METAL1O 20 10

VIA2 enclose VIA1 P 125 100

* This rule is mandatory to ensure to have a seal area all around the die. In other cases the

cavity could be wider than the silicon


Design rules illustration

Rule H: and ≥ 5 µm

qa cb

HoleSi

Silicon



Rule I: hermetic pad cell example

Silicon

Cavity

15 µm



Rule J,K,L,M,N,O,P: hermetic pad cell example

Silicon

Cavity

METAL2

METAL1

VIA1

VIA2


Design tips : Basic rules

- Always use base cell (give a frame to your design construction).

- Use as often as possible the pads cells given in the DK.

- Think to your interconnect and pads placement before designing the active part level (it help you to determine the remaining area available for your structures).

- Follow, as often as possible, the nominal values of the DRM, instead of the minimum values.


Design tips : Anti sticking design


Design tips : Reduce capacitance

Anchorage

Fixed Comb part

~17.5 µm

Oxide area after release30 µm

HoleSi

8. SOI-HARM – MPW

Dr. Joël COLLET

Senior Engineer


Prinicple of MPW

Sharing cost of wafers between customer


Products benefits

Large dies size: 8x7mm² with 7.5x6.5mm² of active area Possibility to build e.g. the highest performance gyros

Hermetic Wafer Level Packaging Industry state of the art standard for manufacturing Protection and ease of handling/integration

Up to 24 electrical/optical/fluidic holes connections From simple to most complex functions Hermetically sealed or open access

20 dies delivered structures released


SOI-HARM MPW pricing and schedule

RunDesign submission (GDSII/CAT format)

Delivery (20 chips)

N Jan. 1 April 31

N+1 May 1 Aug. 31

N+2 Sept. 1 Dec. 31

Price/location/run Corporate Academic

For 1 location 7,500 € 4,500 €

For 2-3 locations 6,500 € 3,500 €

For 4-5 locations 5,500 € 3,000 €

SOI High Aspect Ratio Micromachining

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