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Transcript of Slide 4-1 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective,...

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Slide 4-1 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 4 Computer Organization Slide 2 Slide 4-2 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 CSCI 3753 Announcements Moodle - posted last Tuesdays lecture Programming shell assignment 0 due Thursday at 11:55 pm, not 11 am Homework #1 due next Thursday at 11 am Read Chapters 3 and 4 in the textbook, skip 4.7 and 4.8 Slide 3 Slide 4-3 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Stored Program Computers and Electronic Devices Patter n Fixed Electronic Device Variable Program Stored Program Device Jacquard Loom Slide 4 Slide 4-4 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Program Specification int a, b, c, d;... a = b + c; d = a - 100; Source ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d Assembly Language Slide 5 Slide 4-5 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Machine Language ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d Assembly Language 101110010011001 101110010100000 101001110011000 101110100011001 101110010100000 101001100011000 101110011011001 Machine Language Slide 6 Slide 4-6 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The von Neumann Architecture Control Unit (CU) Central Processing Unit (CPU) Device Address Bus Data Bus Arithmetical Logical Unit (ALU) Primary Memory Unit (Executable Memory) Slide 7 Slide 4-7 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The ALU R1 R2 Rn... Status Registers Functional Unit Left Operand Right Operand Result To/from Primary Memory load R3,b load R4,c add R3,R4 store R3,a Slide 8 Slide 4-8 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Control Unit 3046 3050 3054 3058 Primary Memory Fetch Unit Decode Unit Execute Unit PC IR Control Unit load R3,b load R4,c add R3,R4 store R3,a 101110010011001 101110010100000 101001110011000 101110100011001 load R4, c 3050 Slide 9 Slide 4-9 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Control Unit Operation PC = ; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; // fetch phase }; Fetch phase: Instruction retrieved from memory Execute phase: ALU op, memory data reference, I/O, etc. Slide 10 Slide 4-10 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Primary Memory Unit MAR MDR Command 0 1 2 n-1 123498765 Read Op: 1234 1. Load MAR with address read 2. Load Command with read 98765 3. Data will then appear in the MDR Slide 11 Slide 4-11 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Processor Modes Mode bit: Supervisor or User mode Supervisor mode Can execute all machine instructions Can reference all memory locations User mode Can only execute a subset of instructions Can only reference a subset of memory locations Slide 12 Slide 4-12 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Kernels The part of the OS critical to correct operation (trusted software) Executes in supervisor mode The trap instruction is used to switch from user to supervisor mode, entering the OS Slide 13 Slide 4-13 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Supervisor and User Memory User Space User Space Supervisor Space Supervisor Space User Process User Process Supervisor Process Supervisor Process Slide 14 Slide 4-14 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Procedure Call and Message Passing Operating Systems call(); trap return; send(, A, ); receive(, B, ); receive(A, ); send(, B, ); send/receive Slide 15 Slide 4-15 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 System Call Using the trap Instruction fork(); fork() { trapN_SYS_FORK() } sys_fork() sys_fork() { /* system function */ return; } Kernel Trap Table Slide 16 Slide 4-16 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 A Thread Performing a System Call User SpaceKernel Space fork(); sys_fork() { } Thread Slide 17 Slide 4-17 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Examples of Exceptions in Pentium Systems ClassCauseAsync/ Sync Return behavior TrapIntentional exception Syncalways returns to next instruction FaultPotentially recoverable error Syncmight return to current instruction Abortnonrecover- able error Syncnever returns Interruptsignal from I/O device Asyncalways returns to next instruction Slide 18 Slide 4-18 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Examples of Exceptions Kinds of Exceptions traps, e.g. system calls interrupts faults aborts Pentium: Table of 256 different exception types some assigned by CPU designers (divide by zero, memory access violations, page faults) some assigned by OS, e.g. system calls Pentium CPU contains exception table base register that points to this table Slide 19 Slide 4-19 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Examples of Exceptions in Pentium Systems Exception Number DescriptionException Class 0Divide errorfault 13General protection fault fault 14Page faultfault 18machine checkabort 32-127OS-definedInterrupt or trap 128System callTrap 129-255OS-definedInterrupt or trap Exception Table OS assigns Slide 20 Slide 4-20 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The Device-Controller-Software Relationship Application Program Device Controller Device Software in the CPU Abstract I/O Machine Device manager Program to manage device controller Supervisor mode software Slide 21 Slide 4-21 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Device Controller Interface Command Status Data 0 Data 1 Data n-1 Logic busydoneError code... busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined) Slide 22 Slide 4-22 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Performing a Write Operation while(deviceNo.busy || deviceNo.done) ; deviceNo.data[0] = deviceNo.command = WRITE; while(deviceNo.busy) ; deviceNo.done = TRUE; Devices much slower than CPU CPU waits while device operates Would like to multiplex CPU to a different process while I/O is in process Slide 23 Slide 4-23 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 CPU-I/O Overlap CPU Device Ready Processes CPU Device Ready Processes I/O Operation CPU Device Ready Processes Uses CPU Slide 24 Slide 4-24 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Polling I/O - Busy Waiting // Start the device While((busy == 1) || (done == 1)) wait(); // Device I/O complete done = 0; while((busy == 0) && (done == 1)) wait(); // Do the I/O operation busy = 1; busydone Software Hardware Slide 25 Slide 4-25 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Determining When I/O is Complete CPU Device Interrupt Pending CPU incorporates an interrupt pending flag When device.busy FALSE, interrupt pending flag is set Hardware tells OS that the interrupt occurred Interrupt handler part of the OS makes process ready to run Slide 26 Slide 4-26 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Control Unit with Interrupt (Hardware) PC = ; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest) { memory[0] = PC; PC = memory[1] }; memory[1] contains the address of the interrupt handler Slide 27 Slide 4-27 Copyright 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Interrupt Handler (Software) interruptHandler() { saveProcessorState(); for(i=0; i