3

2

4

51OE VCC

Y

A

GND

SN74AHC1G126-EP

www.ti.com SCLS731 –DECEMBER 2013

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTCheck for Samples: SN74AHC1G126-EP

1FEATURES• Operating Range of 2 V to 5.5 V• Max tpd of 6 ns at 5 V DCK PACKAGE

(TOP VIEW)• Low Power Consumption, 10-μA Max ICC

• ±8-mA Output Drive at 5 V• Latch-Up Performance Exceeds 250 mA Per

JESD 17

SUPPORTS DEFENSE, AEROSPACE,AND MEDICAL APPLICATIONS• Controlled Baseline• One Assembly and Test Site• One Fabrication Site• Available in Military (–55°C to 125°C)

Temperature Range• Extended Product Life Cycle• Extended Product-Change Notification• Product Traceability

DESCRIPTIONThe SN74AHC1G126 is a single bus buffer gate and line driver with 3-state output. The output is disabled whenthe output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through apulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

ORDERING INFORMATION (1)

TJ PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER

–55°C to 125°C SOT (SC-70) – DCK Reel of 250 74AHC1G126MDCKTEP SLI V62/14605-01XE

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Table 1. FUNCTION TABLEINPUTS OUTPUT

OE A YH H HH L LL X Z

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

A Y

OE1

2 4

SN74AHC1G126-EP

SCLS731 –DECEMBER 2013 www.ti.com

LOGIC DIAGRAM (POSITIVE LOGIC)

ABSOLUTE MAXIMUM RATINGS (1)

over operating junction temperature range (unless otherwise noted)VCC Supply voltage range −0.5 V to 7 VVI Input voltage range (2) −0.5 V to 7 VVO Output voltage range (2) −0.5 V to VCC + 0.5 VIIK Input clamp current VI < 0 -20 mAIOK Output clamp current VO < 0 or VO > VCC ±20 mAIO Continuous output current VO = 0 to VCC ±25 mA

Continuous current through VCC or GND ±50 mATJ Junction temperature range −55°C to 150°CTstg Storage temperature range −65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

THERMAL INFORMATIONSN74AHC1G126-EP

THERMAL METRIC (1) DCK UNITS5 PINS

θJA Junction-to-ambient thermal resistance (2) 282.8θJCtop Junction-to-case (top) thermal resistance (3) 91.1θJB Junction-to-board thermal resistance (4) 60.1

°C/WψJT Junction-to-top characterization parameter (5) 1.6ψJB Junction-to-board characterization parameter (6) 59.2θJCbot Junction-to-case (bottom) thermal resistance (7) N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.Spacer

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SN74AHC1G126-EP

www.ti.com SCLS731 –DECEMBER 2013

RECOMMENDED OPERATING CONDITIONS (1)

MIN MAX UNITVCC Supply voltage 2 5.5 V

VCC = 2 V 1.5VIH High-level input voltage VCC = 3 V 2.1 V

VCC = 5.5 V 3.85VCC = 2 V 0.5

VIL Low-level input voltage VCC = 3 V 0.9 VVCC = 5.5 V 1.65

VI Input voltage 0 5.5 VVO Output voltage 0 VCC V

VCC = 2 V -50 µAIOH High-level output current VCC = 3.3 V ±0.3 V -4

mAVCC = 5 V ±0.5 V -8VCC = 2 V -50 µA

IOL Low-level output current VCC = 3.3 V ±0.3 V 4mA

VCC = 5 V ±0.5 V 8VCC = 3.3 V ±0.3 V 100

Δt/Δv Input transition rise/fall time ns/VVCC = 5 V ±0.5 V 20

TJ Operating junction temperature range –55 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

ELECTRICAL CHARACTERISTICSover recommended operating junction temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT2 V 1.9

IOH = −50 μA 3 V 2.9VOH 4.5 V 4.4 V

IOH = −4 mA 3 V 2.48IOH = −8 mA 4.5 3.8

2 V 0.1IOH = 50 μA 3 V 0.1

VOL 4.5 V 0.1 VIOH = 4 mA 3 V 0.44IOH = 8 mA 4.5 0.44

II VI = 5.5 V or GND 0 V to 5.5 V ±1 µAIOZ VO = VCC or GND 5.5 V ±2.5 µAICC VI = VCC or GND, IO = 0 5.5 V 10 µACi VI = VCC or GND 5 V 10 pF

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SN74AHC1G126-EP

SCLS731 –DECEMBER 2013 www.ti.com

SWITCHING CHARACTERISTICSover recommended operating junction temperature range, VCC = 3.3 V ±0.3 V (unless otherwise noted)

FROM TOPARAMETER LOAD CAPACITANCE MIN MAX UNIT(INPUT) (OUTPUT)tPLH 1 13 ns

A Y CL = 50 pFtPHL 1 13 nstPZH 1 13 ns

OE Y CL = 50 pFtPZL 1 13 nstPHZ 1 15 ns

OE Y CL = 50 pFtPLZ 1 15 ns

SWITCHING CHARACTERISTICSover recommended operating junction temperature range, VCC = 5 V ±0.5 V (unless otherwise noted)

FROM TOPARAMETER LOAD CAPACITANCE MIN MAX UNIT(INPUT) (OUTPUT)tPLH 1 8.5 ns

A Y CL = 50 pFtPHL 1 8.5 nstPZH 1 8 ns

OE Y CL = 50 pFtPZL 1 8 nstPHZ 1 10 ns

OE Y CL = 50 pFtPLZ 1 10 ns

OPERATING CHARACTERISTICSVCC = 5 V, TJ = 25°C

PARAMETER TEST CONDITIONS TYP UNITCpd Power dissipation capacitance No load, f = 1 MHz 14 pF

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50% VCC

VCC

VCC

0 V

0 V

thtsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VCC

0 V

50% VCC50% VCC

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

50% VCC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

Waveform 1

S1 at VCC(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈VCC

0 V

50% VCC VOL + 0.3 V

50% VCC≈0 V

VCC

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

tPLH/tPHLtPLZ/tPZLtPHZ/tPZHOpen Drain

Open

VCCGND

VCC

TEST S1

VCC

0 V

50% VCC

tw

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.

D. The outputs are measured one at a time, with one input transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

From Output

Under Test

CL(see Note A)

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

S1

VCC

RL = 1 kΩ

GNDFrom Output

Under Test

CL(see Note A)

Test

Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

50% VCC

50% VCC 50% VCC

50% VCC

50% VCC 50% VCC

50% VCC 50% VCC

VOH − 0.3 V

SN74AHC1G126-EP

www.ti.com SCLS731 –DECEMBER 2013

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit and Voltage Waveforms

Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: SN74AHC1G126-EP

PACKAGE OPTION ADDENDUM

www.ti.com 17-May-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

74AHC1G126MDCKTEP ACTIVE SC70 DCK 5 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -55 to 125 SLI

V62/14605-01XE ACTIVE SC70 DCK 5 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -55 to 125 SLI

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 17-May-2014

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AHC1G126-EP :

• Catalog: SN74AHC1G126

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

74AHC1G126MDCKTEP SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Mar-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

74AHC1G126MDCKTEP SC70 DCK 5 250 340.0 340.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Mar-2017

Pack Materials-Page 2

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