Digital Electronics Electronics Technology

Landon JohnsonShift Registers

Shift Register Competencies39. Without references, the student will define the term Serial Data Transmission with 100% accuracy.40. Without references, the student will define the term Parallel Data Transmission with 100% accuracy.41. Without references, the student will define the acronym SISO with 100% accuracy.42. Without references, the student will define the acronym SIPO with 100% accuracy.

Shift Register Competencies43. Without references, the student will define the acronym PISO with 100% accuracy.45. Given a specified register, the student will draw the register with 100% accuracy44. Without references, the student will define the acronym PIPO with 100% accuracy.46. Given a specified SISO or SIPO register, the student will state the number of pulses to completely load the register with 100% accuracy.

PARALLEL SHIFT REGISTERLab 18.

SHIFT REGISTER VOCABULARYREGISTER- group of flip flops capable of storing data.SERIAL DATA TRANSMISSION- transfer of data from one place to another one bit at a time.PARALLEL DATA TRANSMISSION- simultaneous transfer of all bits of a data word from one place to another.SISO- SERIAL IN/SERIAL OUT- type of register that can be loaded with data serially and has only one serial output.SIPO- SERIAL IN/PARALLEL OUT- type of register that can be loaded with data serially and has parallel outputs available.PISO- PARALLEL IN/SERIAL OUT- type of register that can be loaded with parallel data and has only one serial output.PIPO- PARALLEL IN/PARALLEL OUT- type of register that can be loaded with parallel data and has parallel outputs available.

74194A BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

S1

S0

MODE

H

H

PARALLEL LOAD

L

H

SHIFT RIGHT

H

L

SHIFT LEFT

L

L

NO CHANGE

OVERVIEW OFSHIFT REGISTERS Common tasks of shift registers: Serial/parallel data conversion UART (an example) Time delay Ring counter Twisted-ring counter or Johnson counter Memory device

A shift register is a sequential logic device made up of flip-flops that allows parallel or serial loading and serial or parallel outputs as well as shifting bit by bit.

CHARACTERISTICS OF SHIFT REGISTERSNumber of bits (4-bit, 8-bit, etc.)

Loading Serial Parallel (asynchronous or synchronous)

Common modes of operation. Parallel load Shift right-serial load Shift left-serial load Hold Clear

Recirculating or non-recirculating

SERIAL/PARALLEL DATA CONVERSION Shift registers can be used to convert from serial-to-parallel or the reverse from parallel-to-serial.

SERIAL LOAD SHIFT REGISTERNote the use of D FFs.Clock (CLK) inputs wired in parallel.Clear (CLR) inputs can be activated with LOWor disabled with HIGH.Preset (PS) inputs deactivated.Parallel outputs here.Order= A B C DInputs here:(1) Data(2) Clock(3) ClearClear input:Active = 0Deactivated = 1Clock input:Positive-edgetriggering0 0 0 01 0 0 01 1 0 00 1 1 00 0 1 10 0 0 11 0 0 00 1 0 04-bitserial-inparallel outshift rightshift register

QUESTION #1This is a ___ type shift register.A. Serial-in, parallel outB. Parallel-in, serial-outA: Serial-in, parallel-outQUESTION #2What is the 4-bit output (bit A on left, D on right) after pulse 1?

A: 0000QUESTION #3What is the 4-bit output (bit A on left, D on right) after pulse 2?

A: 1000QUESTION #4What is the 4-bit output (bit A on left, D on right) after pulse 3?

A: 0100QUESTION #5What is the 4-bit output (bit A on left, D on right) after pulse 4?

A: 0010QUESTION #6What is the 4-bit output (bit A on left, D on right) after pulse 5?

A: 1001QUESTION #7What is the 4-bit output (bit A on left, D on right) after pulse 6?

A: 1100TEST

PARALLEL LOAD SHIFT REGISTERNote the use of J-K FFs.Clock (CLK) inputs wired in parallel.Clear (CLR) input activated with LOW.Parallel load inputs (A,B,C,D) are active LOW.Outputs here.Order= A B C DParallel datainputs

(Active LOW)Clock input- H-to-L Clear input- Active LOW

RECIRCULATING SHIFT REGISTER0 0 0 00 0 1 11 0 0 11 1 0 00 1 1 00 0 1 10 0 0 00 1 0 0

UNIVERSAL SHIFT REGISTER IC74194 Universal 4-bit Shift Register IC.Modes of operation: Hold, Parallel load, Shift right & Shift left.An active LOW Clear (CLR) input overrides all others.Outputs hereMode Controls:

HoldParallel loadShift rightShift leftClock inputL-to-H triggeringParallel data inputs

Order: A, B, C, Dduring Parallel loadingClear inputactive LOWSerial data Right inputused during Serial Load Rightmode of operationSerial data Left inputused during Serial Load Leftmode of operation

USING THE 74194 SHIFT REGISTER ICCLR = 1

Serial R = X

Parallel Load= 0 1 1 0

Serial L = X

Clock pulse 1 (L-to-H)

S0= 1

S1= 10 1 1 0X = IrrelevantCLR = 1

Serial R = 0

Parallel Load= 0 1 1 0

Serial L = X

Clock pulse 2 (L-to-H)

S0= 1

S1= 00 0 1 1CLR = 1

Serial R = 0

Parallel Load= 0 1 0 0

Serial L = X

Clock pulse 3 (L-to-H)

S0= 1

S1= 00 0 0 1CLR = 1

Serial R = 0

Parallel Load= 0 1 0 0

Serial L = X

Clock pulse 4 (L-to-H)

S0= 0

S1= 00 0 0 1CLR = 0

Serial R = 0

Parallel Load= 0 1 0 0

Serial L = X

Clock pulse 5 (L-to-H)

S0= 1

S1= 10 0 0 0CLR = 1

Serial R = X

Parallel Load= 0 1 0 0

Serial L = X

Clock pulse 6 (L-to-H)

S0= 1

S1= 10 1 0 0CLR = 1

Serial R = X

Parallel Load= 0 1 0 0

Serial L = 1

Clock pulse 7 (L-to-H)

S0= 0

S1= 11 0 0 1CLR = 1

Serial R = X

Parallel Load= 0 1 0 0

Serial L = 0

Clock pulse 8 (L-to-H)

S0= 0

S1= 10 0 1 0

CLR = 0

Serial R = X

Parallel Load= 0 1 0 0

Serial L = X

Clock pulse 1 (L-to-H)

S0= 1

S1= 1? ? ? ?CLR = 1

Serial R = 0

Parallel Load= 0 1 0 0

Serial L = X

Clock pulse 2 (L-to-H)

S0= 1

S1= 1CLR = 1

Serial R = 0

Parallel Load= 0 1 0 0

Serial L = X

Clock pulse 3 (L-to-H)

S0= 1

S1= 0CLR = 1

Serial R = 0

Parallel Load= 0 1 0 0

Serial L = X

Clock pulse 4 (L-to-H)

S0= 0

S1= 0CLR = 1

Serial R = X

Parallel Load= 0 1 0 0

Serial L = 1

Clock pulse 5 (L-to-H)

S0= 0

S1= 1QUESTION #1The 74194 IC could be described as a 4-bit (shift right, universal)shift register.

A: UniversalQUESTION #2What is the mode of operation during and the output of the shift register after pulse 1?

A: Clear, 0 0 0 0QUESTION #3What is the mode of operation during and the output of the shift register after pulse 2?

A: Parallel load, 0 1 0 0QUESTION #4- What is the mode of operation during and the output of the shift register after pulse 3?

A: Shift right, 0 0 1 0QUESTION #5What is the mode of operation during and the output of the shift register after pulse 4?

A: Hold, 0 0 1 0QUESTION #6What is the mode of operation during and the output of the shift register after pulse 5?

A: Shift left, 0 1 0 1CLR = 1

Serial R = X

Parallel Load= 0 1 0 0

Serial L = 1

Clock pulse 6 (L-to-H)

S0= 0

S1= 1QUESTION #7What is the mode of operation during and the output of the shift register after pulse 6?

A: Shift left, 1 0 1 1TEST

SIMPLE TROUBLESHOOTING HINTSFeel top of IC to determine if it is hotLook for broken connections, signs of excessive heatSmell for overheating Check power sourceTrace path of logic through circuit Know the normal operation of the circuit