MSI Shift Registers

MSI Shift Registers• 74LS194 4-Bit

Bidirectional Universal Shift Register

• may be used in the following data register transfers– serial-serial, – shift left, – shift right, – serial-parallel, – parallel-serial, – and parallel-parallel

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MSI Shift Registers

• 74LS194 4-Bit Bidirectional Universal Shift Register

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MSI Shift Registers

• 74LS194 control inputs S1 and S0

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MSI Shift Registers


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01 11 10 00 01 11 10 0001 11 10 0001 11 10 00

MSI Shift Registers


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“Universal” shift register

74x194

• Shift left• Shift right• Load• Hold

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MSI Shift Registers

• One stage of the 74x194

MSI Shift Register 74195


or D0–D3or D0–D3

MSI Shift Register 74195• 74195 logic diagram

/P3/P3/P0/P0 /P1/P1 /P2/P2

Ring Counter

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• A ring counter is a loop of flip-flops interconnected in such a manner that only one of the devices may be in a specified state at one time

• If the specified state is HIGH, then only one device may be HIGH at one time.

• As the clock, or input, signal is received, the specified state will shift to the next device at a rate of 1 shift per clock, or input, pulse.

MSI Shift Registers

• 74LS194 control inputs S1 and S0

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Shift-Register Counters

• Ring counter

• For Shift right

S0Vcc, S1 for Load and Reset, AVcc, BCD Gnd,

QD RIN, LIN is not connected

Ring counter (Self correcting)• 4 bit, 4 state with a single circulating 1

00010001

00100010

01000100

10001000

10101010

01010101 11011101

01100110

00110011 10111011

11101110

01110111 11111111

1100110010011001

00000000

State diagram for a self correcting ring counter

Ring counter (Self correcting)• 4 bit, 4 state with a single circulating 0

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Johnson Counter (“Twisted ring” counter)

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Timing diagram for a 4-bit Johnson counter

State Name

Q3 Q2 Q1 Q0 Decoding

S1 0 0 0 0 Q3’•Q0’

S2 0 0 0 1 Q1’•Q0

S3 0 0 1 1 Q2’•Q0

S4 0 1 1 1 Q3’•Q2

S5 1 1 1 1 Q3•Q0

S6 1 1 1 0 Q1•Q0’

S7 1 1 0 0 Q2•Q1’

S8 1 0 0 0 Q3•Q2’

States of an 4-bit Johnson counter

* Can be decoded with 2-input gates

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Self correcting Johnson Counter• n-bit counter • 2n - 2n unused states• 0x…x0 → 00…01• 2 input NOR gate

performs correction

Linear Feedback Shift Register Counter• n-bit shift register counters have far less than the

maximum number of 2n normal states • n states for ring counter, 2n states for Johnson counter• An n-bit LFSR counter can have 2n – 1 states

also called as maximum length sequence generator• Design is based on the theory of finite fields• Developed by French mathematician Evariste Galois• Serial input is connected to the sum modulo 2 of a

certain set of output bits• These feedback connections determine the state

sequence of the counter• By convention, outputs are always numbered and

shifted in the direction shown in figure on next slide

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• There exists at least one equation which makes the counter go through all the 2n - 1 states before repeating

• It can never cycle through all 2n states

• Regardless of the connection pattern 0…0 → 0…0

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Feedback equations for LFSR counters

3-bit LFSR counter

X0X0

X1X1X2X2

X3X3

X2 X1 X0

1 0 0

0 1 0

1 0 1

1 1 0

1 1 1

0 1 1

0 0 1

1 0 0

Sequence

Modified LFSR Counter• An LFSR can be modified to have 2n states including

the all 0’s state• In an n-bit LFSR counter, an extra EXOR gate and an

n – 1 input NOR gate connected to all the shift register outputs except X0 accomplishes the task

• The states are not visited in binary order • Usually used where this characteristic is an advantage

- Generating test inputs for logic circuits- Encoding and decoding circuits for certain error-

detecting and error-correcting codes including CRC codes

- Scrambling and descrambling data patterns in data communications- Pseudo random binary sequence generator

Modified 3-bit LFSR counter to include all 0’s

X2 X1 X0

1 0 0

0 1 0

1 0 1

1 1 0

1 1 1

0 1 1

0 0 1

0 0 0

1 0 0

Sequence

X0X0

X1X1

X2X2

X3X3

MSI Shift Registers

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