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  • 8-Jun-20—3:41 PM

    1University of Florida, EEL 3701 – File 14© Drs. Schwartz & Arroyo

    Registers, RALU, Asynch, Synch

    EEL3701

    1 University of Florida, EEL 3701 – File 14

    © Drs. Schwartz & Arroyo

    Menu • Registers

    >Storage Registers >Shift Registers

    • More LSI Components >Arithmetic-Logic Units (ALUs) > Carry-Look-Ahead Circuitry (skip this)

    • Asynchronous versus Synchronous

    Look into my ...

    EEL3701

    2 University of Florida, EEL 3701 – File 14

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    •Q+=D

    •Q+=TQ' + T'Q

    •Q+=D•Q+=D

    •Q+=TQ' + T'Q

    •Q+=S + R' Q

    Excitation Tables (Bonus Slide)

    •Q+=D

    •Q+=TQ' + T'Q

    •Q+=S + R' Q

    •Q+=J Q' + K' Q

  • 8-Jun-20—3:41 PM

    2University of Florida, EEL 3701 – File 14© Drs. Schwartz & Arroyo

    Registers, RALU, Asynch, Synch

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    Registers

    A Storage Register n n D O

    CLK

    CLR See also Lam Fig

    5.24 (on next several pages), Mano Fig 5.1

    Commercially available models 74’273, 74’378, 74’163

    A register is a device that conceptually performs the functions: LOAD, READ, DO NOTHING, DISABLE

    We can think of them as a bank of n D-FFs.

    n

    n

    CLK READ n nLOAD

    n

    D Q

    Q

     A collection of FFs designed to work as a unit (in parallel).

    Do not use this!!! A gated-clock

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    8-bit Storage Register with Master Reset (74’273) Lam Fig 5.24

  • 8-Jun-20—3:41 PM

    3University of Florida, EEL 3701 – File 14© Drs. Schwartz & Arroyo

    Registers, RALU, Asynch, Synch

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    8-bit Storage Register / Tri-State Buffer (74’373)

    OE LE Di Q+i 1 0 - Qi 1 1 0 0 1 1 1 1 0 - - Z

    EEL3701

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    8-bit Storage Register / Tri-State Buffer (74’573)

    OE LE Di Q+i 1 0 - Qi 1 1 0 0 1 1 1 1 0 - - Z

  • 8-Jun-20—3:41 PM

    4University of Florida, EEL 3701 – File 14© Drs. Schwartz & Arroyo

    Registers, RALU, Asynch, Synch

    EEL3701

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    Octal 3-State Non- inverting Flip-Flop with Output Enable (74’574)

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    6-bit Storage Register with Enable (74’378) Lam Fig 5.24

  • 8-Jun-20—3:41 PM

    5University of Florida, EEL 3701 – File 14© Drs. Schwartz & Arroyo

    Registers, RALU, Asynch, Synch

    EEL3701

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    4-bit Storage Register Using a Counter (74’163) Lam Fig 5.24

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    Arithmetic-Logic Units (ALU’s)

    [Example] Let a computer instruction to complement the A register be COMA. The instruction COMA must do the following 3 things: (a) Connect the output of the A register to the A input of the ALU. (b) Present the ALU with control signals:

    M = H, S0 = L, S1 = L, S2 = L, and S3 = L. (c) Wait an appropriate delay and connect the output of the ALU (F3-F0)

    to the input of the A register to reload the A register.

    • ALU’s are at the heart of CPU’s - They are the combinational circuit elements that perform common functions: A set of logical functions & a set of arithmetic functions. See Lam Fig 6.1 (on next page), Mano Section 7.7

  • 8-Jun-20—3:41 PM

    6University of Florida, EEL 3701 – File 14© Drs. Schwartz & Arroyo

    Registers, RALU, Asynch, Synch

    EEL3701

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    ALU (74’181) Active-High

    View Lam Fig 6.1

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    ALU (74’181) Active-Low

    View Lam Fig 6.1

  • 8-Jun-20—3:41 PM

    7University of Florida, EEL 3701 – File 14© Drs. Schwartz & Arroyo

    Registers, RALU, Asynch, Synch

    EEL3701

    13 University of Florida, EEL 3701 – File 14

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    Arithmetic-Logic Units (ALU’s)

    [Example] Let a computer instruction to complement the A register be COMA. The instruction COMA must do the following 3 things: (a) Connect the output of the A register to the A input of the ALU. (b) Present the ALU with control signals:

    M = H, S0 = L, S1 = L, S2 = L, and S3 = L. (c) Wait an appropriate delay and connect the output of the ALU (F3-F0)

    to the input of the A register to reload the A register.

    • ALU’s are at the heart of CPU’s - They are the combinational circuit elements that perform common functions: A set of logical functions & a set of arithmetic functions. See Lam Fig 6.1 (on previous page), Mano Section 7.7

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    Register Application

    R1 3 0 3 0

    4

    4 4

    4

    R2

    4 BIT ALU

    3 0

    4

    4 Result Reg.

    S0 S1 S2 C0

    1 bit register Carry FF

    BUS

    Command Bits

    e.g., To ADD, say

    Set S0S1S2 to 010

    • Application: inside computers (CPU’s), the ALU (Arithmetic Logic Unit) performs, say, 4-bit addition.

    CLK

    CLKCLK

    CLK

    Cout

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    Registers, RALU, Asynch, Synch

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    Shift Registers 3 0

    MSB LSB

    ? 1 ? 2 Shift Right

    Shift Left

    ? 1

    RIGHT SHIFT

    ? 2

    ? 1? 2

    Logical: ?1 = “lost”, ?2 = 0 ?1 = 0, ?2 = “lost”

    Arithmetic: ?1 = “carry”, ?2 = 0 ?1 = MSB, ?2 = “lost” or “placed in a FF”

    LEFT SHIFT

    • There are two types & two directions of shift : > logical vs. arithmetic > left vs. right

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    More Shift Registers

    • If we let ?2 = ?1 on a “Left Shift” or ?1 = ?2 on a “Right Shift”, we get a “Circular Shift” or a “Rotate Shift.”

    • Some computers (CPU’s) use the Carry FF as an agent in their SHIFT operations. Especially in those that have “Rotates”, a “copy” of the last bit that participated in the shift is copied into the Carry 1-bit Register (i.e., the “Carry” FF).

    • Conceptually, Shift Registers perform: Serial Loads, Parallel Loads, Shift Lefts, Shift Rights, Parallel Reads, Serial Reads, Clears, etc.

    Show Lam Fig 5.26-5.27, Mano Fig 5.3-5.4 (on next pages)

    ? 1

    RIGHT SHIFT

    ? 2

    ? 1? 2 LEFT SHIFT

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    9University of Florida, EEL 3701 – File 14© Drs. Schwartz & Arroyo

    Registers, RALU, Asynch, Synch

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    Serial-to-Parallel: Realization of 4-bit Shift Register with

    D-FF’s Lam Fig 5.26

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    N-bit Storage Register

    • Make an N-bit storage register using N D-FFs & N 2-input MUXs

    > Load determines if loading occurs on next clock edge > For each of the i-bits, use one of the below

    Di(H) CLK

    R(L)

    D

    R

    Q 0

    1

    Load(H)

    S(L)

    S Qi(H)

    R(L)

    D LD

    R

    QS S(L)

    Qi(H) Qi(H)

    Di(H)

    CLKCLK

    Load(H)

    Functional Block Diagram

  • 8-Jun-20—3:41 PM

    10University of Florida, EEL 3701 – File 14© Drs. Schwartz & Arroyo

    Registers, RALU, Asynch, Synch

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    Serial-to-Parallel & Parallel-to- Serial:

    Bi-directional Universal Shift Register (74’194)

    Lam Fig 5.27 (Can simulate this

    with Quartus)

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    Shifting with MUXs • Make an N-bit shift register using N D-FFs & N 2-input

    MUXs > Shift determines if shifting occurs on next clock edge > Example: Shift left (ShL)

    – Shift lefts elements are identical (except for bit 0), i=1, …, n-1

    Di Qi CLK

    CLR

    D

    R

    Q0

    1Qi-1 Di

    – Bit 0 is slightly different

    Qi

    ShL

    D0 Q0 CLK

    CLR

    D

    R

    Q0

    1Gnd D0Q0

    ShL

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    11University of Florida, EEL 3701