SCOC TESTBENCH result - European Space...

SCOC Ref : R&D-SOC-NT-322-V-ASTR Issue : 1 Rev. : 0 Date : 02 June 2003 Page : ii

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SCOC Ref : R&D-SOC-NT-322-V-ASTR Issue : 1 Rev. : 0 Date : 02 June 2003 Page : iii

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TABLE OF CONTENTS

1 OBJECT ........................................................................................................................................................... 1

2 DOCUMENTS................................................................................................................................................. 1

2.1 APPLICABLE DOCUMENTS.............................................................................................................................................................1 2.2 REFERENCE DOCUMENTS .............................................................................................................................................................1

3 TESTBENCH DESCRIPTION ...................................................................................................................... 2

3.1 GENERAL DESCRIPTION ................................................................................................................................................................2 3.2 DESCRIPTION OF THE EMULATORS .............................................................................................................................................3

3.2.1 SOFT MEMORY.......................................................................................................................................................................3 3.2.2 The EMU_CONTROLER........................................................................................................................................................3 3.2.3 The EMU_SP ..............................................................................................................................................................................4 3.2.4 The EMU_Static_Mem................................................................................................................................................................4 3.2.5 1553 Emulator..............................................................................................................................................................................5 3.2.6 PCI Emulator................................................................................................................................................................................5 3.2.7 TC Emulator.................................................................................................................................................................................5 3.2.8 TM Emulator ................................................................................................................................................................................5 3.2.9 Extern Signal Emulator ................................................................................................................................................................5

3.3 SCOC SIGNALS CONNECTION .....................................................................................................................................................5 3.4 LEON CPU SOFTWARE FOR SIMULATIONS ..............................................................................................................................9

3.4.1 Global Description .........................................................................................................................................................................9 3.4.2 Detailed Description .......................................................................................................................................................................9

4 SCOC SIMULATION PLAN..........................................................................................................................13

4.1 INTRODUCTION............................................................................................................................................................................ 13 4.2 PRELIMINARY TESTS..................................................................................................................................................................... 13

4.2.1 Test of support processor emulator integration............................................................................................................................... 13 4.3 RESET........................................................................................................................................................................................... 13 4.4 LEON FUNCTIONS ...................................................................................................................................................................... 14 4.5 TEST OF CCSDS TIME MANAGER............................................................................................................................................ 14

4.5.1 Test of HDMA and IOMCTRL .............................................................................................................................................. 15 4.6 IP1553 SIMULATION.................................................................................................................................................................... 16

4.6.1 Remote Terminal (rt) mode.......................................................................................................................................................... 16 4.6.2 Bus Controller (BC) mode ........................................................................................................................................................... 17

4.7 SPACEWIRE SIMULATION............................................................................................................................................................. 18 4.7.1 Test of the Spacewire without the host interface............................................................................................................................. 18 4.7.2 Test of the host interface............................................................................................................................................................... 18 4.7.3 Test in SCoC.............................................................................................................................................................................. 19

4.8 PTCD SIMULATION PLAN .......................................................................................................................................................... 20 4.8.1 Test of the PTCD IP alone ......................................................................................................................................................... 20

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4.8.2 Test in the top level ...................................................................................................................................................................... 21 4.9 PTME SIMULATION PLAN.......................................................................................................................................................... 21 4.10 HKPF SIMULATION PLAN .......................................................................................................................................................... 22 4.11 PCI SIMULATION PLAN ............................................................................................................................................................ 23

5 SIMULATION EXECUTION....................................................................................................................... 25

5.1 DESCRIPTION OF THE SIMULATION DATABASE STRUCTURE................................................................................................ 25 5.2 SIMULATION EXECUTION........................................................................................................................................................... 27

5.2.1 Setting up the environment ........................................................................................................................................................... 27 5.2.2 Compiling VHDL structure....................................................................................................................................................... 27 5.2.3 Executing simulation................................................................................................................................................................... 27

6 SIMULATION RESULTS............................................................................................................................. 29

6.1 SIMULATED CONFIGURATION ................................................................................................................................................... 29 6.2 FUNCTIONAL RESULTS ................................................................................................................................................................ 29 6.3 COVERAGE RESULTS.................................................................................................................................................................... 29

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1 OBJECT

The purpose of this document is to describe the simulation of the SCoC. The simulation environment is derived from the generic VHDL environment used at ASTRIUM.

Section 3 describes the simulation environment (testbench) set up for SCoC simulations.

Section 4 describes the simulation plan.

Section 5 describes the database used for the simulation

Section 6 covers the simulations results.

2 DOCUMENTS

2.1 APPLICABLE DOCUMENTS

AD1 ASIC Design and Manufacturing Requirements, WDN/PS/700 Issue 2, available at

ftp://ftp.estec.esa.nl/pub/vhdl/doc/DesignReq.pdf

AD2 SCOC Functional Specification, R&D-SOC-ST-302-V-ASTR issue 0, 20/06/2002

2.2 REFERENCE DOCUMENTS

RD1 The LEON Processor User’s Manual, version 2.4.0, November 2001 RD2 IP1553 specification, R&D-SOC-NT-237-ASTR, 19/10/2000 RD3 IOMCTRL Specification And Architecture, R&D-SOC-RP-312-V-ASTR, Issue 0/0, 03/02/2003 RD4 HDMA Specification And Architecture, R&D-SOC-RP-313-V-ASTR, Issue 0/0, 03/02/2003 RD5 PCI to AMBA Bridge VHDL Model Datasheet, D/TOS-ESM/153, Issue 2/1, 18 July 2002 RD6 Packet Telecommand Decoder VHDL Core Specification ICD, R&D-SOC-RP-304-V-ASTR, 16 July

2002

RD7 Spacecraft-Controller-on-a-Chip adapted Packet Telemetry Encoder VHDL Model (SCoC_PTME), PTME-002-01 Issue 0/4, July 2002

RD8 SPACEWIRE Specification and Architecture, R&D-SOC-NT-292-V-ASTR, Issue 0/1, 22 Jan. 2003

RD9 CCSDS Unsegmented Code (CUC) and CCSDS Time Manager (CTM) Synthesisable VHDL core Data Sheet, D/TOS-ESM/SH/154 Issue 0.1 Rev. A

RD10 HouseKeeping Packetizer Function VHDL Core Description, R&D-SOC-NT-291-V-ASTR, Issue 0/0 09/10/2001



3 TESTBENCH DESCRIPTION

3.1 GENERAL DESCRIPTION

The testbench is performed with a unique VHDL test environment, the test being programmed by script files driving the behaviour of the testbench. A general description of the SCoC testbench is given in following diagram.

SCOC

SRAM/PROMCPU

EMULATOR

SRAM/PROMIO

EMULATOR

SOFT MEMORYEMULATOR

MEMORY SPYEMULATOR

SUPPORTPROCESSOREMULATOR

SpaceWireEMULATOR

PCIEMULATOR

1553EMULATOR

TMEMULATOR

TCEMULATOR

EXTERNSIGNALS

EMULATOR

.dat.CONTROLLEREMULATOR

.tb .tb

.tb

.tb

.tb

.tb

.dat.dat

Figure 3-1 : Testbench environment

The SCoC testbench integrates memory models. These memories are initialised from object dump hexadecimal files “*.dat”, including LEON start-up and program, and test data (for Spacewire, 1553).



Moreover, each functional part of the SCoC (like uart...) is connected to a dedicated emulator, which is in charge of the stimulation, verification of the good functioning of the part. Each emulator runs a script “EMU”.COM that includes all the command of the current test.

A particular emulator is called EMU_SP (for Support Processor) and is connected to the CPU IO interface. This emulator does not have a program script. This emulator allows synchronisation between the LEON test program and the emulator scripts.

Finally, each emulator (including EMU_SP) is connected to the EMU_CONTROLLER by semaphore signals. This controller allows synchronising the behaviour of the emulators (and of the LEON test code through the EMU_SP).

3.2 DESCRIPTION OF THE EMULATORS

3.2.1 SOFT MEMORY

The SOFT MEMORY (SM) is an emulator in charge of the emulation of table of data. This table of data is used by memory emulators as storage tables.

The interest of the SM is to put all the data, usually spread over many memory models, to a single location. This eases the functions of comparison of data for example.

SM is a generic emulator that is connected to other emulators by means of SM PORTS. The number of SM PORTS is configurable as a generic parameter of the SM.

The SM PORTS allow performing basic operations as read/write a byte/halfword/word, and standard C functions as memset, memcpy, and memcmp.

In addition, a generic parameter of the SM receives a list of file name, each one associated to a start address, for the initialisation of the tables.

The SM dynamically allocates memory chunks (of configurable size) when needed, thus limiting the used memory of the computer during simulations.

3.2.2 The EMU_CONTROLER

The EMU_CONTROLER entity is a generic controller that allows the synchronisation of all emulators. The EMU_CONTROLER is connected to each emulator by two signals :

• semaphore is a record giving the state of the emulator to the controller

• contsig is a pulse signal indicating that the emulator is allowed to resume execution of its script.

Each emulator accepts 5 commands :

⇒ SYNC/SYNC_AFTER [TIME] VAL set the synchronisation signal to VAL

⇒ WAIT EMU_NAME VAL wait emulator EMU_NAME to put its synchronisation to VAL

⇒ WAIT_T TIME wait for TIME



⇒ PAUSE wait for all emulators to PAUSE

3.2.3 The EMU_SP

The EMU_SP is connected for one part to the SCoC to the Memory IO port and for other part to the EMU_CONTROLER and to the SOFT MEMORY.

This allows the synchronisation of the LEON test code with the emulators. Indeed, the LEON code can emulate the basic commands of synchronisation (refer to 3.2.2) by writing and reading through the memory IO port.

In addition, EMU_SP provides functionalities for LEON to print out messages with a minimum simulation time (one access to the memory IO). The C commands used are :

• MSG

LEON writes to EMU_SP_MSG the number of the message to be written in the transcript window.

• MSG_ARG

LEON writes to EMU_SP_MSG the number of the message to be written in the transcript window and an argument appended to the message in hexadecimal.

• MSG_DRV

Same as MSG but dedicated to drivers code.

• MSG_DRV_ARG

Same as MSG_ARG but dedicated to drivers code.

In addition, EMU_SP provides an interface between SCoC and the SoftMem to command basic operations as :

• MEMCMP : compares two SoftMem areas

• MEMCPY : copy one source area to the destination area

• MEMSET : initialise a SoftMem area with a constant

To support the use of the EMU_SP in the LEON test code, the “emu_sp.h” header file defines in C or ASM the offset value of the registers described here before. This file also declares inline functions to perform the basic operations.

3.2.4 The EMU_Static_Mem

The EMU_Static_Mem allows emulating banks of memories. This emulator provides the control/address/data interface of memory banks (with multiple chip select, write enable and output



enable), connected to the SCoC. Each EMU_Static_Mem is connected to the SOFT MEMORY to write and read the data.

3.2.5 1553 Emulator

This emulator is a BC/RT emulator that allows generating commands or responding to commands. It checks the commands coming from a BC and the answers from the RT. It also checks the protocol. It is able to insert error in commands and responses.

3.2.6 PCI Emulator

The PCI emulator is a basic PCI Initiator/target agent that allows emulating basic protocol on the PCI.

The Target responds to Configuration/Memory Read/write. It is able to detect errors and disconnections. It is able to insert wait states or to prematurely abort the transfer. It checks the received data.

The initiator generates to Configuration/Memory Read/write. It is able to detect target abort/retry/errors. It can insert wait states and prematurely abort transfers. It checks the read data.

3.2.7 TC Emulator

The TC emulator generates TC segments according to the TC protocol. It can insert errors in the protocol.

3.2.8 TM Emulator

The TM emulator is not really an emulator (it is not synchronised with other emulators).

SCoC Testbench implements the generation and check procedures delivered with the PTME.

3.2.9 Extern Signal Emulator

The extern signals emulators (EMU_SET_SIG and EMU_TEST_SIG) allows generating or testing basic signals.

They generate SCoC clocks, reset, test and RTAD signals and check CPU_ERRORN and CPU_WDOGN.

3.3 SCOC SIGNALS CONNECTION



The table below describes the input/output signal connection of the SCoC VHDL model inside of the testbench.

Name Type Connections LEON Interface – Memory Bus signals ( 83) A(30:0) O EMU_CPU_ROM, EMU_CPU_RAM, EMU_SP D(31:0) IO EMU_CPU_ROM, EMU_CPU_RAM, EMU_SP BEXCN I EMU_SP BRDYN I EMU_SP IOSN O EMU_SP OEN O EMU_CPU_ROM, EMU_SP RAMOEN(3:0) O EMU_CPU_RAM RAMSN(3:0) O EMU_CPU_RAM READ O EMU_SP ROMSN(1:0) O EMU_CPU_ROM RWEN(3:0) O EMU_CPU_RAM WRITEN O EMU_CPU_ROM, EMU_SP LEON Interface – System Interface signals ( 23) CLK I EMU_SET_SIG SYSCLK O RESETN I EMU_SET_SIG SYSRESETN O EMU_TEST_SIG PIO(15:0) IO EMU_SET_SIG, EMU_UART, EMU_TEST_SIG WDOGN Open Drain EMU_TEST_SIG ERRORN Open Drain EMU_TEST_SIG PCI Interface – ( 58) PCI_AD(31:0) IO EMU_PCI PCI_CB(3:0) IO EMU_PCI PCI_PAR IO EMU_PCI PCI_FRAMEN IO EMU_PCI PCI_TRDYN IO EMU_PCI PCI_IRDYN IO EMU_PCI PCI_STOPN IO EMU_PCI PCI_DEVSELN IO EMU_PCI PCI_LOCKN IO EMU_PCI PCI_IDSEL IO EMU_PCI PCI_REQN IO SCOC PCI_GNTN IO SCOC PCI_CLK I EMU_SET_SIG PCI_RSTN IO EMU_SET_SIG PCI_PERRN IO EMU_PCI PCI_SERRN IO EMU_PCI PCI_REQN(2:0) I EMU_PCI PCI_GNT(2:0) O EMU_PCI PCI_SYSENN I EMU_SET_SIG MIL_STD 1553 Interface ( 35) RXA0 I EMU_1553_A RXA0B I EMU_1553_A TXA0 O EMU_1553_A TXA0B O EMU_1553_A TXA0INH O EMU_1553_A RXA1 I EMU_1553_A RXA1B I EMU_1553_A TXA1 O EMU_1553_A TXA1B O EMU_1553_A



TXA1INH O EMU_1553_A RXB0 I EMU_1553_B RXB0B I EMU_1553_B TXB0 O EMU_1553_B TXB0B O EMU_1553_B TXB0INH O EMU_1553_B RXB1 I EMU_1553_B RXB1B I EMU_1553_B TXB1 O EMU_1553_B TXB1B O EMU_1553_B TXB1INH O EMU_1553_B RTAD_A(4..0) I EMU_SET_SIG RTPAR_A I EMU_SET_SIG RTAD_B(4..0) I EMU_SET_SIG RTPAR_B I EMU_SET_SIG CLK1553 I EMU_SET_SIG TC Interface – ( 41) TCC(3:0) I EMU_PTCD TCA(3:0) I EMU_PTCD TCS(3:0) I EMU_PTCD TCDAT(7:0) IO EMU_RLAC LACCS O EMU_RLAC LACK I EMU_RLAC LAWR_N O EMU_RLAC MAPSTN O EMU_MAP_SERIAL MAPCK O EMU_MAP_SERIAL MAPDSR O EMU_MAP_SERIAL MAPDTR I EMU_MAP_SERIAL MAPDATA O EMU_MAP_SERIAL MAPADT O EMU_MAP_SERIAL MAPOUT1 O EMU_MAP_SERIAL MAPOUT2 O EMU_MAP_SERIAL CPDUSTN O EMU_TEST_SIG CPDUEN O EMU_TEST_SIG CPDUDIV I EMU_SET_SIG CPUDEXT(4) TBD RFAVN I EMU_SET_SIG VCLSB I EMU_SET_SIG RSTTCN I EMU_SET_SIG TM Interface – ( 13) VC3CK I packetWire procedure VC3DATA I packetWire procedure VC3DTR I packetWire procedure VC3DSR O packetWire procedure VC4CK I packetWire procedure VC4DATA I packetWire procedure VC4DTR I packetWire procedure VC4DSR O packetWire procedure VC5DATA O packetAsynchronous procedure VC6DATA O packetAsynchronous procedure TMCKI I EMU_SET_SIG TMO O TM acquisition procedure chain TMCKO O TM acquisition procedure chain IO Memory Interface – ( 42)



TMDAT(15:0) IO EMU_IO_RAM, EMU_IO_ROM TMADR(18:0) O EMU_IO_RAM, EMU_IO_ROM TMRWN O EMU_IO_RAM, EMU_IO_ROM TMRAMCSN(3..0) O EMU_IO_RAM TMROMCSN O EMU_IO_ROM Central Time Management Interface (2) CTMEVENT I EMU_SET_SIG CTMPULSE O EMU_TEST_SIG Spacewire interface (12) SW0_TXS O EMU_SPACEWIRE SW0_TXD O EMU_SPACEWIRE SW0_RXS I EMU_SPACEWIRE SW0_RXD I EMU_SPACEWIRE SW1_TXS O EMU_SPACEWIRE SW1_TXD O EMU_SPACEWIRE SW1_RXS I EMU_SPACEWIRE SW1_RXD I EMU_SPACEWIRE SW2_TXS O EMU_SPACEWIRE SW2_TXD O EMU_SPACEWIRE SW2_RXS I EMU_SPACEWIRE SW2_RXD I EMU_SPACEWIRE



3.4 LEON CPU SOFTWARE FOR SIMULATIONS

3.4.1 Global Description

Test simulation plan is based on the use of a test program running on the CPU to activate, control and check internal behaviour of the SCoC.

LEON CPU boots in PROM at address 0. A “Startup” program basically initialise memory controller and jump into SRAM at address 0x40000000.

Reset program at address 0x40000000 contains the trap table, the “hardreset” function that initialise interrupts and jumps to the main test function, “tb”.

The “tb” function is then specific to each test performed.

Basic drivers or macro help the use of the SCoC and simulation resources.

For simulation, some basic functions, such as message printing to the stdout (of simulator), memory initialisation, copy or comparison are accelerated.

• Memory operations are handled by the EMU_SP (support processor). Commands are activated through the memory mapped IO interface of LEON

• Global registers g6 and g7 are used respectively as index to EMU_SP and to APB bridge

A strict minimum of initialisation is performed in the boot procedure. Then the runtime for simulation is not compatible of a runtime for program development.

3.4.2 Detailed Description

3.4.2.1 Startup (PROM)

The startup boot strap is defined in the file Prom.S (assembler). The boot strap consists in :

• initialise LEON internal state registers

• initialise CPU memory controller registers

• initialise %g7 to Apb start address

• call the reset handler (see next section)

The boot strap is compiled and the object file is loaded into the CPU PROM at address 0

3.4.2.2 Reset Handler (RAM)

The reset handler is defined in the file Reset.S (assembler). This file includes :



• the initialisation of the trap table :

• reset trap calls reset handler at address 0x1000

• exception trap write a trap message with help of the EMU_SP and stop the program (ta 0)

• interrupt trap call the interrupt handler : definition of the interrupt and call of the function installed for this interrupt. User can change the interrupt function installed with the function “install_callback”

• other traps (including soft trap) write a trap message with help of the EMU_SP and stop the program (ta 0)

• the reset handler :

• initialise TBR, WIM and stack pointer

• enables traps

• call tb (user defined testbench)

Note that there is no trap handler for basic window_overflow or window_underflow. The purpose of the test program is not to test the behaviour of LEON.

Then when developing a test program, one must consider not using too many subprogram calls.

3.4.2.3 Test Program

Each test program should include the header file <tbscoc.h>. This header file includes header files of all the drivers and also declares the “tb” symbol (test program entry).

The table below gives the list of the HEADER files and their basic content :



tbscoc.h scoc.h

DEFINE physical address of APB, Spacewire, PCI scoc.base.h

assign Apb base address to %g7 MACRO APBLoadReg,APBSetReg,APBGetReg scoc_defs.h DEFINE SCoC register addresses, register fields common.h

MACRO for GNU assembler TYPEDEF basic integer types

MACRO for data structure initialisations emu_sp.h

assign emu_sp base address to %g6 MACRO WAIT, WAIT_T, PAUSE, SYNC, SYNC_AFTER, MSG, MSG_ARG, MSG_DRV, MSG_DRV_ARG, MEMCMP, MEMCPY, MEMSET emu_sp_defs.h

DEFINE EMU_SP register addresses, commands tbscoc_defs.h DEFINE testbench emulators it_mgr.h

DEFINE interrupt numbers and masks PROTOTYPE “init_it” and “install_callback” (it_mgr.c)

uart_driver.h MACRO for access to UART registers PROTOTYPE “InitUart”, “SendToUart”, “RecFromUart” polled buffer exchange (uart_driver.c)

uart_driver_it.h PROTOTYPE “InitUartIT”,”SendToUartIT”,”uart0_ITHandler” and “uart1_ITHandler” (uart_driver_it.c) fifo.h

definition of byte FIFO buffer used for buffered UART transfer hdma_driver_it.h

DEFINE interrupt numbers and masks MACRO for access to HDMA registers

PROTOTYPE “HDMAIT_Init”, ”HDMAIT_Transfer”, « HDMAIT_Handler » (hdma_driver_it.c)

ctm_driver.h DEFINE Frequency initialisation for 1Hz generation MACRO for access to CTM registers

irq2_driver.h DEFINE interrupt numbers and masks for secondary interrupt controller MACRO for secondary interrupt controller register access

PROTOTYPE “IRQ2_init_it”, “IRQ2_install_callback” and “IRQ2_IT_Handler” (irq2_driver.c)

iomctrl.h MACRO for IOMCTRL register access 1553_driver.h

MACRO for IP1553 register access

PROTOTYPE “C53_Init” and “C53_IT_Handler” (1553_driver.c)



sw_driver.h MACRO for SPACEWIRE register access PROTOTYPE interrupt handling functions (sw_driver.c)

pci_driver.h MACRO for PCI register access DEFINE PCI constants and commands

PROTOTYPE “GET_PCI_BRIDGE_CFG”, “GET_PCI_CORE_CFG”, “PCI_APB_SGL_R”, “PCI_APB_BURST_R”, “PCI_APB_SGL_W”, “PCI_APB_BURST_W”, “PCI_DMA” and interrupt handling functions (pci_driver.c)

ptcd_driver.h PROTOTYPE “ptcd_map_it”, “get_tc_seg”,”new_tc_seg_status” (ptcd_driver.c) ptme_driver.h

PROTOTYPE “read_comp”, “send_papb8” and “send_papb16” functions equivalent to procedures of the PTME testbench (ptme_driver.c)

msg_driver.h DEFINE message numbers associated to DRIVER messages

util.h PROTOTYPE functions GetPSR, SetPSR, GetFSR, SetFSR (util.c)

In the test program, a message section (put in C comment) can be define. The “extractmsg” script will extract these messages and generate automatically different files :

• msg.em.h define a number for each message symbolic name

• msg.em.S defines strings containing these messages

• msg.em.txt is used by EMU_SP to map the messages to the MSG function calls of LEON

//BEGIN_MSG // // MSG1 "Starting TEST_UART" // MSG2 "End of test program" // MSG3 "Initialisation PIO" // MSG4 "Initialisation UART1" // MSG5 "Initialisation UART2" // MSG6 "Send message UART1" // MSG7 "Wait inter messages" // MSG8 "Send message UART2" // MSG9 "Receive message UART1" // MSG10 "Receive message UART2" // MSG_ERR1 "******ERROR, Wrong message received" // MSG_OK1 "OK : Message received correctly" // //END_MSG



4 SCOC SIMULATION PLAN

This section describes the simulation performed at SCoC level and reminds simulations performed at block level for some blocks.

4.1 INTRODUCTION

Each test described in the next section corresponds to a script file for the emulators and to a C file for LEON program.

Each test use LEON, and then LEON mapping and functionality in SCoC is tested during all tests.

An initial sequence used for each test sets the SCoC clocks and reset the SCoC.

Each test starts with a message indicating the simulation name.

At the end of each test, the signal FIN_SIMU is set to 1 from the EMU_SET_SIG.

4.2 PRELIMINARY TESTS

4.2.1 Test of support processor emulator integration

The first test is to validate the connection of LEON with its support processor emulator (EMU_SP) , as this EMU_SP is used throughout all other simulations. It also tests the connecting of EMU_SP with the SOFTMEM.

Simulation Name Description Init_test Use of MSG, WAIT_T and PAUSE commands

1 Test of messages without arguments (MSG) 2 Test of messages with arguments (MSG_ARG) 3 Test of synchronisation with emulators (WAIT, SYNC, PAUSE) 4 Test of interface with the softmem (MEMCPY, MEMCMP, MEMSET)

4.3 RESET

This simulation tests the reset value of all SCoC registers

Simulation Name Description reset_test test of the reset values of LEON internal registers

1 Reset SCoC (TC_RSTN and CPU_RSTN) 2 Read each SCoC register and compare with the expected value. In case of non

expected value, issue a message with EMU_SP indicating the register address, the expected value and the read value.

3 At the end of the test issue a message OK if no error has been detected



4.4 LEON FUNCTIONS

LEON functions are tested by individual test of LEON. The “reset_test” simulation tests the connection of the internal services to the APB interface. Access to memory is tested in the preliminary test “init_test”. This test validates the connection of the PIO to the SCoC top level, with a test of the UARTs.

Simulation Name Description Test_uart Test of emission and reception with UART 1 and UART 2 (polling UART status)

1 Initialisation of UART 2 Send message to UART 1. EMU_UART1 compares the received message with the expected

message and issue a report. 3 Send message to UART 2. EMU_UART2 compares the received message with the expected

message and issue a report. 4 EMU_UART1 sends a message. LEON checks the received message and issue a report 5 EMU_UART2 sends a message. LEON checks the received message and issue a report

Test_uart_it Test of emission and reception with UART 1 and UART 2 and IT generation 1 Initialisation of UART with interrupts 2 Initialisation of sending and receiving FIFO 3 Send message to UART 1. EMU_UART1 compares the received message with the expected

message and issue a report. 4 Send message to UART 2. EMU_UART2 compares the received message with the expected

message and issue a report.

This test validates :

• the connection of the UART to the APB bus

• the connection of the UART interrupt line to the interrupt handler

• the connection of the interrupt handler to the IU

4.5 TEST OF CCSDS TIME MANAGER

The test of the CCSDS time manager consists in testing the access to the CTM through the main APB interface, the connection of the CTM interrupt line to the interrupt controller, and the connection of the CTM inputs and outputs to the switch matrix.

The Second APB interface (for time source packet acquisition) is tested in the test of the HKPF function.

Référence Description Test_ctm CTM initialisation, time sampling and pulses generation

1 Initialise CTM 2 Initialise Switch Matrix 3 Wait 100 us 4 Read CUC P and T field, set an alarm to current time + 50 us, enable alarm interrupt 5 check the interrupt 6 Wait 100 us 7 Read CUC P and T field 8 connect alarms(1) to CTM_PULSE SCoC output (switch matrix) 9 enable alarms(1)



10 connect alarms(0) to CTM_PULSE SCoC output (switch matrix) 11 enable alarms(0) 12 connect seconds(1) to CTM_PULSE SCoC output (switch matrix) 13 enable seconds(1) 14 connect seconds(0) to CTM_PULSE SCoC output (switch matrix)

15 enable seconds(0)

16 For each periodic pulses output, connect successively to CTM_PULSE SCoC output (switch matrix)

17 enable pulses

18 Connect successively CTM_EVENT SCoC input to events CTM inputs (switch matrix)

19 generate CTM_EVENT pulse

20 read datation register

4.5.1 Test of HDMA and IOMCTRL

This test verify the connection of the HDMA to the CPU AHB and IO AHB bus. The tests also check the connection to the APB bus and to the secondary interrupt controller.

In addition, this test checks the IOMCTRL connection to the IO AHB bus, to the APB bus and to the secondary interrupt controller.

Reference Description Test_hdma DMA transfer between CPU memory and IO memory

1 Initialise IO memory controller 2 Transfer data from CPU memory to IO memory (32 bits words) – compare data 3 Transfer data from IO memory to CPU memory (32 bits words) – compare data 4 Transfer data from CPU memory to IO memory (16 bits words) – compare data 5 Transfer data from IO memory to CPU memory (16 bits words) – compare data 6 Transfer data from CPU memory to IO memory (8 bits words) – compare data 7 Transfer data from IO memory to CPU memory (8 bits words) – compare data 8 Program a transfer with 64 bits data size – verify occurrence of system error

Test_cpu_io CPU to IO transfers with IT handling (HDMA transactions are queued and managed by interrupt handler)

1 Initialise IO memory controller 2 Initialise Interrupt Controller 3 Initialise HDMA transfer queue 4 Program 3 CPU to IO transfer in transfer queue 5 Wait for End of 1st transfer – compare data 6 Wait for End of 2nd transfer – compare data 7 Wait for End of 3rd transfer – compare data

Test_io_cpu CPU to IO and IO to CPU transfers with IT handling 1 Initialise IO memory controller 2 Initialise Interrupt Controller 3 Program error address in IOMCTRL corresponding to 2nd transfer 4 Initialise HDMA transfer queue with 3 transfers 5 Program 3 IO to CPU transfer in transfer queue



6 Wait for End of 1st transfer – compare data 7 Wait for End of 2nd transfer – verify the occurrence of transfer error Wait for End of 3rd transfer – compare data

4.6 IP1553 SIMULATION

The test of the IP1553 verify the connection of the IP to the IO AHB bus, to the APB bus, to the secondary interrupt controller and to the switch matrix.

The IP is tested in BC and RT mode. BM mode is not used as it does not increase the test coverage in the SCoC.

4.6.1 Remote Terminal (rt) mode

Référence Description Test_rt_1553_nom Nominal exchanges in 32 bits mode (reception and emission commands)

1 Initialise IO memory controller 2 test 1 word emission 3 test 3 words reception 4 test 2 word emission 5 test 2 words reception 6 test 3 words broadcast reception

Test_rt_1553_nom_16 Nominal exchanges in 16 bits mode (reception and emission commands) + access in extended memory without updating buffers

1 Initialise IO memory controller 2 test 1 word emission 3 test 3 words reception 4 test 2 word emission 5 test 2 words reception 6 test 3 words broadcast reception 7 Mode command : Load Ext Mem Address register MSB 8 Mode command : Load Ext Mem Address register LSB 9 4 words emission in extended memory area with extended memory area mode deactivated 10 4 words emission to invalid Sub-address in extended memory area with extended memory

area mode activated 11 4 words emission in extended memory area with extended memory area mode activated

Test_rt_1553_nom_st Nominal exchanges of 32 words in 32 bits mode (reception and emission commands) with updating buffers

1 Initialise IO memory controller 2 test two 32 words reception to the same sub-address with updating buffer 3 test two 32 words reception to the same sub-address without updating buffer 4 test two 32 words emission to the same sub-address with updating buffer 5 test two 32 words emission to the same sub-address without updating buffer 6 test four 1 word reception to the same sub-address with updating buffer

Test_rt_1553_nom_CC Mode commands



1 Initialise IO memory controller 2 Sending of the CC n°0 with DBC enable and check of the status to verify that the DBC bit is

active. 3 Sending of the CC n°0 with DBC disable and check of the status to verify that the DBC bit is

inactive. 4 Sending of the CC n°1 and check of the activation of ItTrok and ItSync. 5 Sending of the CC n°1 with ItTrokMask and ItSyncMask activated and check of the non-

activation of ItTrok and ItSync. 6 Sending of the CC n°2: Transmit status word 7 Sending of the CC n°8 with Mode Command Reset disable 8 Sending of the CC n°8 with Mode Command Reset enable – check occurrence of C53Rst

interrupt 9 Sending of valid and legal reception command 10 Sending of CC n°4 Transmitter Shutdown 11 Sending of valid and legal reception command on redundant 1553 bus. 12 Sending of the CC n°8 with Mode Command Reset enable. 13 Sending of valid and legal reception command. 14 Sending of the CC n°16: Transmit Vector Word 15 Connect the SYNC output to the CTM_PULSE output with the switch matrix - Sending of

the CC n°17: Synchronize with data word – check occurrence of the SYNC.

Test_rt_1553_AHBerr Hresp error on the different types of AHB access in RT mode 1 Initialise IO memory controller 2 Error during « characterization word » read – check occurrence of error interrupt 3 Error during « indirection table » read 4 Error during data read/write 5 Error during “command word” write 6 Error during “indirection table” write

4.6.2 Bus Controller (BC) mode

Référence Description Test_bc_1553_nom Nominal program in burst enable mode

1 Initialise IO memory controller 2 connect CTM pulses(0) output to the CYCLE input of IP1553 with the switch matrix –

Program CTM to generate periodic pulses(0) (every 2 ms). 3 connect CTM pulses(1) output to the SLOT input of IP1553 with the switch matrix –

Program CTM to generate periodic pulses(0) (every 500 µs). 4 connect CTM alarm(0) output to the DELIN_N input of IP1553 with the switch matrix –

generate an alarm(0) after 2,5 ms 5 Start BC program 6 1 word Emission – wait for SLOT 7 2 words reception – wait for SLOT 8 4 words RT-RT exchanges – wait for CYCLE 9 3 words reception – wait for DELIN_N 10 32 words emission

Test_bc_1553_err Same program as test_bc_1553_nom but with memory access errors 1 Initialise IO memory controller 2 Start BC program 3 Program IOMCTRL Error during Program Pointer Loading 4 Program IOMCTRL Error during Instruction Block reading 5 Program IOMCTRL Error during data read/write



4.7 SPACEWIRE SIMULATION

This section reminds the test performed on the Spacewire as standalone block and then describes the simulation for the integration of the Spacewire blocks in the SCoC.

4.7.1 Test of the Spacewire without the host interface

The spacewire (host interface not included) is connected with the Austrian Aerospace spacewire emulator. The verification is done on the FIFOs data.

Spacewire

d_in

d_out

s_out

s_inSpacewire Emulator

d_in

d_out

s_out

s_in

The Austrian Aerospace test bench checks the protocol initialization, the TX interface, the RX interface and the Time Code, FCT and data management.

The test cases performed are:

• Link Startup

• Normal operation

• Error cases

• Stress Cases (TX and RX rates are different)

To execute these simulations, go to the $PROJ/archi/spacewire/cur/simenv2 directory then type RUN.

Then, check the transcript windows of Modelsim.

4.7.2 Test of the host interface

Two spacewires are connected together.

Spacewire1

Spacewire2

d_in

d_in

d_out

d_out

s_out

s_out

s_in

s_in

APB

APB

AHB

AHB

SoftMem

This test checks the TX AHB master and slave interface and the RX AHB master interface.

To check the TX AHB master/slave of one spacewire, the data received by the other spacewire is verified.

The RX AHB master is checked for normal operations and operations performed when the area limit is reached.



The following check points are performed:

• Data are transmittted using TX AHB master and the received data are checked in the SoftMem.

• The RX AHB master stops writing when the available memory area is full.

• Correct status generated when the current area becomes full but no other area is available.

• Area1 becomes full and area2 is available.

• Area2 becomes full and area1 is available.

• Exceeding the area (when packet can't be entirely stored into the area).

• Transfer abortion.

• Behaviour of Area1_valid and Area2_valid signals in normal mode and test mode.

• Launching a new transfer after abortion.

• Test of the interrupts (interrupts and mask)

• Time code test (triggered by CTM or APB write).

• Error response when wr/rd access to the TX AHB slave is improperly performed.

• Retry, split and error response of the TX AHB master.

• Test of the "Link not enabled" interrupt.

• TX AHB slave test.

To launch the simulation, go to the $PROJ/archi/spacewire/cur/simenv1 directory then type "run_simu5".

The transcript file should contain no error message.

4.7.3 Test in SCoC

The spacewire is instantiated in the scoc_core module. Two spacewires are connected together for this test. The test goal is to check the AMBA CPU AHB and APB connection, the connection of the interrupts to the secondary interrupt controller and the time code to the switch matrix.

Référence Description Test_spacewire Test of the Spacewire integrated into SCoC

1 Initialise Spacewire blocks 2 Start links – verify connection 3 Transmit list of packet in TX AHB master mode in both directions – check received data on

the other link 4 Transmit packets in direct TX AHB slave mode in both directions – check received data on

the other link 5 Check access to all registers and interrupt generation 6 Transmit time packets with the CTM_EVENT and CTM_PULSE connected to tick_in and

tick_out with the switch matrix



4.8 PTCD SIMULATION PLAN

This section reminds the test performed on the PTCD as standalone block and then describes the simulation for the integration of the PTCD blocks in the SCoC.

4.8.1 Test of the PTCD IP alone

The test environment is depicted hereafter:

EMU_APBSLV

EMU_TEST_SIG

PTCD

EMU_AHBSLV_SM

SOFTMEM

IO_AHBARB

EMU_MEM_SPY

LAC Counter

EMU_MONITOR

EMU_PTDTC

EMU_PTDTMPAR1

EMU_PTDMAPPAR1

EMU_PTDCLCW1

EMU_APBMST

RFAVAIL, VCLSB

configuration & HKPF link

CLCW information

MAPCPU_IT

CLCW serial link

MAP link

TM link

TC transfer

VHDL blocks have been developed to emulate the behaviour of the PTCD block environment. The VHDL emulators used for the test are:

• EMU_APBMST is used for the PTCD block configuration through APB bus. It also retrieves information for the HKPF block such as the TC FAR, AU and CPDU values.

• EMU_TEST_SIG checks the interrupt activation.

• IO_AHBARB manages the AHB master/slave traffic.

• EMU_AHBSLV_SM interfaces between AHB slave and SoftMem.

• SOFTMEM is an advanced memory block.

• EMU_MEM_SPY checks the memory data.

• EMU_APBSLV is an APB slave used to receive the CLCW information sent by the PTCD.

• The LAC counter stores the LAC value.

• The EMU_PTDCLCW1 checks the CLCW serial link.

• The EMU_PTDMAPPAR1 checks the MAP parallel link.

• The EMU_PTDTC generates TC frames.



• The EMUPTDTMPAR1 check the TM parallel link.

The PTCD IP is in parallel mode for the following tests:

• None regression tests

• HKPF APB interface test

• MAP CPU test

• CLCW APB interface test

4.8.2 Test in the top level

Référence Description Test_ptcd Test of the PTCD integrated into SCoC

1 Initialise IO memory 2 Initialise PTCD 3 Send TC segment destined to the CPU – check MAP IT management – check data 4 Send TC segment destined to the Serial MAP interface – check the output of the segment

4.9 PTME SIMULATION PLAN

The different I/O interfaces (PacketAPB, PacketWire, PacketAsynchronous, CLCW APB) are tested.

The following tests are performed:

• TM frame generation with internal and external telemetry clock

• TM frame generation from VC0, VC1, VC2, VC3, VC4, VC5, VC6 and VC7

• Checking of the CLCW value (from PTCD through APB)

The TM output is reported in .txt files. These files must be compared with reference files to validate the PTME.

The PacketAPB interfaces are validated using the CPU APB bus and the HK APB bus.

The PacketWire and PacketAsynchronous interfaces are validated using emulators provided by ESA.

The TM output is written into report files by VHLD procedures provided by ESA.



PTME

PAPB0 PAPB1 PAPB2 PW3 PW4 PA5 PA6

CPU APB

HK APB

PacketWireEmulator

PacketWireEmulator

PacketAsynchronousEmulator

PacketAsynchronousEmulator

SCOC

Splitdecoder

ConvolutionDecoder

NRZDecoder

ScramblingDecoder

TurboDecoder

ReedSolomonDecoder

report file

report file

report file

CLCW APB

4.10 HKPF SIMULATION PLAN

The test of the HKPF consists in the test of the connection of the HKPF to the CPU APB and to the HK_APB busses. The connection of the trigger input signals to the switch matrix are also tested.

Référence Description Test_hkpf Test of the HKPF and HK APB bus

1 Initialise IO memory 2 Initialise PTCD 3 Initialise CTM



4 Initialise PTME 5 Connect CTM_PULSE to the trigTC input of HKPF – generate a pulse on CTM_PULSE 6 Trig PTCD source packet acquisition and transfer 7 Fill Context RAM with data in random access mode 8 Connect CTM_PULSE to the trigContext input of HKPF – generate a pulse on

CTM_PULSE 9 Fill Context RAM with data in FIFO mode 10 generate a pulse on CTM_PULSE (Trig context RAM packet generation) 11 Connect CTM_PULSE to the trigCTM input of HKPF and to the event(0) input of CTM –

program CTM to generate time source packet on event(0) 12 generate a pulse on CTM_PULSE 13 Check TM output for HKPF TM packets.

4.11 PCI SIMULATION PLAN

PCI module (PCI CORE and PCI wrapper) is tested in its standalone testbench. Additional tests are performed at SCoC level in order to test the integration of the PCI module in the SCoC.

The test verifies :

• connections internal to SCoC

o the connection of the 3 AHB busses (Initiator Master, Initiator Slave, Target Master)

o the connection of the APB bus

o the connection of the interrupt line to the interrupt controller

• connections external to SCoC

o connection of the PCI bus

o connection of the PCI arbiter

Référence Description Test_pci_1 Test of the PCI module in host mode

1 Initialise PCI target emulator with 12 bits IO area and 22 bits memory area 2 Check PCI core status through APB interface 3 Check PCI wrapper status through APB interface 4 Initialise PCI interrupts (unmask all interrupts) 5 Enable PCI master and target interfaces. Set BAR1 to 0x40000000 and BAR2 to 0x80000000 6 Read Status of the first agent (PCI target emulator) (5 first registers and BAR registers) –

Detect BAR requirements of first agent 7 Configure Memory and IO BAR of the first agent (PCI target emulator) 8 Test simple PCI memory read and write through APB interface 9 Test error and interrupt generation for access to an unimplemented agent (Master Abort) 10 Test simple IO memory read and write through APB interface 11 Test PCI direct write access (through Initiator AHB slave interface) to PCI emulator 12 Test PCI direct access to an unimplemented agent (Master Abort) – verify error and interrupt

generation



13 Test Memory read and write to PCI emulator in DMA mode (Initiator AHB master interface) 14 Test of wait states insertion by PCI agent 15 Test of PERR assertion by the PCI emulator – verify interrupt generation 16 Test target interface : read in IO area (access to SCoC registers from a PCI initiator) 17 Test target interface : write in memory area (write to CPU RAM from a PCI initiator) 18 Test target interface : read in memory area (read in CPU RAM from a PCI initiator)



5 SIMULATION EXECUTION

5.1 DESCRIPTION OF THE SIMULATION DATABASE STRUCTURE

The delivered database is described in figure below scoc_archi

modelsim.inicompilesetup.csh

amba

source

tb

simenv1

vhdl source files

vhdl testbench files

work

modelsim.inicompile

Makefileall_simu

Standard structure

package_scoc stand. struct.

package_emu stand. struct.

spacewire stand. struct.

ptcd stand. struct.

ptme stand. struct.

iomctrl stand. struct.

hdma stand. struct.

ioahbarb stand. struct.

ctm stand. struct.

ip1553 stand. struct.

switch stand. struct.

spacewire

stand. struct.

scoc stand. struct.

hkpf stand. struct.

pci stand. struct.

leon

leon = source

isiface

pci_arb

LEON vhdl source files

PCI wrapper vhdl source files

PCI arbiter vhdl source files

pcicore compiled PCI core

bin

tbpp

docref

codrf

tbref

spwref

work2

simenv2



Top level of the SCoC RTL architecture is scoc_archi. At this level, 3 files are present :

setup.csh : setep environment variables for modelsim scripts

compile : global modelsim compilation of all modules

modelsim.ini : library declaration for all modules and standard packages

For each module, a standard structure is created. In this structure, one can find :

source: directory containing the VHDL RTL description of the module

tb : directory containing the VHDL description of the testbench

simenv1 : directory where to launch compilation and simulation. always includes at least 3 files :

compile : modelsim compilation script

modelsim.ini : local modelsim.ini . Points out to the global modelsim.ini file

all_simu : lauch the simulations

work : directory created by the compilation. Library for the module.

The compile script compile all source files and testbench files. It creates a Makefile with the vmake modelsim command.

The all_simu script launchs selected simulations step of the module for selected configuration.

For LEON module, there is no local simulation. Compilation of LEON and PCI source files is performed in the SCOC module.

The pcicore module corresponds to the compiled modelsim library of the InSilicon PCI core.

The spacewire module contains the standard structure plus the ESA reference testbench structure, modified to be adapted to the applicable Spacewire specification.

The bin directory contains script files used for all modules. Currently, it contains then TestBench Pre Processor (TBPP) script.



5.2 SIMULATION EXECUTION

5.2.1 Setting up the environment

The source script setup.csh in the directory scoc_archi set up environment variables used for the simulation.

The created/modified environment variables are :

ARCHI = path to the top of SCoC architecture = scoc_archi (created)

PATH = YOUR_PATH/scoc_archi/bin:$PATH

In addition, the script creates a link to scoc_archi/leon in scoc_archi/source. This link is used by the synthesis script to access to LEON VHDL sources.

5.2.2 Compiling VHDL structure

In the directory scoc_archi, launch the CSH script compile. This script compiles each module of the SCoC VHDL description in the correct order.

After each module is compiled a first time, a Makefile file is created in [module_name]/simenv1 by the command vmake.

The script compile detects the presence of the file Makefile and executes the UNIX make command instead of compile for the module. To force the re-compiling of the modules, lauch compile with the option –f (force).

5.2.3 Executing simulation

SCoC simulations are executed in the directory scoc_archi/scoc/simenv1. The script file all_simu launch the simulations. The synopsis of the command is :

all_simu config_name|-m|-a test_name|-m|-a timing|-m

where :

config_name : name of the top_level configuration or entity to simulate

test_name : name of the test step to execute

timing : for pre-layout simulations, type none

for post-layout simulations, type none, min, typ or max

The name of the top_level configuration can be :

pre_layout_sim : Normal simulation of SCoC

pre_layout_nopci_sim : Configuration that allocate and empty PCI architecture core (useful when no VERILOG simulator is available)



pre_layout_blade : The SCoC for BLADE board is wrapped in a standard SCoC top level for simulations (uses architecture scoc_blade_wrapped of scoc entity)

pre_layout_blade_nopci : Idem as pre_layout_blade with an empty PCI architecture

post_layout_blade : Post layout VHDL netlist wrapped in the SCoC top level for simulations (uses architecture scoc_blade_post_wrapped of scoc entity)

Typing –a instead of a configuration name launches the simulation for all configurations in sequence.

Typing –m prints out a menu to select the configuration.

The name of the test corresponds to the tests described in section 4 of this document.

Typing –a instead of a test name launches the simulation for all tests in sequence.

Typing –m prints out a menu to select the test.

The list of the tests and a small description are in the file scoc_archi/scoc/script/liste_simu.txt.

The script all_simu can be edited to modify global options of the simulations :

BATCH : if 1, then simulations are launched in batch (command line) mode

COVER : if 1, coverage analysis is launched and coverage results are incrementally stored in the file [config_name]_global.cov. The scoc_archi/scoc/simenv1/Exclude.cov file lists all files excluded from the coverage analysis (standard packages, testbench …)

Modelsim transcript files are saved in the file [config_name]_[test_name].log (suppressing the initial Modelsim messages Loading …).



6 SIMULATION RESULTS

6.1 SIMULATED CONFIGURATION

The SCoC version simulated is SCOC_V1R3.

The configuration used for the simulations is : pre_layout_sim.

The version of the simulator used is : 5.5b

6.2 FUNCTIONAL RESULTS

All simulation log files are analysed. The simulation detects no errors.

For the tests test_ptme and test_HKPF, the Telemetry output files are examined and manually checked.

6.3 COVERAGE RESULTS

All simulations are launched with the –coverage option of vsim simulator. Results of previous coverage are reloaded for each simulation. Then the coverage results here correspond to all the simulation steps.

PTCD and IP1553 are not covered by these results.

The figures below correspond to the total coverage results :

# Coverage Report Totals : Files 46, Lines 3459, Hits 3131, Coverage Percentage 90.5

The non covered lines at top level simulation correspond to :

• unimplemented lines for the SCoC configuration : “if generate” clauses with false condition, unimplemented EDAC in the IOMCTRL module, reduced maximum burst size in HDMA …

• never accessed states of the combinatorial logic : “when others” clauses for example

• impossible conditions to generate at top simulation level : SPLIT or RETRY answer on AHB bus for example.

The table below lists all the files with missed lined and the reasons of the non coverage of these lines (files with 100% coverage are not in the table). File total hit generate unimp. never

access non

simulated comment on non simulated

SCOC scoc_core 195 127 68 HDMA apbslv 92 87 4 1 CPU AHB transfer error pack_hdma 16 14 2 HKPF crtrans 61 58 1 2 address counter overflow ctmtrans 39 38 1 emarb 79 67 1 11 registering of multiple requests during

packet transfer hkapbmst 146 145 1 hkp_apbslv 81 73 4 4 read Context RAM in FIFO mode



File total hit generate unimp. never access

non simulated

comment on non simulated

tctrans 77 76 1 IOAHBARB ioahbarb 91 80 9 2 access to an unimplemented slave IOMCTRL iomctrl 285 253 6 4 22 Burst on PROM

Size, protection and mapping errors pack_iomctrl 90 68 1 15 6 timeout error SPACEWIRE ahb_mst_rx 313 271 42 SPLIT and ERROR responses on AHB

Receive buffer limit conditions for packet storage

ahb_mst_slv_tx 252 209 1 42 SPLIT and ERROR responses on AHB ahb_tx_int 99 94 5 packet transfer abort init_fsm 108 92 16 transitions in case of errors rx_decod 147 140 7 alternate phase of D/S signals rx_mgt 64 48 16 multiple data and/or EOP/EEP

detected at the same time in the SW_CLK domain

spacewire 4 3 1 sw_counters 62 59 3 counters (outstanding and credit) errors sw_reg 206 194 1 11 interrupts due to errors tx_ack 59 47 12 multiple data to acknowledge in

sequence tx_mgt 104 102 2 FIFO flush SWITCH switch 32 29 3 TOTAL 80 26 18 204

All functionality of the blocks not covered by the SCoC global testbench are covered by the module local testbench.

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