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Rapid ARM-based JPEG Processor report of HW/SW Co-Design Professor: 陳少傑 Students: R91921061...
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Transcript of Rapid ARM-based JPEG Processor report of HW/SW Co-Design Professor: 陳少傑 Students: R91921061...
Rapid ARM-based JPEG Processorreport of HW/SW Co-Design
Professor: 陳少傑
Students: R91921061 林耿賢 R91921062 李源華 P91921001 陳宗裕
Outline Block of ARM-based JPEG Processor JPEG Software Demo Benchmark of JPEG Software Why use hardware 2D DCT? Algorithm of Row-Column decomposition 2D DCT. Matlab Demo of this Algorithm Comparison Reference
Rapid ARM-based JPEG Processor
Integrate which we learn in the HW/SW Co-Design and ARM Lab.Embedded System/ Real Time Operation System.ARM 32-bits processor/ AMBA Bus.JPEG Algorithm.
Block Diagram 1ARM Core ARM7TDMI
On-ChipRAM
DMAMaster
Bridge
AHB
UART
Timer
PIO
Keypad
APBMemory Interface
A typical AMBA systemAHB CMOS Sensor
Wrapper
Block Diagram 2
ARM7TDMIRun(uC/OSII, JPEG Encoder..) DRAM
AHB CMOS Sensor
Wrapper
ARM semi-Hoster
AHB
CMOS Image Sensor
i-Magic Technologies IM88023A
JPEG Algorithm
Color TransformRGB to YUV
Down Sampling DCT Quantization
HuffmanEncoding
JPEG File
BMP File
JPEG Encoder in Mobile Phone
Task 2: Communication Task
Task 1: Read a frame from COMS Sensor and JPEG Encoder
JPEG ARM Software Demo
JPEG Software Demo 1
Peppers.bmp Peppers.jpg
ARM JPEG Encoder
JPEG Software Demo 2
ARM JPEG Encoder
Mandrill.bmp Mandrill.jpg
Benchmark of the ARM JPEG Software
DCT Quant. VLC
Cycles 5000 3000 3000
Block of 2D DCT in ARM-based JPEG Processor
ARM7TDMIRun(uC/OSII, JPEG Encoder ..) DRAM
AHB CMOS Sensor
Wrapper
ARM semi-Hoster
AHB
2D DCT
Product of DSC 1SunPlus – GT8980
Product DSC 2TMS320DSC25
Algorithm of 2D DCT
N
vn
N
umvufnkmk
NnmF
N
u
N
v 2
)12(cos
2
)12(cos),()()(
2),(
1
0
1
0
Tc
TTc
Tc
T
CfCfFCffassume
CfCF
)(
The original 1D DCT
Row-Column decomposition (RCD) method
Transposition Memory
1-D DCT
Inp
ut
Bu
ffe
r
Ou
tpu
t B
uff
er
Matlab Demo of 2D DCTOur Algorithm
Algorithm of 1D DCT 1
)cos()cos( xx
)2
cos()2
cos( xx
Algorithm of 1D DCT 2
)7()0(
)6()1(
)5()2(
)4()3(
)4()3(
)5()2(
)6()1(
)7()0(
0000
0000
0000
0000
0000
0000
0000
0000
)7(
)3(
)5(
)1(
)6(
)2(
)4(
)0(
ff
ff
ff
ff
ff
ff
ff
ff
geca
cgae
eagc
aceg
fbbf
dddd
bffb
dddd
y
y
y
y
y
y
y
y
)16
7cos(
8
2
)16
6cos(
8
2,)
16
5cos(
8
2
)16
4cos(
8
2,)
16
3cos(
8
2
)16
2cos(
8
2,)
16cos(
8
2
g
fe
dc
ba
Where
Algorithm of 1D DCT 3
))4()3(())7()0((
)))5(2(())6()1((
)6(
)2(
ffff
ffff
fb
bf
y
y
))5()2()6()1(())4()3()7()0((
))5()2()6()1(())4()3()7()0((
0
0
)4(
)0(
ffffffff
ffffffff
d
d
y
y
Algorithm of 1D DCT 4
Algorithm of 1D DCT 5
Algorithm of 1D DCT 6
Architecture Design for Proposed
Transposition Memory 1
Architecture Design for Proposed
Transposition Memory 2
Comparison1D DCT
Compare with software