Rambus Seminar

Equalization & Clock Recovery for a 2.5-10 Gb/s 2PAM/4PAM Backplane Transceiver Cell

May 2, 2003Fred ChenSr. Member of Technical StaffRambus Inc.

UC Berkeley BWRC Seminar

Agenda

• The Backplane Environment

• PAM2 vs. PAM4 signaling

• Link Design

• Simulation & Measured Results

• Conclusions


The Backplane Environment

• There are many sources of Z and thus many possible sources of reflections• Board Material Loss• Counter Bored Backplane Vias

Back plane connector

Line card trace

Package

On-chip parasitic (termination resistance and device loading capacitance)

Line card via Back plane trace

Backplane via


Backplane Component Effects

PCB only

PCB + Connectors

PCB, Connectors,Via stubs & Devices

Device parasitics alone can cause add’l 5dB loss at high

frequencies


Variations Within a Backplane

• Four channels from a single FR4 backplane

• There are large variations between channels


Single Bit Response

0 1 2 3 4 5 6

x 10-9

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

ns

VEqualized & Unequalized Single Bit Response

•Iimpact of reflections increases when relative to equalized eye•Wworst-case sequence can sum all reflections

0 1 2 3 4 5 6

x 10-9

-0.08

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0.08

ns

V


TXDATA

RXDATA

AT

AR

CR

CT

D

B

500 1000 1500 2000-10

-8

-6

-4

-2

0

2

4

6

8

10

gh-gh conn. (baseline) : Normalized Raw and eq pulse response: PR length aftermain 60

% o

f th

e re

ceiv

ed m

ain

A T,R

A2 T,R

B

C T,R D

500 1000 1500 2000-10

-8

-6

-4

-2

0

2

4

6

8

10


% o

f th

e re

ceiv

ed m

ain

500 1000 1500 2000-10

-8

-6

-4

-2

0

2

4

6

8

10


% o

f th

e re

ceiv

ed m

ain

A T,R

A2 T,R B

C T,R D

T

Reflection Sources

• Primary reflection sources are at the connector/backplane transition• Grouped in time – as a function of backplane length


(left) 2-PAM probability distribution function (PDF) showing the probability of an eye waveform for each voltage at the sample point (right) equalized eye with worst-case pattern. 6.4Gb/s over 20” backplane.

-15 -10 -5 0-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2V

olt

ag

e [

V]

log10

pdf0 0.5 1 1.5

x 10-10

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

sec

Eye With Worst Case Reflections


Agenda



• Link Design


• Conclusions


What is 4-PAM

• Binary (NRZ) is 2-PAM• 2-PAM uses 2-levels to send

one bit per symbol• Signaling rate = 2 x Nyquist

• 4-PAM uses 4-levels to send 2 bits per symbol

• Each level has 2 bit value• Signaling rate = 4 x Nyquist

00

01

11

10

1

0

1

0

Note : both can be either single-ended or differential


When Does 4-PAM Make Sense?

• First order : slope of S21• 3 eyes : 1 eye = 10db

• loss > 10db/octave : 4-PAM should be considered

0.0 1.0 2.0 3.0 4.0 5.0

Nyquist Frequency (GHz)

|H(f

)|

-20db

-40db

-60db


Agenda



• Link Design• Equalization• Clocking


• Conclusions


Equalization For Loss : Flatten Response

• Channel is band-limited• Equalization : boost high-frequencies relative to

lower frequencies

+

=


Transmit Linear Equalizer : SBR

0.0 0.3 0.6 0.9 1.2-0.3

-0.1

0.1

0.3

0.5

0.7

UnequalizedEqualization PulseEnd of Line

time (nsec)

Vo

ltag

e


Transmit and Receive Equalization

• Transmit and receive equalizers are combined to make a range restricted DFE• Tx equalizer functions as the feed-forward filter• Rx equalizer restricted in performance of loop

TAP SELLOGIC

TXDATA

3

RXDATA


Tx & Rx Equalization Ranges

TX Driver/Equalizer : 5 taps1(pre)+1(main)+3(post)

RX Equalizer5-17 taps after mainPick any 5 taps


2-PAM/4-PAM Transmitter

• Transmit either 2-PAM or 4-PAM using Gray code

2-PAM: LSB=0

00

TP

TN10

00

TP

TN01 11 10

4-PAM

4-PAMEncoder

[MSB,LSB] TNTP

A[0]

A[1]

A[2]


5-Tap 2P/4P Transmitter (Original)

• Simple 2P/4P transmitter: Total gate = 3W/L• 5-Tap 2P/4P transmitter: Total gate = 15W/L

TNTP

A[0]

A[1]

A[2]

1/z

1/z

...

A[0]

B[0]

1/z

E[0]

TNTP

W/L

W/L

W/L

W/L

W/L

W/L

WB[6:0]

WA[6:0]

WE[6:0]


5-Tap 2P/4P Shared Transmitter

Total gate = 3(5) = 15W/L Total gate = 3(7/8+5/8) = 4.5W/L

WB[6:0]

1/z

1/z

...

A[0]

B[0]

1/z

E[0]

TNTP

W/L

W/L

W/L

WE[6:0]

...A[0]...

Sh

are

dD

riv

er

Se

gm

en

ts (

7)

E[0]

De

dic

ate

d T

ap

Dri

ve

rs (

5)

AllocationLogic

WA[6:4] ...

WE[6:4]

A[0]

...WA[3:0]

W/8L

...A[0]

E[0]

W/8L

E[0]

WE[3:0]

W/8L

W/8L

TNTP


Receive Equalizer

Sampler

VariableDelay

CDR

PhaseMixer

UP/DOWNRx Data

0101...

Calibrate

TrainingSequence

ReceiveEqualizer

Tap Weights

Tap Select

Normal Rx Path

......

...


Dual Loop PLL/DLL Design

• Self-biased 4x or 5x RefClk Multiplier based on [Maneatis, Sidiropoulos, Horowitz]

• CDR is DLL w/PLL vectors & phase mixers• 2X oversampling per bit (edge + data)• Dual loop design avoids harmonic locking

PD

Low PassFilter VCO

Ref Clk

÷ 4,5

Phase MixersCDRLogic

RXData

RX Clk

TX Clk


Multi PAM clock recovery• Data can transition from and to any level• 2PAM CDR may lock to any of three strong

timing distributions


4-PAM Edges & CDR

• Timing errors possible if using a 2-PAM CDR on unrestricted 4-PAM data

Minor Major

10

11

01

00

MSB threshold

LSBthresholds


2-PAM/4-PAM CDR

• 2-PAM mode - uses major transitions • 4-PAM mode - uses minor transitions

Tran(2PAM) = MSBTran

Tran(4PAM) = (LSBTran * MSBTran) + (MSBTran * LSBTran)

MajorityVoter

CDR clkMSBTranDet

LSBTranDet

CDRtransitionselection

2PAM/4PAM Mode

Early/Late

Tran PhaseMixer


Complete Link Block Diagram

Serial to Parallel

Phase Control

Parallel to Serial

Vtt

TXP

TXNTX Data

SysClk

RefClk

1/4 or 1/5

1 or 1/2PLL

Vtt

RXP

RXN

RX Clk

RX Data

Tclk

RX Equalizer

Tap Weights

Phase Mixer

Phase MixerPhase MixerPhase Mixer Rclk

Rclk

Tap Selection

TX EQ

TX

Clocking

RX


Agenda



• Link Design


• Conclusions


Measured PLL (+TX) Jitter

2.3psec rms; 18psec p-p @ 3.2GHz(6.4Gbps @ 2P, 12.8Gbps @ 4P) 0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 1 2 3 4

PLL frequency [GHz]

RM

S J

itte

r [%

UI]

Includes on-chip noise


Measured 4-PAM CDR Performance

• 2-PAM CDR on 4-PAM data• 60ps p-p @ 8Gb/s

Phase

Phase

Cycle

• 4-PAM CDR uses only minor transitions

• Lower dither jitter• 35ps p-p @ 8Gb/s


System Level Simulink Model


TX Equalization EffectivenessU

n-f

old

ed:

10*

TF

old

ed

No EQ w/TX EQ

20” of FR4 & two connectors


2-PAM eye with no equalization at 6.4Gb/s over 20” BP


2-PAM eye with Tx equalization at 6.4Gb/s over 20” BP


10G Eyes & System Margin Shmoos

• 3”/20”/3” = 26” Trace + 2 Connectors• Tested to BER < 10-15


(left) 4-PAM PDF showing broad distributions and (right) eye including worst-case transitions at 10Gb/s over a 20” backplane.

-15 -10 -5 0-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

Vo

lta

ge

[V

]

log10

pdf0 1 2

x 10-10

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

sec

Data Level Distribution With No Receive Equalization


(left) 4-PAM PDF showing narrowed distributions and (right) eye including worst-case transitions showing improvement of both distributions and eyes. 10Gb/s over 20” BP

-15 -10 -5 0-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

Vo

lta

ge

[V

]

log10

pdf0 1 2

x 10-10

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

sec

Data Level Distribution With Receive Equalization


RX Equalization Effectiveness

• Measured system margin with device shmoo shows large improvement with RX Eq

20” of FR4 & two connectors

No RX Eq With RX Eq


Agenda


• PAM2 (NRZ) vs. PAM4 signaling

• Link Design


• Conclusions


Prototype System Evaluation

• Constructed line cards with commercially available and next generation connectors

• A complete matrix of backplanes was constructed• 5 connectors X 3 materials • Counterbored/Non-Counterbored vias

• System components (packages, vias, connectors, traces, etc.) were individually measured to construct complete channel models


2P/4P Performance by Configuration

2-PAM (NRZ) Maximum Performance (Gbps)

0

2

4

6

8

10

12

Top Bottom Top Bottom Top Bottom Top Bottom

20" 20" 10" 10" 20" 20" 10" 10"

FR4NoCB FR4NoCB FR4NoCB FR4NoCB Nelco6kCB Nelco6kCB Nelco6kCB Nelco6kCB

0 1 2 3 4 5 6 7

4-PAM Maximum Performance (Gbps)

0

2

4

6

8

10

12

Top Bottom Top Bottom Top Bottom Top Bottom

20" 20" 10" 10" 20" 20" 10" 10"

FR4NoCB FR4NoCB FR4NoCB FR4NoCB Nelco6kCB Nelco6kCB Nelco6kCB Nelco6kCB

0 1 2 3 4 5 6 7

Configuration Space

5 Different connectors

2 Different dielectrics

2 Different via types

2 Different Trace lengths

Top & Bottom Layers


Summary & Conclusions

• Backplane Environment is very challenging• Frequency dependent dielectric and skin loss • Many variations between channels• Reflection locations in time vary with length and Nyquist• Does not scale due to increasing need for complexity

• With the right silicon approaches copper backplanes can run at 10Gb/s

TX

RX

PLL Process 0.13 CMOS

Power 40mW / Gb

Area 1mm2

2-PAM Range 2 – 6.4 Gb/s

4-PAM Range 4 – 10 Gb/s

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