DesignCon 2012

Design and Characterization of the Power Supply

System for a High Speed 1600 Mbps DDR3

Interface in Wirebond Package

Ralf Schmitt, Rambus Inc. [Email: rschmitt@rambus.com]

Hai Lan, Rambus Inc.

Abstract

This paper presents a supply system design methodology for high-speed interface

systems used in the design of a 1600 Mbps DDR3 interface in wirebond package. The

high data rate and challenging system environment requires a system-level approach of

supply noise mitigation that demonstrates the full spectrum of Power Integrity

considerations typical in the design of high-speed interfaces. We will first discuss supply

noise considerations during the architectural design phase used to define a supply

mitigation strategy for the interface design. Next, we will discuss the physical

implementation of the supply network component on the chip, the package, and the PCB

using a co-design approach. Finally, we will present measurement data demonstrating the

achieved supply quality and correlations to simulation results based on supply systems

models developed during the design phase of the interface.

Authors Biography

Ralf Schmitt received his Ph.D. in Electrical Engineering from the Technical University

of Berlin, Germany. Since 2002, he is with Rambus Inc, Los Altos, California, where he

is a Senior Engineering Manager leading the SI/PI group, responsible for designing,

modeling, and implementing Rambus multi-gigahertz signaling technologies. His

professional interests include signal integrity, power integrity, clock distribution, and

high-speed signaling technologies.

Hai Lan is a Principal Engineer at Rambus Inc., where he has been focusing on on-chip

power integrity and jitter analysis in high-speed and/or low-power I/O interfaces,

specializing in advanced modeling, simulation, and on-chip characterization. He received

his Ph.D. in Electrical Engineering from Stanford University in 2006 with his doctoral

research on substrate coupling noise in mixed-signal ICs and SoC. His professional

interests include on-chip and system PI and SI, mixed-signal integrated circuits, high-

speed interconnects, and advanced silicon effects such as substrate noise coupling.

Acknowledgement

Special thanks go to June Feng for extensive SI and PI simulations as well as channel

correlation on the final system.

Also special thanks go to Elias Lozano for his extensive work on supply noise

measurements and the extraction of self- and transfer supply impedances in the final

system.

I. Introduction

Power Integrity is an important design aspect for high-speed interfaces systems. Supply

noise causes jitter in clocking and timing paths, commonly called Power Supply Induced

Jitter (PSIJ), which reduces the timing margin of internal signal paths as well as the

timing margin of the entire interface system. Noise on the power supplies of driver and

receiver circuits also effect the signal integrity of the interface system, causing timing

jitter and voltage noise that reduces the system margin. Interfaces operating in the Multi-

Gigabit range require a supply system design that thoroughly analyzes supply noise and

its impact on system performance and carefully optimizes the power supply design in a

co-design covering architectural decisions of power partitioning and the implementation

of the Power Distribution Network (PDN) on chip, package, and PCB.

In this paper, we will present the design and characterization methodology for the power

supply system of a DDR3 interfaces operating at 1600Mbps in a low-cost wirebond

package. In this interface system, the supply design was particular challenging due to a

data rate target that is relatively high for DDR3 signaling, which leaves very little room

for supply noise induced margin losses. Further challenges were the high inductance of

wirebond packages, which causes supply noise as a response to current changes, and the

large output driver currents in DDR3 systems during SSO events. It therefore required the

development of a highly optimized supply system for this interface design which

exemplifies the general considerations required for the design of high-quality interface

supply systems. The design methodology presented in this paper can therefore also be

used as a general reference for the supply system design of advanced high-speed interface

systems.

First, we will discuss the critical design considerations for the power supply systems

during the architectural phase of the interface design, defining the principle strategy for

supply noise mitigation in this design. We will analyze critical timing paths in the

interface and determine the impact of supply noise on these paths. Based on this analysis,

we will define power supply domains that separate circuits generating large noise

currents from timing circuits that are sensitive to supply noise and define supply noise

targets for each of these rails.

Next, we will describe the physical implementation of the PDN in the target system

environment. We will analyze the requirements on the supply impedance in order to

control self-induced noise on each supply rail. We will also analyze noise coupling

between different supply rails using the supply transfer impedance between supply rails

and define strategies to mitigate this noise coupling. Finally, we will use a

chip/package/PCB co-design approach to design a PDN that meets both the requirements

for self-induced noise as well as noise coupling.

Finally, we will present characterization results of the supply system measured on the

final system implementation. Using on-chip noise measurement circuits implemented in

this design we will present supply noise measurements as a function of interface activity

and data pattern and demonstrate the effectiveness of the noise mitigation strategies

defined earlier in the design process. We will also characterize the noise coupling

between supply rails and correlate this with the prediction of our supply model used for

the design of the PDN. In these measurements we will show that noise coupling,

especially in a challenging system environment like a wirebond package, limits the

supply quality achievable in an interface design, and that a system-level design approach

is required to mitigate these challenges and achieve the high data rate targeted in this

interface design.

II. Power Supply Architecture

II.1. Target System Overview and Design Challenges

The interface described in this paper is a DDR3 PHY providing a bandwidth of 6.4GB/s,

which is achieved using an x32 data bus operating at a data rate of 1600Mbps. The design

targets high-performance consumer electronic applications like DTV systems that require

high memory bandwidth in a cost-optimized system environment. A detailed description

of the target system requirements can be found in [1].

In order to meet the cost targets of these systems, the PHY was designed in a 4-layer

wirebond package, which is significantly less expensive than flip-chip packages, however

it poses challenges for signal and power integrity especially at higher data rates.

Furthermore, the PHY is designed for a system implementation in a 4-layer PCB with

tolerance and routing rules typical for low-cost high-volume-manufacturing system

environments. Finally, silicon area, pad count, and decoupling requirements were

carefully optimized to minimize total system cost for the memory subsystem.

The goal for the design project was a PHY and package implementation that will reliably

achieve the targeted data rate under High Volume Manufacturing (HVM) conditions

using any DDR3 DRAM meeting the JEDEC spec at the targeted data rate. In order to

meet this project goal it was not enough to design and analyze the PHY alone. Instead,

the PHY had to be analyzed in the targeted system environment, optimizing system,

package, and PHY implementation concurrently. Closing the voltage and timing (VT)

budget on the system level resulted in design requirements for PHY, package, and PCB

necessary to achieve the targeted interface system performance in the final

implementation using the low-cost system environment defined for this project. Details of

this system-level analysis can be found in [2].

Creating a cost-efficient high-speed memory interface requires careful analysis of power

and system integrity. The memory device itself requires more than 40% of the bit time for

internal timing, leaving little more than half of the bit time for all channel and PHY

timing errors. Bond wires in the PHY package lead to crosstalk especially at the high data

rates targeted for this design. Routing the signaling channel in 4-layer stack-up in

package and PCB only allows for microstrip instead of stripline routing, adding further

crosstalk to the signaling channel. As a result, a significant amount of system margin has

to be reserved for crosstalk related voltage and timing errors, leaving very little margin

for supply noise related voltage and timing errors.

Unfortunately, designing a high-quality PDN in a low-cost wirebond package is

particular challenging. The bond wires in a wirebond package contribute significantly to

the inductance of the power distribution network (PDN) of the interface. Inductance in

the supply path is always a challenge for a PDN design, as it will cause supply noise

whenever the current dissipation of the PHY is changing. Achieving the Power Integrity

necessary for a high data rate operation in a system environment that is highly inductive

by nature is a serious challenge and requires a supply design strategy that starts early in

the architectural design of the interface system itself.

II.2. Supply Partitioning

The first step in the planning of a supply design strategy is the decision of a suitable

supply partitioning. Finding the best suited supply partitioning requires an analysis of the

noise generated in the supply system and the sensitivity of circuits to this supply noise.

Ideally, a constant supply voltage Vnom is provided to the circuits on the chip. In reality,

the supply voltage is transmitted through various elements of the PDN in the PCB, the

package, and on the silicon chip, and each of these elements adds impedance to the

supply path that will cause voltage variations dependent on the current dissipation of the

circuits. A common way to describe the impact of the PDN on the supply noise uses the

supply impedance ZPDN seen by the circuits on the chip when looking into the PDN.

Figure 1 shows a simplified schematic of a PDN and the typical profile of ZPDN over

frequency ([3]).

Figure 1: PDN Schematic and Resulting ZPDN Profile

Using ZPDN, the supply noise generated in a system as a result of current changes in the

design can be described as:

( ) ( ) ( ) ( )

This relationship shows that large supply noise amplitude is generated when the circuit

current has significant components at frequencies where the ZPDN impedance is high.

Worst case noise is usually generating when supply current changes are exciting the

package-chip resonance frequency around 50…200MHz where the resonance between

package related inductance and on-chip decoupling capacitors causes a peak in ZPDN.

Luckily, not all of the circuits in a PHY design are able to excite the package-chip

resonance of the PDN, and also not all circuits are equally sensitive to supply noise. As it

turns out, many of the circuits that are very sensitive to supply noise don’t create much

noise themselves, because their current spectrum does not have components in the range

of high ZPDN. Other circuits that will generate large supply noise are often less sensitive to

supply noise. An effective concept to control the impact of supply noise on the circuits in

the system is therefore a supply partitioning that separates the circuits sensitive to supply

noise from the circuits generating most of the noise.

In our DDR3 design we separated the circuits of the PHY into the following categories:

PLL circuits:

The current changes generated by the PLL are very small. Most of the current

changes occur at the frequency of the data-rate clock (i.e. 800MHz and harmonics)

where the on-chip decoupling capacitors provide a low PDN impedance. Minor

current components are generated at the reference clock frequency, which could be

close to the package-chip resonance, but these current components are usually too

small to generate significant noise.

The sensitivity of the PLL circuits to supply noise is high, especially around the

frequency of the PLL loop bandwidth around 30…50MHz. But the supply noise

generated by the PLL in this frequency range is small. At the data-rate clock

frequency, where most of the PLL noise is generated, the sensitivity of the PLL is

low.

Clocking circuits (other than PLL):

The current changes generated by the clocking circuits are occurring at the frequency

of the data-rate clock, where the PDN impedance is low.

The sensitivity of clocking circuits to supply noise is high, and usually largely

constant over a wide frequency range.

Other internal (digital and mixed-signal) circuits:

The current changes of these circuits are usually large and depend on the activity of

the PHY and the pattern transmitted by the PHY. These currents therefore can excite

the package-chip resonance of the PDN for a pathological data or activity pattern.

The sensitivity of most of the circuits, however, is low to moderate.

Output driver circuits:

Output drivers are generating large current transients to drive large external loads. The

frequencies of these current transients are dependent on the data pattern transmitted by

the PHY and they can excite the package-chip resonance for pathological data pattern.

The sensitivity of output drivers to supply noise is usually low, but noise can be

substantial if the drivers switch simultaneously (SSO noise) and then have significant

impact on the system margin of the interface.

Based on these categories, the PHY was designed using four separate supply rails:

Rail Vnom Circuits Comment

VDDP 0.9V PLL Localized at PLL location

VDDA 0.9V Clock tree,

Timing circuits

Distributed over entire PHY

VDDIO 1.5V /

1.35V

SSTL output drivers,

ODT

Vnom mandated by DDR3 Spec

VDDR 0.9V All other circuits Main supply rail for internal circuits

Defining different supply rails for a PHY design does not imply that these supply rails

have to be separated through the entire supply system down to separate VRM modules. In

many cases, as long as the nominal voltages are the same, rails that are separated on the

PHY (i.e. on the silicon) can be consolidated either in the package or on the PCB, as long

as noise coupling between these rails can be controlled in such a way that each supply rail

will meet its noise target at the silicon level. In the case of the DDR3 PHY described in

this paper we will later see that all three supply rails sharing the same nominal voltage of

0.9V (VDDP, VDDA, and VDDR) can be derived from the same VRM module on the

PCB.

II.3. Supply Noise Sensitivity

After defining the supply partitioning and identifying circuits sharing the same supply

rail, the noise targets for each of these rails has to be identified. For this, we have to

understand how supply noise affects the system margin of the interface system.

There are two major sources of supply induced margin loss in a DDR3 system. The first

source is SSO (Simultaneous Switching Outputs) noise on the output driver supply. This

noise, generated when many output drivers are switching at the same time causing large

current transients on the driver supply, causes timing errors as well as voltage distortions,

both creating margin loss in the interface systems. We will analyze this impact in a SI/PI

co-analysis of the signaling channel described later.

The second source of supply noise induced margin loss comes from Power Supply

Induced Jitter (PSIJ) on clock and signal paths inside the PHY. However, not every

timing jitter inside a PHY translates into margin loss. Depending on the clocking

architecture of an interface, some jitter components might be tracked between different

paths, reducing or eliminating the impact of this jitter on system margin. In order to

identify critical jitter components, we have to review the critical timing relationships in

the interface systems and identify the impact of supply noise on the different signal paths

involved in this timing relationship.

II.3.1. Critical Timing Relationships in WRITE Mode

Figure 2 shows a signaling schematic of a DDR3 interface systems in WRITE mode. The

critical timing relationships defined in the DDR3 Specification for this mode are marked

with a red arrow. For details of the timing relationships defined in the DDR3

specification please see [5].

Figure 2: DDR3 Signaling Schematic and Critical Timing Arcs in WRITE Mode

There are several critical timing relationships defined at the DDR3 pins during WRITE

access that the controller PHY has to meet:

DQ relative to DQS/DQS#:

In a DDR3 interfaces the timing on the DQ data bus is most critical, since these

signals are transmitted at the full (double) data rate. The critical timing parameters on

this bus are defined relative to differential data strobe signals DQS/DQS#. As a result,

jitter that is shared between the DQ data signals and the DQS/DQS# strobe signals is

not affecting the system timing margin. Only PSIJ components due to DQ and

DQS/DQS# mismatches have an impact on this timing margin.

For the most part, DQ and DQS/DQS# signal paths are matched in a byte. The major

mismatch between both signal paths comes from the 90 phase shift necessary for the

DQS/DQS# signals. This phase shift places the DQS/DQS# crossing into the center of

the DQ data eye, making it possible for the DRAM to latch DQ data using DQS/DQS#

as trigger (Figure 3). This phase shift can add unmatched PSIJ to the strobe primarily

for high-frequency VDDR and VDDIO supply noise. The impact of VDDIO noise will

be covered during SSO analysis. PSIJ due to VDDR noise will be covered in circuit

simulations used to extract the internal transmitter (data output uncertainty tQ) and

receiver (setup and hold times tS and tH) timing of the PHY described in [4].

Figure 3: DQ relative to DQS/DQS# during WRITE Access in a DDR3 System

CA relative to CK/CK#

The differential clock signal CK/CK# generated by the PHY acts as a timing reference

source for the internal DRAM timing and has to meet various jitter requirements

defined in the DRAM specifications. There is an extensive specification for jitter on

CK/CK# over different frequency range the controller PHY design has to meet,

limiting the acceptable PSIJ on the clock signal due to VDDP and VDDA noise.

The clock signal also acts as timing reference for the control and address signals on

the CA bus. Again, the clock signal is phase-shifted by 90 relative to CA signals,

adding mismatch between both signal paths. But timing requirements on this bus are

less critical since the CA bus only operates at half the data rate of the DQ bus.

There are additional timing requirements between DQS/DQS# and CK/CK#, but these

are driven by system-level timing considerations where PSIJ plays a minor role.

II.3.2. Critical Timing Relationships in READ Mode

A similar analysis has to be done for the READ mode. Figure 4 shows the signaling

schematic in READ mode, again marking the critical timing relationships in red.

Figure 4: DDR3 Signaling Schematic and Critical Timing Arcs in READ Mode

CA relative to CK/CK#

The timing requirements of CA<> relative to CK/CK# in READ mode are the same as

for WRITE mode, due to the uni-directional nature of the CA bus.

DQ relative to DQS/DQS#

In READ mode, the strobe signals are sent by the DRAM in-phase with the DQ data

signals. The controller has to line up the strobe signals relative to DQ signals to latch

the data appropriately. This again results in a mismatch that can add unmatched PSIJ

to this strobe path, but as in the WRITE mode case, this PSIJ impact can be made

negligible compared to other timing error terms by a careful matching of strobe and

signal paths.

Jitter on the CK/CK# clock signals, however, can have a much larger impact on the

DQ margin during READ access. Jitter on the CK/CK# signal decreases the output

hold time parameter tQH of the DRAM device ([5]), reducing the DQ eye opening

during READ operations. Therefore, minimizing jitter on the CK signal, keeping it

even lower than required by the DRAM specification, gains system margin during

READ access.

II.3.3. Summary of Supply Noise Requirements

Based on the analysis of critical timing parameters in the DDR3 PHY the supply rails in

the design have to meet the following noise requirements:

VDDP and VDDA:

Supply noise on these two rails primarily adds PSIJ to the CK/CK# differential clock.

The total jitter on CK/CK# has to meet the DDR3 clock jitter spec in all frequency

ranges. Furthermore, CK/CK# jitter (and thus VDDA and VDDP noise) should be

minimized to gain DQ margin during READ access. A PSIJ analysis of CK/CK# will

analyze the necessary decoupling and package design requirements to meet the jitter

targets in the project.

VDDR:

VDDR is the supply used by most of the high-speed circuits in the PHY. These

circuits require minimum voltage headroom in order to achieve their target

performance. The necessary decoupling and package requirements will be analyzed

using worst-case noise simulations.

VDDR also adds PSIJ to the clock (CK/CK#) and strobe (DQS/DQS#) path. The

impact on clock jitter will be analyzed during CK/CK# PSIJ analysis. The impact on

strobe timing will be covered in circuit simulations extraction the transmitter and

receiver timing parameters of the PHY.

VDDIO:

Major VDDIO noise will be excited during SSO events. SI/PI co-simulations will be

used to analyze the impact of SSO on the system margin and to identify the

decoupling requirements to control this margin loss. Due to the offset

III. Power Distribution Network Analysis and Design

In the previous section we have partitioned the power distribution system into separate

supply rail, combining circuits that share similar noise sensitivity as well as noise

generation profile. After this, we analyzed the critical timing requirements in the system

and identified the supply rails affecting margin on these timing arcs.

In the next step, we have to decide for a noise design target for each rail that will meet the

performance requirements of the system. For this, we have to quantify the impact of

supply noise on the critical timing relationships. Based on a sensitivity analysis we can

specify a noise target for each rail and calculate the worst-case margin loss associated

with the accepted supply noise levels. This margin loss can then be incorporated in a

system-level VT budget analysis, making sure that the system has sufficient margin under

all operating conditions to achieve the performance target.

III.1. Power Supply Induced Jitter (PSIJ)

A systematic approach to analyze the jitter impact of supply noise was presented in [6]

and [7]. The flow of this methodology is shown in Figure 5.

Figure 5: Methodology to predict Power Supply Induced Jitter (PSIJ) ([7])

In order to estimate the supply noise impact on jitter, this method predicts the jitter

spectrum, J(f), which in obtained by the product of supply noise spectrum, V(f), and jitter

sensitivity profile, S(f), all in frequency domain. The Inverse Fourier Transform of the

jitter spectrum provides the jitter sequence over time, which can be used to calculate the

peak-peak jitter and the statistical jitter distribution ([2]).

The jitter sensitivity profile is solely determined by the circuit realization and

independent of the circuit activity. On the other side, the supply noise spectrum is

determined by both the power delivery network and the current profile, a variable

depending on different circuit activity and data pattern ([2]).

For the definition of supply noise targets, we are inverting the steps of this methodology.

We are starting from PSIJ targets acceptable for the system-level VT budget of the

interface. Using the Jitter Sensitivity Profile of the signaling path we can define worst

case supply noise budgets for each supply rail necessary to meet these PSIJ targets.

III.1.1. PSIJ sensitivity

In the DDR3 system the major timing relationship affected by PSIJ is the jitter on the

differential clock CK/CK#. Figure 6 shows the signaling path and the supply rail used for

each circuit block.

Figure 6: CK/CK# Signaling Path and Supply Rails

The circuit blocks in the clock signaling path are using the supply rails VDDP, VDDA,

VDDR, and VDDIO. The impact of VDDIO noise on this signal path will be addressed in

the SSO noise analysis described later. Figure 7 shows the supply noise sensitivity of this

path for the remaining supply rails.

Figure 7: PSIJ Sensitivity Profiles of Clock Signaling Path

III.1.2. Margin Impact of PSIJ

From the sensitivity profiles in Figure 7 we can derive the following supply noise

requirements and margin impact:

For VDDP, self-induced noise occurs primarily at data-rate frequencies, where

sensitivity is very low. The PSIJ impact of this self-induced noise is negligible.

At lower frequencies noise can be coupled into VDDP from other supply rails. This

will be discussed later in more detail. is primarily caused by coupling from other

supply rails, described in detail later. This coupled noise can cause significant PSIJ,

therefore, noise coupling into VDDP has to be limited by the design of the PDN.

Luckily, noise coupling is strongest around the package/chip resonance frequencies of

the PDN, which is typically between 50MHz and 200MHz. In this frequency range

PSIJ sensitivity to VDDP noise is not very high – less than 0.4ps/mVpp. Since the

noise sensitivity at lower frequencies, especially around 10MHz, is much higher, the

PDN design has to minimize self-induced noise as well as noise coupling at these

lower frequencies.

Assigning a noise budget of ±2% Vnom (i.e. 36mVpp) to VDDP results into a worst-

case PSIJ contribution of 15ps or 2.4% UI at 1600Mbps data rate, which is acceptable.

For VDDA, the considerations are very similar to the VDDP case. Again, self-induced

noise is expected at high data-rate frequencies, where sensitivity is low. Noise can be

coupled into VDDA at lower frequencies, causing additional PSIJ. The PSIJ

sensitivity to VDDA noise is constant at 0.25ps/mVpp for these lower frequencies.

Assigning a noise budget of ±2% Vnom (i.e. 36mVpp) to VDDA results into a worst-

case PSIJ contribution of 9ps or 1.4% UI at 1600Mbps data rate, which is acceptable.

There is significant PSIJ sensitivity of the clock path to VDDR noise. In general, self-

induced VDDR noise is more difficult to control, as different activity pattern in the

circuits can excite noise at different frequencies, in particular it can excite the

package/chip resonance of the supply network. It is therefore difficult to restrict this

noise to less than ±2% Vnom , and this worst-case noise will likely occur around the

package/chip resonance frequency of 50…200MHz. In this frequency range the PSIJ

sensitivity to VDDR noise is approximately 0.32ps/mVpp, resulting in a PSIJ

contribution of 23ps or 3.7% UI at 1600Mbps data rate.

In summary, supply noise can add up to 47ps (or 7.5% UI at 1600Mbps data rate) of PSIJ

to the clock signal path. This jitter has to be accounted for in the system-level VT budget

of the interface. Half of this PSIJ is originating from VDDR noise. This emphasizes the

need to optimize VDDR supply noise in the interface.

For VDDP and VDDA, PSIJ is primarily caused by noise coupling from other supply

rails. Therefore, noise coupling into these supply rails has to be thoroughly analyzed and

carefully optimized.

III.2. Supply System Design Implementation

III.2.1. Self-Induced Noise on Internal Supplies

After defining supply noise targets for all internal supply, the power supply system for

these rails can be designed. A common approach for this design step is using the ‘Target

Impedance’ concept:

The ‘Target Impedance’ concept works well for systems that can oscillate between two

extreme power states, high current and low current, at a wide frequency range including

the frequency of the package/chip resonance. The ‘Target Impedance’ concepts is

inherently pessimistic if circuit currents always have a broad spectrum, i.e. if there is no

single-tone current excitation of the power distribution system. Since the PDN design of

our OHY is already challenging due to the high inductance of wirebond packages, we

will avoid the pessimism of the ‘Target Impedance’ approach and instead design the PDN

of internal supply rails using a supply noise simulation using extracted current profiles

and a full model of the power distribution system. Figure 8 shows the schematic of these

noise simulations.

Figure 8: Supply Noise Simulation Model for PDN Design

As shown in Figure 8, the PDN is modeled in three components. The PCB component

consists of a VRM model and models for low-frequency (bulk) capacitors as well as

high-frequency PCB capacitors. The electrical parameters (RHF, LHF, CHF) of the high-

frequency capacitors is dependent on the type, number, and placement of capacitors on

the system board. The model assumptions in this simulation reflect the decoupling

requirements specified in the System Design Guide of the interface PHY.

The package component of the PDN model initially consists of simple inductance

models, representing the total package inductance. This model is later replaced with an

extracted package model accurately reflecting the inductance contributions of bond wires,

package traces, vias, and pins, verifying the physical package implementation.

The on-chip model reflects the resistance of the power grid, on-chip decoupling

capacitors, and the impedance feedback of circuits connected to the supply rail.

This PDN model is excited using current waveforms for each supply rail extracted from

circuit simulations. In these simulations, a sequence of activities is simulated that is likely

triggering worst-case noise on every supply rail. This sequence consists of a low-power

state, when the interface stops transmitting, and a high-power state, when the system is

transmitting a PRBS pattern. In the simulation the system is changing between these two

states with the frequency of the package/chip resonance, exciting the resonance of the

supply system. Figure 9 shows the simulated current waveforms for this sequence for all

internal supply rails ([2]).

Figure 9: Simulated Current waveforms on Internal Supplies ([2])

Using the supply noise simulation setup, the amount of on-chip decaps, the package

inductance, and the amount and type of PCB decaps is varied until the noise targets on all

supply rails are met. Figure 10 shows the self-induced supply noise on each rail after this

optimization ([2]). We can see that all internal rails are easily meeting their supply

targets. However, this simulation so far does only account for the self-induced noise on

each supply rail. Noise coupling between rails will have to be analyzed later.

Figure 10: Self-Induced Supply Noise on Internal Supply Rails ([2])

III.2.2. SSO Noise on Output Driver Supply

Simultaneous Switching Outputs (SSO) is a well-known cause source of supply noise and

margin loss in single-ended signaling systems. Output drivers, designed to drive large

off-chip loads, create significant current changes when switching. If many or all of the

output drivers are switching simultaneously, supply noise is generated on the output

driver supply that will cause timing jitter as well as voltage distortions to the output

signal, reducing system margin.

Similar to the discussion of noise on internal supply rails, the noise amplitude on the

output driver supply is not a good measure for the quality of the supply system for an

interface. More important than the amplitude on the supply rail is the impact of this noise

on system margin. Therefore, the design of the PDN for the output drivers should be

based on an analysis how sensitive the margin in the interface reacts to this supply noise.

For this reason, the PDN design for the output driver supply is based on a SI/PI co-

simulation of the interface during SSO events. Figure 12 shows the schematic of the SI/PI

co-simulation model. A detailed discussion of the modeling methodology can be found in

[8].

Figure 12: Scheamtic of SI/PI Co-Simulation Model

A major challenge for a SI/PI co-simulation analysis of SSO noise is managing the

complexity of the simulation model. Ideally, transistor-level driver and receiver models

are used to excite accurate current in the model and correctly model the impact of supply

noise on the driver and receiver circuits. This is possible for a small number of signal

traces. However, a supply noise simulation requires that the currents of all drivers are

accounted for. A solution is the use of Current Controlled Current Sources (CCCS) to

mirror identical currents in the model. In this approach, a smaller number of signal traces

is modeled in full detail, including transistor-level models of the driver and receiver

circuits. The current waveforms generated by these detailed traces can be measured, and

other traces sharing the same data pattern as the detailed traces are replaced with CCCS

modules that mirror the currents of the detailed traces. This makes sure that all currents in

the system are accounted for with only a small number of detailed models that generate

accurate current excitations and noise responses. Figure 13 shows the resulting simulation

deck used for the SI/PI co-simulation. A detailed discussion of this concept can be found

in [9] and [10].

Figure 13: SI/PI Co-Simualtion Deck using CCCS Macros for Current Mirroring

In order to estimate worst-case margin loss due to SSO, we first have to identify the data

pattern causing this worst-case margin loss. Finding this data pattern is not a trivial. In

previous work methods were presented to identify the data pattern generating worst-case

supply noise on the VDDIO supply rail (e.g. [8]). In principle, worst-case supply noise is

generated when the current changes of the data pattern excite the package-chip resonance

of the supply system. But for a DDR3 system in a wirebond package the relevant

resonance loop is not entirely clear, as shown in Figure 14 (from [8]).

Figure 14: Supply Current Loops in DDR3 Package

Traditionally, package-chip resonance analysis is based on the ZPDN loop marked in

green. But this is not the path the signaling current will take during a data transmission.

Instead, Zup and Zdown marked in blue are showing the current loops during pull-up and

pull-down operation of the output driver. Both loops, the ZPDN loop and the Zup/Zdown

loop, usually have slightly different resonance frequencies. In the case of the DDR3

system described in this paper ZPDN had a resonance at 105MHz, while Zup and Zdown had

a resonance at 125MHz. For completeness, we tested the supply noise and system margin

for data pattern exciting either of these resonances, and found that both created almost

identical noise and margin loss.

However, worst-case supply noise does not necessarily lead to worst-case margin loss. In

fact, as we have discussed previously, most signaling paths are tracking jitter in the

output driver at lower and medium frequencies, only high-frequency jitter between paths

is unmatched and will affect the system margin. High-frequency noise is generated by

data pattern with many transitions like PRBS patter. Therefore, we also tested the SSO

supply noise and margin impact of PRBS patters in the system. This analysis showed that

the supply noise was significantly smaller, but contained higher frequency components

and lead to significantly larger margin loss. The table below summarizes the results for

different data patters.

Data pattern Supply noise Margin loss @1600Mbps

PRBS 180mVpp 15% UI

Resonance pattern 240mVpp 12% UI

The VDDIO PDN was optimized to achieve a margin loss of ≤15% UI at a data rate of

1600 Mbps, as already indicated in the table above. The amount of on-chip decaps, the

assignment of bond wires, and the system decoupling requirements were chosen such that

margin loss due to SSO meets this limit, and the worst-case margin loss was used in

balancing the system-level VT budget.

III.2.3. Noise Coupling Between Supply Rails

So far, we have analyzed the self-induced noise on each supply rail. Additionally, noise

can be coupling between different supply rails, increasing the total noise especially on

‘quiet’ supply rails (i.e. VDDA and VDDP) that have very low self-induced noise.

There are two effects in the interface PHY supply system that can cause rail-to-rail noise

coupling. The first effect is inductive coupling between bond wires. This is a well-

understood effect, and an efficient way to mitigate this coupling is shielding sensitive

supplies with neighboring VSS bond wires. The second effect causing noise coupling

between supply rails is the use of a shared ground (VSS) net.

In order to quantify the noise coupling from the ‘noisy’ supplies VDDIO and VDDr into

the ‘quiet’ supplies VDDP and VDDA, we generated a combined model for all supply

rails, including an extracted model of the wirebond section of the package design. From

this model, we extracted the self-impedance for the two ‘noisy’ supplies as well as the

transfer impedances between one ‘noisy’ supply and the ‘quiet’ supplies. The ratio

between transfer impedance and self-impedance describes the attenuation of the coupled

noise compared to the original self-induced noise on the ‘noisy’ supply.

Figure 15a shows the self- and transfer impedances for VDDIO. Figure 15b shows the

ratio of transfer to self-impedance, which is the noise attenuation for coupling from

VDDIO to the other supply rails. It shows that there is about equal coupling from VDDIO

to both VDDP and VDDA at lower frequencies, but the noise coupling declines quickly

for frequencies above 100MHz. For lower frequency nose, the noise coupling attenuation

is approximately -20dB, at the package-chip resonance of VDDIO, where VDDIO noise

will be maximum, the noise coupling attenuation is approximately -25dB. Taken the

maximum VDDIO noise of 240mVpp at resonance, this translates into a noise coupling of

less than 15mVpp of coupled noise into VDDP and VDDA. This noise, additional to the

self-induced noise, meets the noise targets for both rails. But due to the low self-induced

noise levels on VDDP, noise coupling from VDIO dominated the total noise on this rail.

Figure 15: VDDIO Impedance Profiles to Other Supply Rails

a) Self- and Transfer Impedances b) Noise Coupling Attenuation

In a similar way, the coupling from VDDR to the other rails was analyzed. Figure 16

shows the impedance profiles and noise coupling attenuations.

Figure 15: VDDR Impedance Profiles to Other Supply Rails

a) Self- and Transfer Impedances b) Noise Coupling Attenuation

Noise coupling from VDDR to VDDP and VDDA is smaller than from VDDIO. The

coupling attenuation is consistently approximately -5dB better and the self-induced noise

on VDDR is less than half as expected on VDDIO. Therefore, noise coupling from

VDDR to VDDA and VDDP is a secondary effect and we will focus in the

characterization with measurement data on the noise coupling from VDDIO instead.

IV. Power Supply Characterization

The DDR3 interface PHY was implemented in the TSMC 40G process and a DDR3

memory system was build using this PHY that matches the configuration and system

environment of the target system. This test system was used to characterize the PHY,

verify its performance at the target data rate of 1600Mbps, and also to verify the accuracy

of the system models and margin predictions. The test system was tested successfully at

1600Mbps and even higher data rates.

In order to verify the Power Integrity of the PHY supply system, on-chip supply

measurement circuits were implemented on the test chip that allow the measurement of

the supply noise spectrum on each of the internal supply rails as well as generate

controlled noise on these rails. Details of these measurement circuits can be found in [6]

and [7]. The same measurement structure can also be used to measure the supply

impedance of each supply rail, seen by the circuits on the silicon, as described in [11].

This capability was used to verify the critical supply impedance of VDDIO as well as the

transfer impedances from VDDIO to the ‘quiet’ supply rails VDDA and VDDP.

IV.1. VDDIO Supply Impedance Correlation

Figure 16 shows the measured (dots) and simulated (solid) supply self-impedance and

transfer-impedances for VDDIO.

Figure 16: Self- and Transfer Impedances for VDDIO

For the self-impedance of VDDIO (shown in blue in Figure 16) the measurements (dots)

taken with the on-chip supply measurement circuits correlate very well with the

simulated self-impedance profile (solid blue line) in resonance frequency as well as

impedance amplitude. The supply self- impedance implemented in the test system meets

the design target for this impedance, which is an important prerequisite to meeting the

supply noise target on this ‘noisy’ supply rail.

The transfer impedance from VDDIO to VDDA is shown in green in Figure 16. Again,

we can see that the measured transfer impedance matches very closely the design target,

limiting noise coupling from VDDIO into VDDA to the pre-defined amount.

The measurements of transfer impedance from VDDIO to VDDP, shown in purple in

Figure 16, are almost identical to the transfer impedance to VDDA and slightly higher

than the simulation results. A reason for this discrepancy could be coupling between

package traces, which were not modeled in the supply model since bond wire coupling

was expected to be dominant. Based on the measurement results we expect similar noise

coupling from VDDIO into VDDA and VDDP.

For completion, Figure 16 also shows measurements and simulation results for noise

coupling from VDDIO to VDDR. This noise coupling was not expected to be dominant,

because the transfer impedance is very small, and also because VDDR is a ‘noisy’ supply

itself with a large noise budget. The measurements confirm the low transfer impedance

from VDDIO to VDDR. Measuring a transfer impedance -30dB smaller than the self-

impedance is very challenging, since it requires the measurement of very small noise

signals on the victim supply. Given this limitation, the correlation between measurement

and simulation is good.

IV.2. Supply Noise Measurements

Next, the supply noise spectrum on each supply rail was measured for different activity

profiles, in particular for the cases of package-chip resonance (worst case) and for the

transmission of PRBS data (typical case).

IV.2.1. VDDIO Supply Noise Spectrum

Figure 17 shows the supply noise spectrum on VDDIO for package-chip resonance (00FF

pattern) and for a PRBS pattern.

Figure 17: Supply Noise Spectrum on VDDIO

a) Package-chip resonnace b) PRBS pattern

As expected, exciting the package-chip resonance generates the largest supply noise. The

supply noise generated while transmitting a pattern of FFOO on all 32 data lines was

263mVpp, close to the predicted value of 240mVpp. The noise spectrum itself in this case

consists largely of a single tone close to the package-chip resonance frequency of

100MHz.

For a more typical PRBS pattern, the noise spectrum is broader, showing several spikes

re-shaping the self-impedance profile of this supply rail. In this case, a noise of 180mVpp

was measured, meeting the noise amplitude expected from simulations. The impact of

SSO noise on system margin for 1600Mbps was <15%UI for all pattern and so met the

design target.

IV.2.2. VDDR Supply Noise Spectrum

Figure 18 shows the supply noise on VDDR during package-chip resonance.

Figure 18: VDDR Supply Noise Spectrum during Resonance

As discussed previously, VDDR has an impact on the jitter of the differential clock

CK/CK#. The PSIJ sensitivity profile of VDDR for this clock signal is largely constant

over frequency, so a maximum noise target was defined, and maximum noise is

generated during package-chip resonance. The maximum noise on VDDR for this

excitation was 26mVpp, which easily meets the design target for this supply rail.

IV.2.3. VDDA and VDDP Supply Noise Spectrum

Figure 19 shows the supply noise spectrum on the two ‘quiet’ supply rails VDDA and

VDDP while the interface is transmitting a toggle pattern of 5555. This toggle pattern

was chosen to make sure all interface circuits are active, avoiding any noise reduction

due to the gating of inactive circuit parts, but use an activity that only generates high-

frequency noise on VDDIO and VDDR, which will not couple into VDDA and VDDP.

Figure 19, therefore, shows the spectrum of self-induced noise on these two supply rails.

As expected, the self-induced noise on these supply rails is very small, only 14mVpp on

VDDA and 9mVpp on VDDP. It also has very selective frequency content. For VDDA,

noise is primarily generated at the frequency of the internal bit-rate clock. On VDDP, the

dominant spectral noise contributions are at the frequency of the external reference clock.

Figure 19: Spectrum of Self-Induced Noise on ‘Quiet’ Supplies

a) VDDA b) VDDP

Figure 20 shows the supply noise spectrum on VDDA and VDDP while the interface is

transmitting a PRBS data pattern. Comparing Figures 19, Figure 20 shows a dramatic

change in noise spectrum. During PRBS transmission significant noise is visible on

VDDA and VDDP in the mid-frequency range where VDDIO noise also has large

spectral contributions (see Figure 17) and the transfer impedance from VDDIO to VDDA

and VDDP are large (see Figure 16).

Figure 20: Spectrum of Supply Noise on ‘Quiet’ Supplies during PRBS Transmission

a) VDDA b) VDDP

During PRBS transmission, the supply noise on VDDA and VDDP increases to 27mVpp,

significantly larger than the self-induced noise on these two rails (14mVpp and 9mVpp

respectively). For data pattern exciting package-chip resonance on the VDDIO supply,

noise up to 35mVpp was measured on VDDA and VDDP. This shows that in this PHY

design, using a wirebond package for low system cost, supply noise on these sensitive

supply rails is dominated by noise coupling from the output driver supply during SSO

events.

V. Summary

In this paper, we presented the design, implementation, and characterization of the power

supply system for a DDR3 interface PHY operating at 1600Mbps in a low-cost wirebond

package. First, we presented design considerations during the architectural phase of the

PHY design, defining a supply strategy and analyzing supply noise challenges. Power

supply noise was identified as one of the performance limiters in this design, due to the

inherently large inductance of the wirebond package. The design therefore used a supply

partitioning that allowed a separate optimization of self-induced noise and noise coupling

for different circuit groups.

After this, we analyzed the critical timing requirements in the DDR3 interface and

identified requirements. Based on this analysis requirements for supply noise and Power

Supply Induced Jitter were defined for the different supply rails. This made sure that

critical requirements were identified and quantified, and avoiding over-constraining the

supply design in areas of low noise sensitivity.

Next, we presented the analysis steps during the implementation of the power supply

system for the interface PHY. First, we analyzed the noise sensitivity of all critical timing

relationships in the interface to define targets for the noise spectrum on each supply rail.

Next, we identified decoupling and package design requirements to meet these noise

targets based on a system-level supply model and circuit current profiles extracted from

PHY simulations. We analyzed self-induced supply noise as well as noise coupling

between supply rails and identified PDN design solutions that will meet the total noise

target for each rail.

Finally, we used a test implementation of the DDR3 PHY to verify the PDN design and

power integrity of the design. We measured the major self- and transfer impedances of

the supply system and verified that the PDN meets the predictions and requirements of

the system-level supply model used for the PDN design implementation. We also

measured noise levels under different excitation conditions, making sure that the design

meets the power integrity targets under all operating conditions including typical data

transfer (PRBS pattern) as well as package-chip resonance.

The supply analysis during the PDN implementation predicted that noise coupling from

the output driver supply will dominate the supply noise on the sensitive supplies for PLL

and clock distribution (VDDA and VDDP). The measurements on the test system

confirmed this prediction, and have shown that the control of noise coupling in wirebond

packages is essential for the design of a high-speed interface in these low-cost system

environments.

VI. References

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Interface Co-design Approach,” DesignCon, 2011, Jan. 31-Feb. 3, Santa Clara, CA

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