Quick Start Guide MAXIM001 MGT Module for Xilinx ... · MAXIM001 MGT Module for Xilinx UltraScale...

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Quick Start Guide MAXIM001 MGT Module for Xilinx UltraScale KCU1250 and VCU1287 Evaluation Boards AN6055: Quick Start Guide Rev 1 1 MAXIM001 MGT Module The MAXIM001 MGT Module is a proven application circuit design that provides the MGTAVCCAUX, MGTAVCC, and MGTAVTT rails for Xilinx’s Ultra- ScaleVirtex® FPGA multigigibit transceivers. It contains the connectors that allow it to mate directly to the Xilinx KCU1250 MGT characterization- evaluation kit. This solution allows the user to evaluate the MGT performance. The power supplies are designed to meet the stringent power requirements necessary to ensure high-quality, high- speed communication over the MGT rails. The MAXIM001 MGT module power supplies comprise a MAX20751 DC-DC controller integrated circuit (IC) and a VT1697SB smart slave. UltraScale is a trademark and Virtex is a registered trademark of Xilinx, Inc. Features Meets Xilinx MGT Power Requirements < 10mV Output Voltage Ripple MGTAVCC: 1.0V MGTAVTT: 1.2V MGTVCCAUX: 1.8V 8.5V to 16V Input Voltage Supports High Power MGT Rails 20A Output Current Capability per Phase No Heat Sink Required Easy to Set Up and Use No Configuration File Needed Pin-Strap Configuration PMBus Control and Telemetry SMA Connectors for Low-Noise Measurements Connectors for Multiple-Rail Evaluation PMBus Interface for Control and Monitoring

Transcript of Quick Start Guide MAXIM001 MGT Module for Xilinx ... · MAXIM001 MGT Module for Xilinx UltraScale...

Page 1: Quick Start Guide MAXIM001 MGT Module for Xilinx ... · MAXIM001 MGT Module for Xilinx UltraScale KCU1250 and VCU1287 Evaluation Boards AN6055: Quick Start Guide Rev 1 1 MAXIM001

Quick Start Guide

MAXIM001 MGT Module

for Xilinx UltraScale KCU1250 and VCU1287 Evaluation Boards

AN6055: Quick Start Guide Rev 1 1

MAXIM001 MGT Module

The MAXIM001 MGT Module is a proven application

circuit design that provides the MGTAVCCAUX,

MGTAVCC, and MGTAVTT rails for Xilinx’s Ultra-

Scale™ Virtex® FPGA multigigibit transceivers. It

contains the connectors that allow it to mate directly

to the Xilinx KCU1250 MGT characterization-

evaluation kit. This solution allows the user to

evaluate the MGT performance. The power supplies

are designed to meet the stringent power

requirements necessary to ensure high-quality, high-

speed communication over the MGT rails. The

MAXIM001 MGT module power supplies comprise

a MAX20751 DC-DC controller integrated circuit (IC)

and a VT1697SB smart slave.

UltraScale is a trademark and Virtex is a registered trademark of

Xilinx, Inc.

Features

Meets Xilinx MGT Power Requirements

< 10mV Output Voltage Ripple

MGTAVCC: 1.0V

MGTAVTT: 1.2V

MGTVCCAUX: 1.8V

8.5V to 16V Input Voltage

Supports High Power MGT Rails

20A Output Current Capability per Phase

No Heat Sink Required

Easy to Set Up and Use

No Configuration File Needed

Pin-Strap Configuration

PMBus Control and Telemetry

SMA Connectors for Low-Noise Measurements

Connectors for Multiple-Rail Evaluation

PMBus Interface for Control and Monitoring

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Input Voltage The MAXIM001 is designed to operate with an input voltage between 8.5V and 16V.

Design Requirements The main power supply requirement for powering MGT rails is a total output voltage ripple less than 10mV. All

three power rails meet the 10mV requirement with an all ceramic output voltage filter. The load transient

requirement of ±3% is achieved. The Xilinx MGT configuration and layout require the MGT Module output

capacitors to be placed on the MGT module rather than near the load on the Xilinx characterization board.

Although this MAXIM001 design meets all MGT rail power requirements, Maxim recommends placing the output

capacitors by the actual load in a customer production design. Doing this improves both output voltage ripple and

load transient response.

Output Voltages Table 1 shows the preprogrammed output voltages. The output voltages are preset to match the MGT rail

requirements. Note that the 1.8V rail reports an output voltage of 1.5V through the PMBus even though the actual

output voltage is 1.8V. This is normal and is a result of an external voltage divider in the feedback path of this

voltage rail. The actual output voltage is 1.2x the voltage reported through the PMBus.

Table 1. Output Voltages

MGT RAIL VOLTAGE (V) CURRENT (A)

MGTAVCC 1.0 17

MGTAVTT 1.2 10

MGTAVCCAUX 1.8 4

SMBus Slave Address Each voltage rail is preconfigured to allow the user to easily select one of two possible PMBus slave addresses.

The ICs power up at the default slave address without user intervention. The user can select the alternate slave

address by grounding the ALT address pin. Refer to the MAX20751 data sheet for more details on setting the IC’s

address. Table 2 shows the SMBus address settings. If changing the default addresses, ensure that each device

on the bus has a different address.

Table 2. SMBus Address Settings

MGT RAIL DEFAULT

SMBus ADDRESS

ALTERNATE SMBus

ADDRESS

MGTAVCC 0x71 0x70

MGTAVTT 0x73 0x77

MGTAVCCAUX 0x72 0x76

PMBus Telemetry The MGT Module reports VIN, VOUT, TEMP, IOUT, and POUT through the PMBus. The VOUT reporting

accuracy is 1%, the current reporting accuracy is ±4%

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Hardware Connections The MGT Module contains two connectors that make it compatible with the Xilinx Vertex board. The two boards

mate by simply aligning the connectors and gently pressing the boards together. Ensure that no power is

applied when mating the connectors.

Figure 1. Top View of MAXIM001 MGT Module with Three Single-Phase MAX20751s

Figure 2. Bottom View of MAXIM001 MGT Module

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Measured MGT Module Performance

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Ordering Information

PART QTY DESCRIPTION

MAXPOWERTOOL002# 1 PowerTool USB-PMBus Interface

Revision History

REVISION DATE DESCRIPTION PAGES CHANGED

0 7/15 Initial release —

1 10/15 Added VCU1287 1