Xilinx RPT054 Virtex-4 RocketIO MGT Characterization Report...Virtex-4 RocketIO MGT Characterization...

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Virtex-4 RocketIO MGT Characterization Report

RPT054 (v2.0) January 23, 2007

Virtex-4 RocketIO MGT Characterization Report www.xilinx.com RPT054 (v2.0) January 23, 2007

Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2006–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

Revision HistoryThe following table shows the revision history for this document.

Date Version Revision

09/29/06 1.0 Initial Xilinx release.

01/23/07 2.0 Expanded to include characterization at 4.25, 5.0, and 6.5 Gb/s.

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http://www.xilinx.com

Virtex-4 RocketIO MGT Characterization Report www.xilinx.com 3RPT054 (v2.0) January 23, 2007

Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 1: IntroductionXilinx Virtex-4 FX FPGA Family Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17RocketIO MGT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Scope of Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Test Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Characterization Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21PMA Characterization: Agilent 93K Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Chapter 2: PMA Transmitter CharacterizationTransmitter Output Eye and Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Output Eye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Jitter Generation Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MGT Operating Mode/Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Test Equipment and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37TX Total Jitter in PLL DIV 10 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37TX Total Jitter in PLL DIV 20 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Jitter Generation at 2.488 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Board Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Jitter Generation Data (Plots), Histograms (Jrms, Jp-p). . . . . . . . . . . . . . . . . . . . . . . . . . . 48Jitter Generation Data Graphs (Jrms vs. Voltage, Jrms vs. Temperature) . . . . . . . . . . . . . 49Jitter Generation Data Graphs (Jp-p vs. Voltage, Jp-p vs. Temperature). . . . . . . . . . . . . . 502.488 Gb/s Jitter Generation Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Transmitter Jitter Transfer (ATE Measurement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Lab Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table of Contents


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Test Equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Tx Jitter Transfer for 2.5 GHz, 3.125 GHz, and 4.25 GHz VCO Frequency . . . . . . . . . . . 51Data Distribution/ Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54TX Jitter Transfer Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Transmitter Output Rise and Fall Time (ATE Measurement) . . . . . . . . . . . . . . . . . 57

Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Test Equipment and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Single-Ended Rise and Fall Times at 2.5 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Differential Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Data Distribution/ Comparison/ Summary of Single-Ended Measurements . . . . . . . . 59

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Transmitter Output Amplitude (ATE Measurement) . . . . . . . . . . . . . . . . . . . . . . . . . 59

Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Test Equipment and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60TX Amplitude Test Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Transmitter Pre-emphasis and Amplitude with DAC Settings(ATE Measurement). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Test Equipment and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64TX Amplitude with TXDAT_TAP_DAC Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64TX Pre-emphasis with TXPRE_TAP_DAC Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Chapter 3: PMA Receiver CharacterizationReceiver Jitter Tolerance and Input Eye . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Receiver Sinusoidal Jitter Tolerance (Lab Bench Measurement) . . . . . . . . . . . . . . . . . 69Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Receiver Sinusoidal Jitter Tolerance (ATE Measurement) . . . . . . . . . . . . . . . . . . . . . . . 75Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Test Equipment and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Receiver Stressed-Eye Jitter Tolerance (ATE Measurement) . . . . . . . . . . . . . . . . . . . . . 84Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Receiver Input Sensitivity (ATE Measurement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Test Equipment and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Receiver Lock Range and MGTCLK Frequency Tolerance. . . . . . . . . . . . . . . . . . . . 93Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Board Setup and Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94



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Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Receiver Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Receiver Linear Equalizer (Lab Bench Measurement) . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Test Equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Lab Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Board Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101



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Chapter 1: IntroductionFigure 1-1: Virtex-4 RocketIO MGT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 1-2: ML421 Platform - MGT Characterization Board . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 1-3: ML423 Platform - MGT Characterization Board . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 1-4: Quad Serial Loopback Board with Varying Trace Lengths . . . . . . . . . . . . . . . 24Figure 1-5: NQSL Hybrid Board with Varying Trace Lengths . . . . . . . . . . . . . . . . . . . . . . 25Figure 1-6: Agilent 93K-XP Tester Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 1-7: Agilent 93K-XP (ParBERT) ATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 1-8: Agilent 93K-XP (ParBERT) ATE Loadboard/Thermal System . . . . . . . . . . . . 28

Chapter 2: PMA Transmitter CharacterizationFigure 2-1: Representative TX Output Eye at 622 Mb/s in PLL DIV10 Mode . . . . . . . . . 30Figure 2-2: Representative TX Output Eye at 622 Mb/s in PLL DIV16 Mode . . . . . . . . . 30Figure 2-3: Representative TX Output Eye at 1.25 Gb/s (Analog Receiver Mode)

in PLL DIV10 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 2-4: Representative TX Output Eye at 1.25 Gb/s (Analog Receiver Mode)

in PLL DIV20 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 2-5: TX Output Eye at 2.5 Gb/s in PLL DIV10 Mode . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 2-6: TX Output Eye at 2.5 Gb/s in PLL DIV20 Mode . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 2-7: TX Output Eye at 3.125 Gb/s in DIV10 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 2-8: TX Output Eye at 3.125 Gb/s in DIV20 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 2-9: TX Output Eye at 4.25 Gb/s in DIV10 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 2-10: TX Output Eye at 4.25 Gb/s in DIV20 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 2-11: TX Output Eye at 5.0 Gb/s in DIV10 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 2-12: TX Output Eye at 6.5 Gb/s in DIV10 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 2-13: TJ Distribution at 622 Mb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . 37Figure 2-14: RJ Distribution at 622 Mb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . 37Figure 2-15: DJ Distribution at 622 Mb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . 37Figure 2-16: TJ Distribution at 1.25 Gb/s DIV 10: 0°C, 85°C;

1.2V±5%; All Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 2-17: RJ Distribution at 1.25 Gb/s DIV 10: 0°C, 85°C;

1.2V±5%; All Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 2-18: DJ Distribution at 1.25 Gb/s DIV 10: 0°C, 85°C;

1.2V±5%; All Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 2-19: TJ Distribution at 2.5 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . . 39Figure 2-20: RJ Distribution at 2.5 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . . 39Figure 2-21: DJ Distribution at 2.5 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . . 39Figure 2-22: TJ Distribution at 3.125 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . 40Figure 2-23: RJ Distribution at 3.125 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . 40

Schedule of Figures



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Figure 2-24: DJ Distribution at 3.125 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . 40Figure 2-25: TJ Distribution at 4.25 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . 41Figure 2-26: RJ Distribution at 4.25 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . 41Figure 2-27: DJ Distribution at 4.25 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . 41Figure 2-28: TJ Distribution at 5.0 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . . 42Figure 2-29: RJ Distribution at 5.0 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . . 42Figure 2-30: DJ Distribution at 5.0 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . . 42Figure 2-31: TJ Distribution at 6.5 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . . 43Figure 2-32: RJ Distribution at 6.5 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . . 43Figure 2-33: DJ Distribution at 6.5 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units . . . . . . . 43Figure 2-34: Hardware Setup for 2.488 Gb/s Jitter Generation Test . . . . . . . . . . . . . . . . . . 47Figure 2-35: Histogram, 2.488 Gb/s RMS Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Figure 2-36: Histogram, 2.488 Gb/s Peak-to-Peak Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Figure 2-37: 2.488 Gb/s RMS Jitter Generation vs. AVCCAUXTX at 0°C and 100°C . . . 49Figure 2-38: 2.488 Gb/s RMS Jitter Generation vs. Temperature at 1.14V and 1.26V . . . 49Figure 2-39: 2.488 Gb/s P-P Jitter Generation vs. AVCCAUXTX at 0°C and 100°C . . . . . 50Figure 2-40: 2.488 Gb/s P-P Jitter Generation vs. Temperature at 1.14V and 1.26V . . . . . 50Figure 2-41: 2.5 Gb/s Jitter Transfer, 10X Dividers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 2-42: 2.5 Gb/s Jitter Transfer, 20X Dividers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 2-43: 3.125 Gb/s Jitter Transfer, 10X Dividers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 2-44: 3.125 Gb/s Jitter Transfer, 20X Dividers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 2-45: 2.5 GHz VCO Transfer Jitter at 0°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 2-46: 2.5 GHz VCO Transfer Jitter at 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 2-47: 3.125 GHz VCO Transfer Jitter at 0°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 2-48: 3.125 GHz VCO Transfer Jitter at 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 2-49: 4.25 GHz Transfer Jitter at 0°C/85°C at Vmin and Vmax . . . . . . . . . . . . . . . . . 55Figure 2-50: 4.25 GHz Transfer Jitter at 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 2-51: Rise Time (20%–80%) Distribution, All Units, All Test Corners . . . . . . . . . 58Figure 2-52: Fall Time (20%–80%) Distribution, All Units, All Test Corners. . . . . . . . . . 58Figure 2-53: Distribution of TX Differential Output Amplitudes, 2.5 Gb/s . . . . . . . . . . . 60Figure 2-54: TX Differential Output Amplitudes at 3.125Gb/s, All Units. . . . . . . . . . . . . 60Figure 2-55: TX Diff. Output Amplitudes at 3.125Gb/s & 6.5 Gb/s, DAC=8. . . . . . . . . . . 61Figure 2-56: TX Diff. Output Amplitudes at 3.125Gb/s & 6.5 Gb/s, DAC=16. . . . . . . . . . 61Figure 2-57: TX Diff. Output Amplitudes vs DAC Setting at 3.125Gb/s & 6.5 Gb/s . . . . 61Figure 2-58: TX Differential Output Amplitude over Data Rates. . . . . . . . . . . . . . . . . . . . 63Figure 2-59: Single-Ended TX Output vs TXDAT_TAP_DAC, VTTX=1.5V . . . . . . . . . . 64Figure 2-60: Single-Ended TX Output vs TXDAT_TAP_DAC, VTTX=1.14V . . . . . . . . . 65Figure 2-61: Temperature and Voltage Coefficients for Single-Ended TX Outputs . . . . 65Figure 2-62: Effects of Pre-driver On (Blue) and Post-driver On (Yellow) . . . . . . . . . . . . 66Figure 2-63: Effects of TXPRE_TAP and TXPOST_TAP/TXPRE_TAP On . . . . . . . . . . . . 66Figure 2-64: De-emphasis vs TXPRE_TAP_DAC Setting, VTTX=1.5V . . . . . . . . . . . . . . . 67Figure 2-65: De-emphasis vs TXPRE_TAP_DAC Setting, VTTX = 1.14V . . . . . . . . . . . . . 68



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Chapter 3: PMA Receiver CharacterizationFigure 3-1: Test Setup for RX Characterization with N1015A Modulation Test Set . . . . 70Figure 3-2: Minimum Jitter Tolerance at 1.25 Gb/s, PRBS-7 . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 3-3: Sinusoidal Jitter Tolerance at 1.25 Gb/s, PRBS-7 . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 3-4: Minimum Jitter Tolerance at 1.25 Gb/s, PRBS-31 . . . . . . . . . . . . . . . . . . . . . . . 72Figure 3-5: Sinusoidal Jitter Tolerance at 1.25 Gb/s, PRBS-31 . . . . . . . . . . . . . . . . . . . . . . . 72Figure 3-6: Minimum Jitter Tolerance at 622 Mb/s, PRBS-31 . . . . . . . . . . . . . . . . . . . . . . . 73Figure 3-7: Minimum Jitter Tolerance at 622 Mb/s, PRBS-7 . . . . . . . . . . . . . . . . . . . . . . . . 73Figure 3-8: Sinusoidal Jitter Tolerance at 622 Mb/s, PRBS-31 . . . . . . . . . . . . . . . . . . . . . . . 74Figure 3-9: Sinusoidal Jitter Tolerance at 622 Mb/s, PRBS-7 . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 3-10: RX Jitter Tolerance Sweep, 1.26V 0°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 3-11: RX Jitter Tolerance Sweep, 1.26V 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 3-12: 2.5 Gb/s Jitter Tolerance, 20 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 3-13: 2.5 Gb/s Jitter Tolerance, 80 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . . . 77Figure 3-14: 3.125 Gb/s Jitter Tolerance, 20 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . 77Figure 3-15: 3.125 Gb/s Jitter Tolerance, 80 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . 77Figure 3-16: 4.25 Gb/s Jitter Tolerance, 20 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . . 78Figure 3-17: 4.25 Gb/s Jitter Tolerance, 80 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . . 78Figure 3-18: 5.0 Gb/s Jitter Tolerance, 20 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 3-19: 5.0 Gb/s Jitter Tolerance, 80 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 3-20: 6.5 Gb/s Jitter Tolerance, 20 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 3-21: 6.5 Gb/s Jitter Tolerance, 80 MHz Modulation. . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 3-22: Jitter Tolerance Variation with Voltage, 2.5 Gb/s . . . . . . . . . . . . . . . . . . . . . . 81Figure 3-23: Jitter Tolerance Variation with Voltage, 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . 81Figure 3-24: Jitter Tolerance Variation with Temperature, 2.5 Gb/s . . . . . . . . . . . . . . . . . 82Figure 3-25: Jitter Tolerance Variation with Temperature, 3.125 Gb/s . . . . . . . . . . . . . . . 82Figure 3-26: Stressed Eye at 2.5 Gb/s, PRBS-7, DJ from ISI 0.45 UI . . . . . . . . . . . . . . . . . . 85Figure 3-27: Stressed Eye at 1.25 Gb/s, PRBS-31, DJ from ISI 0.39 UI . . . . . . . . . . . . . . . . 85Figure 3-28: Stressed Eye, Additional SJ Injection to Produce TJ = 0.6 UI . . . . . . . . . . . . 86Figure 3-29: Stressed Eye, TJ Measured by BTC on Data 8 = 0.39 UI . . . . . . . . . . . . . . . . . 86Figure 3-30: Stressed-Eye Sinusoidal Jitter Tolerance, 3.125 Gb/s, ISI = 0.41 UI . . . . . . . 87Figure 3-31: Stressed-Eye Sinusoidal Jitter Tolerance, 2.5 Gb/s, ISI = 0.25 UI . . . . . . . . . 87Figure 3-32: Stressed-Eye Sinusoidal Jitter Tolerance, 3.125 Gb/s . . . . . . . . . . . . . . . . . . . 88Figure 3-33: Histogram of RX Sensitivity at 2.5 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Figure 3-34: Histogram of RX Sensitivity at 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Figure 3-35: Histogram of RX Sensitivity at 4.25 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Figure 3-36: Histogram of RX Sensitivity at 5.0 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 3-37: Histogram of RX Sensitivity at 6.5 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 3-38: Input Sensitivity As a Function of Data Pattern . . . . . . . . . . . . . . . . . . . . . . . 92Figure 3-39: Minimum Jitter Tolerance vs. Differential Input Amplitude, 2.5 Gb/s . . . 93Figure 3-40: 2.5 Gb/s Frequency Lock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Figure 3-41: 2.5 Gb/s Lock Range at 0°C and 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Figure 3-42: 2.5 Gb/s Lock Range at Vmin and Vmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96



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Figure 3-43: Lab Setup for Equalization Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Figure 3-44: BER vs. RXEQ, 2.5 Gb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Figure 3-45: BER vs. RXEQ, 3.125 Gb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Figure 3-46: BER vs. RXEQ, 4.25 Gb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Figure 3-47: BER vs. RXEQ, 5.0 Gb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Figure 3-48: BER vs. RXEQ, 6.5 Gb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101



Chapter 1: IntroductionTable 1-1: RocketIO MGTs per Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 1-2: Measurement Conditions for PMA Characterization . . . . . . . . . . . . . . . . . . . . . 20Table 1-3: Platforms for PMA Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chapter 2: PMA Transmitter CharacterizationTable 2-1: PLL Divider Modes and Reference Clock Frequencies . . . . . . . . . . . . . . . . . . . 29Table 2-2: Configurations of Various MGT Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Table 2-3: Peak-to-Peak Random Jitter in DIV 10 Mode(1). . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 2-4: Peak-to-Peak Deterministic Jitter in DIV 10 Mode(1) . . . . . . . . . . . . . . . . . . . . . 44Table 2-5: Peak-to-Peak Total Jitter in DIV 10 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 2-6: Peak-to-Peak Random Jitter in DIV 20 Mode(1). . . . . . . . . . . . . . . . . . . . . . . . . . 45Table 2-7: Peak-to-Peak Deterministic Jitter in DIV 20 Mode(1) . . . . . . . . . . . . . . . . . . . . . 45Table 2-8: Peak-to-Peak Total Jitter in DIV 20 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Table 2-9: Clock Connections for 2.488 Gb/s Jitter Generation Test . . . . . . . . . . . . . . . . . 47Table 2-10: 2.488 Gb/s Jitter Generation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 2-11: TX Jitter Transfer Summary, 2.5 GHz VCO Frequency . . . . . . . . . . . . . . . . . . 56Table 2-12: TX Jitter Transfer Summary, 3.125 GHz VCO Frequency . . . . . . . . . . . . . . . . 56Table 2-13: TX Jitter Transfer Summary, 4.25 GHz VCO Frequency . . . . . . . . . . . . . . . . . 56Table 2-14: Differential Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Table 2-15: Single-Ended Rise and Fall Times (20%–80%) . . . . . . . . . . . . . . . . . . . . . . . . . . 59Table 2-16: TX Eye Amplitude Distributions, 2.5 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 2-17: TX Eye Mean Amplitude Temperature and Voltage Coefficients . . . . . . . . . 62Table 2-18: TX Amplitude Mean and Standard Deviation . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Chapter 3: PMA Receiver CharacterizationTable 3-1: SJ Jitter Tolerance, All Temperatures/Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 3-2: Jitter Introduced by Various PCB Trace Lengths at Various Data Rates . . . . 84Table 3-3: Summary of Sinusoidal Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Table 3-4: Input Sensitivity Means and Standard Deviations . . . . . . . . . . . . . . . . . . . . . . . 92Table 3-5: Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 3-6: 2.5 Gb/s Frequency Lock Range Data Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 3-7: Channel Lengths and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Schedule of Tables



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Preface

About This Guide

This characterization report provides design verification and characterization results for Virtex™-4 FX RocketIO™ Multi-Gigabit Transceivers (MGTs) using process, voltage, and temperature (PVT) conditions.

Guide ContentsThis manual contains the following chapters:

• Chapter 1, “Introduction,” introduces the Virtex-4 FX MGT family and discusses the characterization and test configurations.

• Chapter 2, “PMA Transmitter Characterization,” describes the characterization process and results for the PMA transmitter.

• Chapter 3, “PMA Receiver Characterization,” describes the characterization process and results for the PMA receiver.

ReferencesThe following document provides supplementary material useful with this user guide:

• Xilinx Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076)

Additional ResourcesTo find additional documentation, see the Xilinx website at:

http://www.xilinx.com/literature.

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

http://www.xilinx.comhttp://www.xilinx.com/literaturehttp://www.xilinx.com/supporthttp://www.xilinx.com/bvdocs/userguides/ug076.pdf


Preface: About This GuideR

Definition of Terms

BER Bit Error Rate

BERT Bit Error Rate Tester

ChannelThe high-speed serial signal path, which can include printed circuit board (PCB) material, connectors, cabling, and so on.

CDR Clock and Data Recovery

CRC Cyclical Redundancy Check

CMU Clock Multiplication Unit

DCD Duty Cycle Distortion

DDJ Data Dependent Jitter

DJ Deterministic Jitter – attributable to specific data patterns or events.

DRPDynamic Reconfiguration Port. Used to dynamically modify PMA settings such as data rate or equalization.

FPGA Field Programmable Gate Array

Gb/s Gigabits per Second

I/O Input/Output

ISI Inter Symbol Interference

MGT Multi-Gigabit Transceiver. MGTs are the high-speed serial I/O transceivers.

PJ Periodic Jitter

PMA Physical Media Attachment – also known as the SerDes portion of the transceiver.

PCS Physical Coding Sublayer – digital logic that supports the 8B/10B and 64B/66B encoding/decoding.

PVT Process, Voltage, and Temperature

RJ Random Jitter – attributable to random noise. Random jitter is Gaussian in nature.

RocketIO™ Xilinx brand name for the high-speed serial I/O transceivers. These transceivers are also referred to as MGTs.

RX Receiver

SerDes Serializer/Deserializer. A complete transceiver with RX, TX, CDR, and CMU blocks.

TJ Total Jitter – equal to DJ + RJ.

TX Transmitter



ConventionsR

ConventionsThis document uses the following conventions. An example illustrates each convention.

TypographicalThe following typographical conventions are used in this document:

Convention Meaning or Use Example

Courier fontMessages, prompts, and program files that the system displays

speed grade: - 100

Courier boldLiteral commands that you enter in a syntactical statement

ngdbuild design_name

Helvetica bold

Commands that you select from a menu

File → Open

Keyboard shortcuts Ctrl+C

Italic font

Variables in a syntax statement for which you must supply values

ngdbuild design_name

References to other manualsSee the Development System Reference Guide for more information.

Emphasis in textIf a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

Square brackets [ ]

An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required.

ngdbuild [option_name] design_name

Braces { }A list of items from which you must choose one or more

lowpwr ={on|off}

Vertical bar |Separates items in a list of choices

lowpwr ={on|off}

Vertical ellipsis...

Repetitive material that has been omitted

IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’...

Horizontal ellipsis . . .Repetitive material that has been omitted

allow block block_name loc1 loc2 ... locn;



Preface: About This GuideR

Online DocumentThe following conventions are used in this document:

Convention Meaning or Use Example

Blue textCross-reference link to a location in the current document

See the section “Additional Resources” for details.

Refer to “Title Formats” in Chapter 1 for details.

Red textCross-reference link to a location in another document

See Figure 2-5 in the Virtex-II Platform FPGA User Guide.

Blue, underlined text Hyperlink to a website (URL)Go to http://www.xilinx.com for the latest speed files.



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Chapter 1

Introduction

Xilinx Virtex-4 FX FPGA Family OverviewThe Xilinx Virtex™-4 FX FPGA family (excluding the FX12 device) includes high-performance RocketIO™ Multi-Gigabit Transceivers (MGTs). These RocketIO MGTs enable unprecedented flexibility and creation of high-speed serial links from chip to chip, across backplanes, to optical modules, or from system to system over a “virtual backplane” such as copper cabling. Depending on the device and package, a Virtex-4 FX FPGA has between 8 and 24 RocketIO MGTs, as shown in Table 1-1.

Each MGT operates at multiple serial bit rates in the range of 622 Mb/s to 6.5 Gb/s. This range allows Virtex-4 FX devices to support many existing and emerging serial I/O standards at data rates up to 6.5 Gb/s, including (but not limited to):

• PCI Express

• SONET/SDH OC-12

• XAUI (10 Gigabit Attachment Unit Interface)

• Gigabit Ethernet

• GPON/EPON/BPON

• Serial ATA (SATA)

• OBSAI/CPRI

• OIF CEI-6G

• Aurora (Xilinx open link-layer protocol)

Table 1-1: RocketIO MGTs per Device

Device RocketIO MGT Cores

XC4VFX20 8

XC4VFX40 12

XC4VFX60 12 or 16(1)

XC4VFX100 20

XC4VFX140 24

Notes: 1. Number of MGTs depends on the package.



Chapter 1: IntroductionR

RocketIO MGT OverviewEach RocketIO MGT has a physical media attachment (PMA) block and a physical coding sublayer (PCS) block. Figure 1-1 shows the Virtex-4 RocketIO MGT top-level block diagram and FPGA interface signals. This report focuses on the PMA portion of the MGT.

The PMA contains the serializer/deserializer (SERDES), which includes the TX and RX input/output buffers, clock generator, and clock recovery circuitry. The PMA implements the physical interface portions of the transmitter and receiver. Features of the PMA include:

• Transmit and receive capabilities from 622 Mb/s to 6.5 Gb/s

• Clock and data recovery (CDR)

• Programmable differential output amplitude on the transmit buffer

• Programmable 3-tap pre-emphasis on the transmit buffer

• Support for AC or DC coupling with on-chip AC-coupled receiver (bypass option)

• Local loopback capability

• Channel bonding capability

• Receiver continuous time equalization

• Digital oversampled receiver for data rates up to 1.25 Gb/s

• Receiver signal detect and loss of signal indicator

• Out-of-band signal receiver

• Transmit driver idle state for out-of-band signaling – both outputs at VCM• User reconfiguration using a Dynamic Reconfiguration Port (DRP)

The PCS is pure digital logic and is responsible for implementing protocol coding and the FPGA fabric interface portions of the transmitter and receiver. Features of the PCS include:

• 8B/10B encoding/decoding (1)

• TX FIFO (6 x 40 bits) for clock synchronization(1)

• RX elastic buffer (16 x 52 bits) for clock correction and channel bonding(1)

• Programmable comma detect

• Cyclical Redundancy Check (CRC) logic on TX and RX

• User programmable interface (1, 2, 4, and 8-byte wide) to FPGA fabric

Characterization of the PCS is not included in this report.

1. By-pass option is available.



RocketIO MGT OverviewR

Figure 1-1: Virtex-4 RocketIO MGT Block Diagram

8B/10B Decoder

FPGA FABRIC

FPGA FABRIC

MULTI-GIGABIT TRANSCEIVER CORE

Serializer

RXP

TXP

ClockManager

PACKAGEPINS

DeserializerCommaDetectRealign

TXRing

Buffer

Channel Bondingand

Clock Correction

8B/10BEncoder

RXRing

BufferRXN

GNDA

TXN

ug076_apA_01_092206

VTRX

AVCCAUXRX

VTTX

AVCCAUXTX

1.2V

TX/RX GND

TerminationSupply RX

1.2V

Termination Supply TX

64B/66BDescrambler

64B/66BBlock Sync

64B/66BDecoder

64B/66BEncoder

GearboxScrambler

Pre

-Driv

er L

oopb

ack

Pat

h

Power Down

Clock/Reset

DynamicReconfiguration

Port

FabricInterface

CRC Block

RXCRCCLKRXCRCDATAVALID

RXCRCDATAWIDTH[2:0]RXCRCIN[63:0]

RXCRCINITRXCRCINTCLK

RXCRCOUT[31:0]RXCRCPD

RXCRCRESETTXCRCCLK

TXCRCDATAVALIDTXCRCDATAWIDTH[2:0]

TXCRCIN[63:0]TXCRCINIT

TXCRCINTCLKTXCRCOUT[31:0]

TXCRCPDTXCRCRESET

PLLCalibration

Block

RXCYCLELIMITTXCYCLELIMITRXCLKSTABLE

TXCALFAILTXCLKSTABLE

VCCINT Fabric PowerSupply

RXCALFAIL

CHBONDI[4:0]CHBONDO[4:0]

RXRECCLK1RXRECCLK2RXPCSHCLKOUTRXPOLARITY

RXREALIGNRXCOMMADET

RXLOSSOFSYNC[1:0]

RXDATA[63:0]RXNOTINTABLE[7:0]RXDISPERR[7:0]RXCHARISK[7:0]RXCHARISCOMMA[7:0]RXRUNDISP[7:0]

RXSTATUS[5:0]RXBUFERR

ENCHANSYNC

TXBUFERR

TXDATA[63:0]TXBYPASS8B10B[7:0]TXCHARISK[7:0]TXCHARDISPMODE[7:0]TXCHARDISPVAL[7:0]TXKERR[7:0]TXRUNDISP[7:0]

TXPOLARITYTXLOCK

TXINHIBIT

LOOPBACK[1:0]

ENPCOMMAALIGNENMCOMMAALIGN

RXRESET

RXUSRCLKRXUSRCLK2

TXRESET

REFCLK1REFCLK2

TXUSRCLK

GREFCLK

RXCOMMADETUSE

RXDATAWIDTH[1:0]

RXDESCRAM64B66BUSERXBLOCKSYNC64B66BUSE

RXSLIDE

TXSCRAM64B66BUSE

RXIGNOREBTF

RXINTDATAWIDTH[1:0]TXDATAWIDTH[1:0]

TXENC64B66BUSETXENC8B10BUSETXGEARBOX64B66BUSE

POWERDOWN

RXLOCK

RXDECC64B66BUSERXDEC8B10BUSE

DI[15:0]DADDR[7:0]

DCLKDENDWEDRDYDO[15:0]

TXINTDATAWIDTH[1:0]

TXOUTCLK2TXOUTCLK1/TXPCSHCLKOUTRXPMARESET

TXUSRCLK2TXPMARESET

PC

S P

aral

lel L

oopb

ack




With the built-in channel bonding logic, from 2 to 24 MGTs can be combined for high bandwidth applications.

Additional details on the MGTs are in the Xilinx Virtex-4 RocketIO™ Multi-Gigabit Transceiver User Guide.

Scope of CharacterizationThis document presents electrical characterization data from the Virtex-4 FX RocketIO PMA transmit (TX) and receive (RX) functions.

This report reflects data from FX20 and FX60 Engineering Sample CES4 and CES4S silicon. This report focuses on process, voltage, and temperature (PVT) data and serial data rates up to 6.5 Gb/s.

Except where otherwise noted, measurements were made at “nominal” voltage and temperature conditions (Table 1-2). VCCINT, the voltage supplied to the FPGA logic core and digital PCS block, does not directly affect the performance of the MGTs. VCCAUXTX and VCCAUXRX are the primary supplies for the PMA portion of the MGT. VTTX and VTRX are the termination supplies. Temperature was either nominal at ambient room temperature (uncontrolled) or at worst-case junction temperature (as measured by an on-chip diode current correlated to temperature) and was controlled using a temperature forcing unit.

Test ConfigurationsVerification and characterization were performed using three basic configurations: the ML421, the ML423, and Agilent 93K-XP (HP93000) platforms. Each configuration/setup meets certain special needs in the characterization process. The details of each setup are included in the relevant sections of this document.

Temperature, voltage, and process corner testing were performed using the Agilent 93K-XP (HP93000) characterization platform. Most analog PMA features and parametrics are characterized on the 93K-XP.

Table 1-2: Measurement Conditions for PMA Characterization

Parameter NominalWorst Case

UnitsMin Max

VCCINT 1.2 1.14 - V

AVCCAUXTXAVCCAUXRX 1.2 1.14 1.26 V

AVCCAUXMGT 2.5 2.375 2.625 V

VTTXVTRX

1.5 1.425 1.575 V

Room Temperature ~25 - - °C

Junction Temperature ~50 0 85 °C



Characterization Board SpecificationsR

Characterization Board SpecificationsTable 1-3 summarizes the boards used for the initial electrical verification and characterization of the PMA. These boards were designed to characterize the Virtex-4 RocketIO MGTs (high-speed serial transceivers) and to provide an MGT evaluation and development platform for Xilinx customers. These boards are available for demonstrations in the Xilinx RocketLabs and for customer purchase.

Figure 1-2 and Figure 1-3 show photographs of the boards.

The ML421 and ML423 boards can either accommodate a test socket or allow the FX device to be soldered directly to the board. To accommodate testing of a variety of parts, the boards used for characterization are primarily equipped with sockets. The socket can contribute some performance degradation in the form of attenuation and jitter, although the design of the boards minimizes this effect. Equivalent boards found in the RocketLabs and for customer purchase have the FX device soldered directly to the board (no socket). Reference clock signals are supplied to the MGTs either by the on-board Xilinx Superclock module (programmable clock module) or an external clock source (for example, Agilent 81134 signal generator). Device configuration management features include a JTAG configuration port, System ACE™ module, and CompactFlash™ memory card adaptor. Power to the ML421 and ML423 boards is provided with an AC adapter and on-board regulators, with external power supplies, or with some combination of both. There are two ways to configure the MGT attributes. Static properties are set through attributes in the HDL code. The HDL code is generated using the RocketIO Wizard. Dynamic changes are made to the attributes via the DRP. See UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide, for details on attributes, the RocketIO Wizard, and the DRP.

Table 1-3: Platforms for PMA Characterization

Board Type Virtex-4 Device PackageAvailable RocketIO

(MGTs)

ML421 FX20FX60FF672FF672

812

ML423 FX60 FF1152 16

http://www.xilinx.comhttp://www.xilinx.com/bvdocs/userguides/ug076.pdf



Figure 1-2: ML421 Platform - MGT Characterization Board

RPT023_02_02_090405




To ensure the integrity of the characterization measurements, special attention is given to the signal integrity of the high-speed serial channels. Detailed analysis ensures the board performs as designed. The transmitter (TX) and receiver (RX) signal paths for each MGT are carefully routed to high-bandwidth SMA connectors to ensure good signal integrity and performance. Stripline board traces are routed on internal signal layers with 100Ω differential impedance. Signal attenuation is minimized by employing Nelco 4000-13 board material to minimize the board effects from the device signals being evaluated.

The total board stackup is 16 layers for both the ML421 and ML423. For some measurements, additional lengths of FR4 trace were added to the high-speed serial signals using stripline evaluation boards, as shown in Figure 1-4 and Figure 1-5. The Quad Serial Loopback board shown in Figure 1-4 allows FR4 trace lengths of 10 inches, 15 inches, 20 inches, 30 inches, 40 inches, or combinations of these trace lengths to be added to the signal path or channel. This 6-layer board is 0.062 inches thick and uses 8-mil traces with 12-mil separation, and has a target 100Ω differential impedance.

Figure 1-3: ML423 Platform - MGT Characterization Board

RPT023_03_03_092605




Figure 1-4: Quad Serial Loopback Board with Varying Trace Lengths

RPT023_04_04_091005




The Nelco Quad Serial Loopback (NQSL) board shown in Figure 1-5 is a hybrid board using three different dielectric materials: Nelco 4000-6 (FR4 equivalent), 4000-13, and 4000-13 SI. The board allows trace lengths of 16 inches, 26 inches, 36 inches, or combinations of these trace lengths in each material to be added to the signal path. This 10-layer board is 0.062 inches thick and has a target 100Ω differential impedance. The trace features of the 10-layer board are:

• 7.75 mil trace width with 8.25 mil separation (Layer 3)

• 7.5 mil trace width with 8.5 mil separation (Layer 5)

• 8 mil trace width with 8 mil separation (Layer 8)

Figure 1-5: NQSL Hybrid Board with Varying Trace Lengths

RPT023_01_05_091005




PMA Characterization: Agilent 93K SetupPMA characterization uses an Agilent 93K-XP Automatic Test Equipment (ATE) as shown in Figure 1-6 to Figure 1-8. The system comprises a high-speed SOC test system (93000) with 4-channel 13.5 Gb/s ParBERT (Parallel Bit Error Rate Test) system modules with up to 80 MHz jitter modulation capability.

The 93K-XP ATE is specifically designed to perform almost all the tests required for the MGT PMA, including:

• TX:♦ Jitter evaluation/jitter decomposition using Bathtub method♦ Amplitude measurements

• RX:♦ Input sensitivity♦ Jitter tolerance

The three clock domains sourced from the E8257C and E4422B instruments provide independent synchronous data generation, reference clock, and error detection. All characterization is performed with the MGT in a half-duplex link configuration with fabric loopback.

A single configuration is used for all modes, as shown in Figure 1-6. The configuration provides access to the DRP to allow changes to the attributes without the need to reconfigure. Photographs of the test setup are shown in Figure 1-7 and Figure 1-8.

Figure 1-6: Agilent 93K-XP Tester Setup

33250A

N4872A

N4872A

N4872A

N4872A

E4809A

4-Channel Pattern Generator

N4872A

N4872A

N4872A

N4872A

E4809A

4-Channel Error Detector

E8257CE8257C E4422B

4-ChannelDistribution

Clock Inputs

Clock Input

To 10 MHz

Sync

20 GHz – 40 GHzClock Source

93000 Digital Tester

1 MHz – 80 MHz WaveformGenerator for Jitter Generation

Fabric Loopback

4-ChannelJitter Injection

4 MGTs

TX1

RX1

TX2

RX2

TX3

RX3

TX4

RX4

600 MHz Digital Channels

Power Supplies Channels

For MGT Configuration,PMA Port Function Testing,

PMA Bus Programming

E8257C 40 GHz clock source, for pattern generator and error detectorE4422B 4 GHz clock source for REFCLK1 or REFCLK233250A 80 MHz waveform generator, jitter injectionN4872A 13.5G data generator moduleN4873A 13.5G error detector moduleE4809A 13.5G clock source

4 GhZClock Source

RPT054_01_06_011007



PMA Characterization: Agilent 93K SetupR

Figure 1-7: Agilent 93K-XP (ParBERT) ATE

XP - 4 Channel 13.5 Gb/s ParBERT

High-Speed Test Head HSSI (High-Speed Serial Interconnect) RPT054_01_07_080206




Figure 1-8: Agilent 93K-XP (ParBERT) ATE Loadboard/Thermal System

93K-XPDaughtercard

TemperatureForcing Unit

RPT054_01_08_080206



R

Chapter 2

PMA Transmitter Characterization

Transmitter Output Eye and Jitter Generation

Output Eye DiagramsEye diagrams are commonly used to evaluate the quality of signals at different points along a serial link. In this section, the near-end eye diagrams for different data rates are shown in Figure 2-1 through Figure 2-12.

In this report, the PLL divider modes are specified. The reference clock frequencies corresponding to each data rate and divide ratio are given in Table 2-1.

Table 2-1: PLL Divider Modes and Reference Clock Frequencies

Data RateVCO Freq.

(GHz)

Reference Clock Frequency (MHz)

Div10 Div16 Div20

622 Mb/s 2.488 248.8 155.5

1.25 Gb/s analog 2.5 250 125

1.25 Gb/s digital, 8X over-sample 2.5(1) 250 125

2.5 Gb/s 2.5 250 125

3.125 Gb/s 3.125 312.5 156.25

4.25 Gb/s 4.25 425 212.5

5.0 Gb/s 2.5 250

6.5 Gb/s 3.25 325

Notes: 1. TX VCO frequency = 2.5 GHz; RX VCO frequency = 5 GHz.



Chapter 2: PMA Transmitter CharacterizationR

Figure 2-1: Representative TX Output Eye at 622 Mb/s in PLL DIV10 Mode

Figure 2-2: Representative TX Output Eye at 622 Mb/s in PLL DIV16 Mode

RPT054_02_14_080206

RPT054_02_15_080206



Transmitter Output Eye and Jitter GenerationR

Figure 2-3: Representative TX Output Eye at 1.25 Gb/s (Analog Receiver Mode)in PLL DIV10 Mode

Figure 2-4: Representative TX Output Eye at 1.25 Gb/s (Analog Receiver Mode)in PLL DIV20 Mode

RPT054_02_16_080206

RPT054_02_17_080206




Figure 2-5: TX Output Eye at 2.5 Gb/s in PLL DIV10 Mode

Figure 2-6: TX Output Eye at 2.5 Gb/s in PLL DIV20 Mode

RPT054_02_18_080206

RPT054_02_19_080206




Figure 2-7: TX Output Eye at 3.125 Gb/s in DIV10 Mode


RPT054_02_20_080206

RPT054_02_21_080206






RPT054_02_22_120106

RPT054_02_23_120106






RPT054_02_24_120106

RPT054_02_25_120106




Jitter Generation Test DescriptionThe total jitter (TJ), random jitter (RJ) and deterministic jitter (DJ) of the transmitter output are measured by the Bath Tub Curve (BTC) method. The test measurements for transmit jitter generation are based on a BER of 1E–12. The data pattern used for the lower data rates in Digital CDR mode is PRBS-31. For the analog mode data rates of 1.25 Gb/s, 2.5 Gb/s, 3.125 Gb/s, 4.25 Gb/s, 5.0 Gb/s, and 6.5 Gb/s, the PRBS-7 pattern is used.

MGT Operating Mode/Configuration

Table 2-2 shows the important operating mode and configuration conditions for the MGT.

Test Equipment and Setup

The Low Volume Manufacturer (LVM) 12-channel 93K ParBERT ATE system is used for characterization.

Table 2-2: Configurations of Various MGT Blocks

Block Mode/Configuration

TX Fabric loop back in 40 bit mode. Tx output direct drives the ParBERT error detector

RX ParBERT data generator drives RX inputs with internal AC couple

TX/RX PLL DIV 10, 20, 16




Characterization Data

TX Total Jitter in PLL DIV 10 Mode

TX Jitter 622 Mb/s:

Figure 2-13: TJ Distribution at 622 Mb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units

Figure 2-14: RJ Distribution at 622 Mb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units

Figure 2-15: DJ Distribution at 622 Mb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units

TJ

RPT054_02_01_011007

Virtex-4 FX TJ p622g div10 TJ (All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

TJ (UI)

Num

ber

of M

GT

s

1

10

100

0

0.04

0.08

0.12

0.16

0.20

0.24

0.28

0.32

0.36

0.40

0.44

0.48

0.52

0.56

0.60

0.64

0.68

Mor

e

RJ

RPT054_02_02_011007

Virtex-4 FX RJ p622g div10 RJ (All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

RJ (UI)

Num

ber

of M

GT

s

0

0

20

40

60

80

100

120

140

0.06

0.12

0.18

0.24

0.30

0.36

0.42

0.48

0.54

0.60

0.66

0.72

0.78

0.84

0.90

0.96

Mor

e

DJ

RPT054_02_03_011007

Virtex-4 FX DJ p622g div10 DJ (All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

DJ (UI)

Num

ber

of M

GT

s

0

0

20

40

60

80

100

120

140

0.06

0.12

0.18

0.24

0.30

0.36

0.42

0.48

0.54

0.60

0.66

0.72

0.78

0.84

0.90

0.96

Mor

e




TX Jitter 1.25 Gb/s:

Figure 2-16: TJ Distribution at 1.25 Gb/s DIV 10: 0°C, 85°C;1.2V±5%; All Units

Figure 2-17: RJ Distribution at 1.25 Gb/s DIV 10: 0°C, 85°C;1.2V±5%; All Units

Figure 2-18: DJ Distribution at 1.25 Gb/s DIV 10: 0°C, 85°C;1.2V±5%; All Units

Num

ber

of M

GT

s

TJ

Virtex-4 FX TJ 1p25g div10 TJ (All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

1

10

100

RPT054_02_04_092806 TJ (UI)

0

0.06

0.12

0.18

0.24

0.30

0.36

0.42

0.48

0.54

0.60

0.66

0.72

0.78

0.84

0.90

0.96

Mor

e

RJ

RPT054_02_05_092806

Virtex-4 FX RJ 1p25g div10 RJ (All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

0

0.06

0.12

0.18

0.24

0.30

0.36

0.42

0.48

0.54

0.60

0.66

0.72

0.78

0.84

0.90

0.96

Mor

e

RJ (UI)

Num

ber

of M

GT

s

0

10

20

30

40

50

60

70

80

90

DJ

RPT054_02_06_092806

Virtex-4 FX DJ 1p25g div10 DJ (All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

0

0.06

0.12

0.18

0.24

0.30

0.36

0.42

0.48

0.54

0.60

0.66

0.72

0.78

0.84

0.90

0.96

Mor

e

DJ (UI)

Num

ber

of M

GT

s

0

10

20

30

40

50

60

70

80

90




TX Jitter 2.5 Gb/s:

Figure 2-19: TJ Distribution at 2.5 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units

Figure 2-20: RJ Distribution at 2.5 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units

Figure 2-21: DJ Distribution at 2.5 Gb/s DIV 10: 0°C, 85°C; 1.2V±5%; All Units

TJ

RPT054_02_01_011007

Virtex-4 FX TJ 2p5g div10 TJ (All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

TJ (UI)

Num

ber

of M

GT

s

01

10

100

1000

0.06

0.12

0.18

0.24

0.30

0.36

0.42

0.48

0.54

0.60

0.66

0.72

0.78

0.84

0.90

0.96

Mor

e

RPT054_02_08_071906

Virtex-4 FX RJ 2p5g div10 (All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

RJ (UI)

Nu

mb

er o

f M

GT

s

0

1

10

100

1000

0.04

0.08

0.12

0.16

0.20

0.24

0.28

0.32

0.36

0.40

0.44

0.48

0.52

0.56

0.60

0.64

0.68

Mor

e

RPT054_02_09_083006

Virtex-4 FX DJ 2p5g div10 (All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

DJ (UI)

Nu

mb

er o

f M

GT

s

0

1

10

100

1000

0.06

0.12

0.18

0.24

0.30

0.36

0.42

0.48

0.54

0.60

0.66

0.72

0.78

0.84

0.90

0.96

Mor

e








RPT054_02_10_083006

Virtex-4 FX TJ 3p125g div10 (All units, VCCAUXRX/TX1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

TJ (UI)

Num

ber

of M

GT

s

01

10

100

1000

0.04

0.08

0.12

0.16

0.20

0.24

0.28

0.32

0.36

0.40

0.44

0.48

0.52

0.56

0.60

0.64

0.68

Mor

e

RPT054_02_11_08306

Virtex-4 FX RJ 3p125g div10 (All units, VCCAUXRX/TX1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

RJ (UI)

Num

ber

of M

GT

s

0

1

10

100

1000

0.04

0.08

0.12

0.16

0.20

0.24

0.28

0.32

0.36

0.40

0.44

0.48

0.52

0.56

0.60

0.64

0.68

Mor

e

RPT054_02_12_08306DJ (UI)

Virtex-4 FX DJ 3p125g div10 (All units, VCCAUXRX/TX1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

Num

ber

of M

GT

s

0

1

10

100

1000

0.06

0.12

0.18

0.24

0.30

0.36

0.42

0.48

0.54

0.60

0.66

0.72

0.78

0.84

0.90

0.96

Mor

e








Virtex-4 FX TJ 4p25g div10 Reference Clock 425 MHz(All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

0

10

20

30

40

50

60

70

80

90

100

1

0.93

0.85

0.780.7

0.63

0.55

0.480.4

0.33

0.25

0.180.1

0.02

TJ in UI

Nu

mb

er o

f M

GT

s

RPT054_02_26_120506

RPT054_02_27_120706

0

50

75

25

100

125

150

0

0.08

0.15

0.23 0.3

0.38

0.45

0.53 0.

6

0.68

0.75

0.83 0.9

RJ in UI

Virtex-4 FX RJ 4p25g div10 Reference Clock 425 MHz(All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)

Nu

mb

er o

f M

GT

s

RPT054_02_28_120606

0

10

20

30

40

50

60

70

80

0.00

0.08

0.15

0.23

0.30

0.38

0.45

0.53

0.60

0.68

0.75

0.83

0.90

0.98

DJ in UI

Nu

mb

er o

f M

GT

s

Virtex-4 FX DJ 4p25g div10 Reference Clock 425 MHz(All units, VCCAUXRX/TX 1.14V, 1.2V, 1.26V, Temp = 0°C, 85°C)




TX Jitter 5.0 Gb/s:




RPT054_02_29_120606

Nu

mb

er o

f M

GT

s


0

20

40

60

80

100

120

0

0.05 0.

1

0.15 0.

2

0.25 0.

3

0.35 0.

4

0.45 0.

5

0.55 0.

6

0.65 0.

7

0.75 0.

8

0.85 0.

9

0.95

1

TJ (UI)

RPT054_02_30_120606


0

20

40

60

80

100

120

140

160

180

200

0

0.07

0.15

0.22 0.

3

0.37

0.45

0.53 0.

6

0.68

0.75

0.85

0.93 1

RJ (UI)

Nu

mb

er o

f M

GT

s

RPT054_02_31_120606


0

20

40

60

80

100

120

140

160

180

0

0.05 0.

1

0.15 0.

2

0.25 0.

3

0.35 0.

4

0.45 0.

5

0.55 0.

6

0.65 0.

7

0.75 0.

8

0.85 0.

9

0.95

DJ (UI)

Nu

mb

er o

f M

GT

s




TX Jitter 6.5 Gb/s:




RPT054_02_32_120606


0

50

100

150

200

250

300

1

0.950.

9

0.850.

8

0.750.

7

0.650.

6

0.550.

5

0.450.

4

0.350.

3

0.250.

2

0.150.

1

0.050

TJ in UI

Num

ber o

f MG

Ts

RPT054_02_33_120606


0

50

100

150

200

250

300

350

0

0.08

0.15

0.23 0.3

0.38

0.45

0.53 0.6

0.68

0.75

0.83 0.9

0.98

RJ in UI

Nu

mb

er o

f M

GT

s

RPT054_02_33_120606


0

50

100

150

200

250

300

0

0.08

0.15

0.23 0.3

0.38

0.45

0.53 0.6

0.68

0.75

0.83 0.9

0.98

DJ in UI

Nu

mb

er o

f M

GT

s




Table 2-3: Peak-to-Peak Random Jitter in DIV 10 Mode(1)

Data RatesMean(UI)

Standard Deviation

(UI)

Minimum(UI)

Maximum(UI)

622 Mb/s 0.05 0.005 0.04 0.06

1.25 Gb/s 0.08 0.025 0.06 0.12

2.5 Gb/s 0.11 0.017 0.08 0.18

3.125 Gb/s 0.09 0.013 0.06 0.14

4.25 Gb/s 0.12 0.018 0.08 0.20

5.0 Gb/s 0.19 0.03 0.10 0.30

6.5 Gb/s 0.14 0.03 0.07 0.28

Notes: 1. All values are peak-to-peak random jitter. Corresponding RMS random jitter values can be obtained

by dividing by 14 (corresponding to the projected BER of 1E–12).

Table 2-4: Peak-to-Peak Deterministic Jitter in DIV 10 Mode(1)

Data RatesMean(UI)

Standard Deviation

(UI)

Minimum(UI)

Maximum(UI)

622 Mb/s 0.00(2) 0.019 0.00(2) 0.04

1.25 Gb/s 0.023 0.007 0.02 0.06

2.5 Gb/s 0.056 0.02 0.00(2) 0.12

3.125 Gb/s 0.08 0.03 0.02 0.14

4.25 Gb/s 0.11 0.02 0.06 0.19

5.0 Gb/s 0.16 0.03 0.08 0.38

6.5 Gb/s 0.19 0.03 0.09 0.37

Notes: 1. Measurement resolution = 0.01 UI.2. This value is well within measurement accuracy.

Table 2-5: Peak-to-Peak Total Jitter in DIV 10 Mode

Data RatesMean(UI)

Standard Deviation

(UI)

Minimum(UI)

Maximum(UI)

622 Mb/s 0.05 0.006 0.04 0.06

1.25 Gb/s 0.09 0.01 0.06 0.12

2.5 Gb/s 0.156 0.04 0.04 0.24

3.125 Gb/s 0.16 0.03 0.12 0.30

4.25 Gb/s 0.24 0.03 0.18 0.33

5.0 Gb/s 0.32 0.03 0.24 0.39

6.5 Gb/s 0.33 0.03 0.26 0.41




TX Total Jitter in PLL DIV 20 Mode

Table 2-6: Peak-to-Peak Random Jitter in DIV 20 Mode(1)

Data RatesMean(UI)

Standard Deviation

(UI)

Minimum(UI)

Maximum(UI)

622 Mb/s(2) 0.05 0.017 0.04 0.06

1.25 Gb/s 0.07 0.012 0.04 0.12

2.5 Gb/s 0.13 0.02 0.08 0.2

3.125 Gb/s 0.12 0.022 0.06 0.22

4.25 Gb/s 0.14 0.023 0.08 0.24

Notes: 1. All values are peak-to-peak random jitter. Corresponding RMS random jitter values can be obtained by

dividing by 14 (corresponding to the projected BER of 1E–12).2. 622 Mb/s is Div16 mode.

Table 2-7: Peak-to-Peak Deterministic Jitter in DIV 20 Mode(1)

Data RatesMean(UI)

Standard Deviation

(UI)

Minimum(UI)

Maximum(UI)

622 Mb/s(2) 0.02(3) 0.017 0.00(3) 0.18

1.25 Gb/s 0.087 0.04 0.02 0.16

2.5 Gb/s 0.102 0.07 0.00(3) 0.26

3.125 Gb/s 0.09 0.043 0.00(3) 0.22

4.25 Gb/s 0.13 0.04 0.06 0.19

Notes: 1. Measurement resolution = 0.01 UI.2. 622 Mb/s is Div16 mode.3. This value is well within measurement accuracy.

Table 2-8: Peak-to-Peak Total Jitter in DIV 20 Mode

Data RatesMean(UI)

Standard Deviation

(UI)

Minimum(UI)

Maximum(UI)

622 Mb/s(1) 0.05 0.03 0.02 0.2

1.25 Gb/s 0.11 0.034 .08 0.22

2.5 Gb/s 0.21 0.055 0.14 0.4

3.125 Gb/s 0.21 0.056 0.14 0.34

4.25 Gb/s 0.27 0.03 0.16 0.34

Notes: 1. 622 Mb/s is Div16 mode.




ConclusionThe variation in total jitter is primarily attributed to DJ. The random jitter RJ is quite consistent at different data rates and over temperature and voltages.

Random jitter is extracted from the bath tub curves using the Agilent MUI software. In low data rates below 1 Gb/s, this methodology has large variations due to steep slope of the BTC. Random jitter is obtained from the eye width measurements of 1010 data. Peak to peak random jitter is calculated based on BER of 1E–12.

Deterministic jitter is obtained from subtracting the peak to peak random jitter from the total jitter. DJ has larger distribution due to reference burst in some MGT. In general, DJ as a function of UI is very small at low data rates.



Jitter Generation at 2.488 Gb/sR

Jitter Generation at 2.488 Gb/s

Test DescriptionThe following is the MGT Optical 2.488 Gb/s transmitter output jitter generation and eye characterization test data. The data (PRBS-23) is generated and checked by the Agilent OMNI_BERT. The reference clocks are generated externally (please refer to Figure 2-34). The data pattern used was limited at PRBS-23 due to limitations of the test instrument.

Board Setup

This test was performed on the ML421 board. Clock connections are shown in Table 2-9.

Hardware Setup

The hardware setup is shown in Figure 2-34.

Table 2-9: Clock Connections for 2.488 Gb/s Jitter Generation Test

Data Rate (Gb/s)

PinFrequency

(MHz)Signal Source Note:

2.488 MGTCLK105 311.04 MGTCLK8648D driving

8133A32-bit data

path

MGTCLK110 311.04 MGTCLK8648D driving

8133A

Figure 2-34: Hardware Setup for 2.488 Gb/s Jitter Generation Test

RPT054_03_01_071906





Jitter Generation Data (Plots), Histograms (Jrms, Jp-p)

Figure 2-35 and Figure 2-36 show TX output jitter generation at 2.488 Gb/s. The data is from six parts (two typical, one from each corner lot), two MGTs per part.

Figure 2-35: Histogram, 2.488 Gb/s RMS Jitter

Figure 2-36: Histogram, 2.488 Gb/s Peak-to-Peak Jitter

Cou

nts

14Average (RMS 6.35 mUI) Max (RMS 8 mUI)

Min (RMS 4 mUI)Stdev (RMS 0.88 mUI)12

10

8

6

4

2

0

3.5

mU

I

4.0

mU

I

4.5

mU

I

5.0

m U

I

5.5

mU

I

6.0

mU

I

6.5

mU

I

7.0

mU

I

7.5

mU

I

8.0

mU

I

8.5

mU

I

Mor

e

RPT054_04_01_011007Jitter (rms)

Histogram (2.488 Gb/s, RMS Jitter)2.488 Gb/s Unformatted PRBS23

REFCLK 311.04 Mhz

0

1

2

3

4

5Average (p-p 87 mUI)

Stdev (p-p 7.1 mUI)

Cou

nts

RPT054_04_02_011007

70.0

mU

I

75.0

mU

I

80.0

mU

I

85.0

mU

I

90.0

mU

I

95.0

mU

I

Mor

e

Jitter (p-p)

Histogram (2.488 Gb/s, P-P Jitter)2.488 Gb/s Unformatted PRBS23

REFCLK 311.04 Mhz

Max (p-p 97 mUI)

Min (p-p 74 mUI)



Jitter Generation at 2.488 Gb/sR

Jitter Generation Data Graphs (Jrms vs. Voltage, Jrms vs. Temperature)

Figure 2-37: 2.488 Gb/s RMS Jitter Generation vs. AVCCAUXTX at 0°C and 100°C

Figure 2-38: 2.488 Gb/s RMS Jitter Generation vs. Temperature at 1.14V and 1.26V

Jitte

r (r

ms)

8.5 mUI

8.0 mUI

7.5 mUI

7.0 mUI

6.5 mUI

6.0 mUI

5.5 mUI

5.0 mUI

4.5 mUI

4.0 mUI

3.5 mUI

MGT103A (Typical and Four Process Corners)

TT-1.14 V

TT-1.26 V

SS-1.14 V

SS-1.26 V

SF-1.14 V

SF-1.26 V

FS-1.14 V

FS-1.26 V

FF-1.14 V

FF-1.26 V

RPT054_04_03_011007

Temp 0° C

Temp 100° C

Jitter Generation (RMS, 2.488 Gb/s, at Different Temperatures)2.488 Gb/s Unformatted PRBS23

REFCLK 311.04 Mhz

Jitte

r (r

ms)


TT-0°C

TT-100°C

SS-0°C

SS-100°C

SF-100°C

FS-100°C

FF-100°C

FS-0°C

FS-0°C

SF-0°C

RPT054_04_04_011007

AVCCAUXTX1.14V

AVCCAUXTX 1.26V

Jitter Generation (RMS, 2.488 Gb/s, at Different AVCCAUXTX)2.488 Gb/s Unformatted PRBS23

REFCLK 311.04 Mhz8.5 mUI

8.0 mUI

7.5 mUI

7.0 mUI

6.5 m UI

6.0 mUI

5.5 mUI

5.0 mUI

4.5 mUI

4.0 mUI

3.5 mUI




Jitter Generation Data Graphs (Jp-p vs. Voltage, Jp-p vs. Temperature)

Figure 2-39: 2.488 Gb/s P-P Jitter Generation vs. AVCCAUXTX at 0°C and 100°C

Figure 2-40: 2.488 Gb/s P-P Jitter Generation vs. Temperature at 1.14V and 1.26V

Jitte

r (p

-p)

100.0 mUI

95.0 mUI

90.0 mUI

85.0 mUI

80.0 mUI

75.0 mUI

70.0 mUITT-

1.1 4VTT-

1.26VSS-

1.1 4VSS-

1.26VSF-

1.1 4VSF-

1.26VFS-

1.1 4VFS-

1.26VFF-

1.1 4VFF-

1.26V


Temp 0°C

Temp 100°C

Jitter Generation (P-P, 2.488 Gb/s, at Different Temperatures)2.488 Gb/s Unformatted PRBS23

REFCLK 311.04 Mhz

RPT054_04_05_011007

Jitte

r (p

-p)

100.0 mUI

95.0 mUI

90.0 mUI

85.0 mUI

80.0 mUI

75.0 mUI

70.0 mUITT-0°C

TT-100°C

SS-0°C

SS-100°C

SF-0°C

SF-100°C

FS-0°C

FS-100°C

FF-0°C

FF-100°C

MGT103A (Typical and 4 Process Corners) RPT054_04_06_011007

AVCCAUXTX1.14 V

AVCCAUXTX1.26 V

Jitter Generation (P-P, 2.488 Gb/s, at Different AVCCAUXTX)2.488 Gb/s Unformatted PRBS23

REFCLK 311.04 Mhz



Transmitter Jitter Transfer (ATE Measurement)R

2.488 Gb/s Jitter Generation Summary

Transmitter Jitter Transfer (ATE Measurement)

Test DescriptionThe device under test (DUT) is configured to allow loopback in the fabric. The ParBERT generator channels drive data into the MGT receiver of the DUT. The data is then de-serialized and clocked into the FPGA fabric. From there, it is clocked into the MGT transmitter, reserialized, and transmitted out of the MGT TX into the ParBERT analyzer. Upon receiving correct data, the analyzer channels synchronize and lock. All twelve MGTs are set to operate with DEFAULT attributes and at a specific data rate of 2.5 Gb/s, 3.125 Gb/s, or 4.25 Gb/s, and TX eye width measurements are taken. Jitter is then modulated onto the MGTCLK and TX eye measurements are taken again. The difference between the two measurements is the amount of jitter transferred through the TX PLL.

Lab Setup

The standard configuration for the Agilent 93K-XP system is used with one modification. The AWG output is connected to the delay control of the MGTCLK generator cards instead of to the DATA Generator cards. This allows for sinusoidal jitter modulation of the MGTCLK across the range of frequencies from DC (1 kHz) through 80 MHz.

Power supplies from the Agilent 93K are used to provide a separate voltage on each of the following: VCCINT , VCCIO , VCCAUX, VCCAUXMGT , AVCCAUXTX, AVCCAUXRX, VTTX, and VTRX. VCCAUXMGT is provided from a digital channel. Board layout and supply polarity have been designed to minimize any IR drop or delayed response to any droop.

Test Equipment

The list of equipment used is covered in the Agilent 93K-XP section. The temperature control for 0°C and 85°C was done using a Thermonics T-2500E.


Tx Jitter Transfer for 2.5 GHz, 3.125 GHz, and 4.25 GHz VCO Frequency

Figure 2-41 through Figure 2-44 show the histogram distributions of the –3 dB “knee frequencies” of the TX PLL. The 2.5 GHz VCO has a lower and narrower distribution than the 3.125 GHz VCO. No difference is seen in distributions between the /10 and the /20 values of the feedback dividers. The reference clock frequencies in the /10 and /20 modes are the appropriate multiples of the VCO frequencies—for example, 250 MHz for a 2.5 GHz VCO frequency.

Table 2-10: 2.488 Gb/s Jitter Generation Summary

Jitter Generation(Sample Size: 20 MGTs)

Min Mean Max Std Dev

RMS (mUI) 4 6.35 8 0.88

Peak-to-Peak (mUI) 74 87 97 7.1




Figure 2-41: 2.5 Gb/s Jitter Transfer, 10X Dividers


2.5 Gb/s TX Jitter Transfer 10x, Vmin / Vmax and 0°C / 85°C

0.001 0.01 0.1 1 10 100

Modulation Frequency (Mhz)

Am

plitu

de o

f Mod

ulat

ion

Tran

sfer

ed

all_AVG_10x all_MIN_10x all_MAX_10x

0.01

0.10

1.00

10.00

RPT054_04_07_072006

0.001 0.01 0.1 1 10 100

Am

plitu

de o

f Mod

ulat

ion

Tran

sfer

ed

all_AVG_20x all_MIN_20x all_MAX_20x

2.5 Gb/s TX Jitter Transfer 20x , Vmin / Vmax and 0°C / 85°C


0.01

0.10

1.00

10.00

RPT054_04_08_072006



Transmitter Jitter Transfer (ATE Measurement)R



0.001 0.01 0.1 1 10 100

Am

plitu

de o

f Mod

ulat

ion

Tran

sfer

ed

0c_AVG_10x 0c_MIN_10x 0c_MAX_10x


3.125 Gb/s TX Jitter Transfer 10x , Vmin / Vmax and 0°C / 85°C


0.01

0.10

1.00

10.00

RPT054_04_09_071906

3.125 Gb/s TX Jitter Transfer 20x, Vmin / Vmax and 0°C / 85°C

0.001 0.01 0.1 1 10 100Modulation Frequency (Mhz)

Am

plitu

de o

f Mod

ulat

ion

Tran

sfer

ed



0.01

0.10

1.00

10.00

RPT054_04_10_072006




Data Distribution/ Comparison

The histograms in Figure 2-45 through Figure 2-50 show the tem

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