Power efficient design imec

© IMEC 2011 / CONFIDENTIAL

POWER EFFICIENT DESIGNSelecting the right technology node

PHILLIP CHRISTIE

IMEC


OVERVIEWSELECTING THE RIGHT TECHNOLOGY NODE

•Technology targeting

• Device modeling

• Virtual libraries

• Data visualization

• IP-level analysis

• Summary

2

© IMEC 2011 / CONFIDENTIAL 3

57 VARIETIES

Technology is a

commodity...

...but an expensive and

complex one


ELEVATOR SLIDE

4

0 0.5 1 1.5 2 2.5 3 3.5150

160

170

180

190

200

210

220

Clock rate (GHz)

Are

a (

um

2)

SiGe 1.1V

SiGe 0.7V

SiGe 0.6V

Si Bulk 1.1V

32nm Si/Ge channel(32-bit multiplier)

Client supplied IP block


LOWER POWER IS NOT AN OPTION!

5

90nm

LP

65nm

HP

28nm

LOPVdd

90% Vdd

80% Vdd

40nm

GP

Foundry A

12 track

9 track

HVT

SVT

Foundry B


THE PATH TO ENLIGHTENMENT?

6

Foundry guidance

ExperienceRepetition


CAN IMEC’S ASIC SERVICES HELP?

• Long term foundry relationships

- Europractice (TSMC, UMC, OnSemi, austriamicrosystems)

- Authorized TSMC VCA partner (Value Chain Aggregator)

- Large customer base

• COT or Turn-Key manufacturing solutions

• Large data-bases of foundry device models and libraries

• Process technology and lithography, design expertise

7

AND YET

• Many problems targeting the right technology


INNOVATION REQUIRED

• Comply with EDA tool data formats (Verilog-A, CCSM/NLDM, Liberty, LEF/DEF, VHDL/Verilog)

BUT

• Critically re-evaluate assumptions about complexity/accuracy trade-offs at different points in design flow

•Transform device models, design rules, libraries, IP blocks from constants into variables

• Visualize complex multi-dimensional data

• Benchmark continuously

8


TARGETED DEVICE MODELING

9

us = sqrt(hyp1(Vsbsum + 0.9*phib, 1e-10) + 0.1*phib);

us0 = sqrt(phib);

VGT1 = hyp1(VGS - vt0, 5e-4);

DELTAVT0 = k0*(us-us0);

DELTAVT1 = (-gam0-(gam1*pow(VDS+1e-4,0.6-1)-gam0)*pow(VGT1,2)/(0.5+pow(VGT1,2)))*pow(VDS,2)/(VDS+0.1);

VGT2 = VGS-(vt0+DELTAVT0+DELTAVT1);

VGT3_hlp1 = (2*m0*v0);

if (abs(VGT3_hlp1) < 1e-20) begin

if (VGT3_hlp1 < 0) begin

VGT3_hlp1 = -1e-20;

end

else begin

VGT3_hlp1 = 1e-20;

end

end

VGT3 = 2*m0*v0*ln(1+exp(VGT2/VGT3_hlp1));

VDSSAT_hlp1 = (1+sqrt(1+2*the3*VGT3));

if (VDSSAT_hlp1 < 1e-20) begin

if (VDSSAT_hlp1 < 0) begin

VDSSAT_hlp1 = -1e-20;

end

else begin

VDSSAT_hlp1 = 1e-20;

end

end

VDSSAT = VGT3*2/VDSSAT_hlp1;

eps5 = 0.3*VDSSAT/(1+VDSSAT);

VDSPR = hyp5(VDS,VDSSAT,eps5);

G1 = exp(VGT2/VGT3_hlp1);

G3 = ((1-exp(-VDS/v0))+G1)/(1+G1);

IDS = beta*G3*((VGT3*VDSPR-0.5*pow(VDSPR,2))/((1+the1*VGT1)*(1+the3*VDSPR)));

Name Description Unit

bet Gain parameter A/V

vt0 Threshold voltage V

mo Sub-threshold slope

k0 Body coefficient

gam0 DIBL coefficient for low gate bias

gam1 DIBL coefficient for high gate bias

the1 Vertical field mobility reduction coefficient

the3 Horizontal field mobility reduction coefficient

bet vt0 k0 m0 gam0 gam1 the1 the3nmos 0.0046 0.5853 0.2456 1.5802 0.1554 0.1247 0.2034 1.1973

pmos 0.0018 0.5686 0.2308 1.5977 0.1735 0.2668 0.2859 0.8325

Eight parameters, fixed temp and gate geometry, disposable

0 0.5 1

2

4

6

8

x 10-5

Vgs (V)

Ids (

A)

0 0.5 1

2

4

6

x 10-5

Vgs (V)

Ids (

A)

0 0.5 1

10-5

Vgs (V)

Ids (

A)

0 0.5 10

2

4

x 10-4

Vds (V)

Ids (

A)

TSMC 40nm LP SVT BSIM4 data

TSMC 40nm LP SVT BSIM4 model parameters


TRANSIENT ANALYSIS BENCHMARKING(L=40NM, W=1UM, INCLUDING DEVICE PARASITICS)

0 0.5 1 1.5 2 2.5 3

x 10-10

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time (sec)

Voltage (

V)

0 0.5 1 1.5 2 2.5 3

x 10-10

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time (sec)

Voltage (

V)

0 0.5 1 1.5 2 2.5 3

x 10-10

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time (sec)

Voltage (

V)

0 0.5 1 1.5 2 2.5 3

x 10-9

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time (sec)

Voltage (

V)

Cload=0.1fFCload=1fF

Cload=10fF Cload=100fF

Reduced model extracted from BSIM4TSMC 40nm LP SVT BSIM4

10


DEVICE MODELING APPLICATIONS

0 0.2 0.4 0.6 0.8

2

4

6

8

10x 10

-5 Vds = 0.05

Vgs (V)

Igs (

A)

0 0.2 0.4 0.6 0.8

2

4

6

8

10x 10

-5 Vds = 0.05

Vgs (V)

Igs (

A)

0 0.2 0.4 0.6 0.810

-10

10-5

100

Vds = 0.8

Vgs (V)

Igs (

A)

0 0.2 0.4 0.6 0.80

2

4

6

x 10-4 Vgs = [0.55 0.7 0.8]

Vds (V)

Ids (

A)

Ioff

Ion

vt0

m0

NMOS

L=22nm

W = 1um

Temp = 25 ;

bet = 0.0136 ;

vt0 = 0.6170 ;

m0 = 1.7167;

k0 = 0 ;

gam0 = 0.28 ;

gam1 = 0.28 ;

the1 = 0 ;

the3 = 1.0517 ;

6

Vdd

(V)

Ion

(uA/um)

Ioff/um

(pA/um)

Vt linear

(V)

Body effect

(V/V)

Sub-threshold

slope

DIBL

(V/V)

90 SVT nmos 1.2 535 345 0.534 0.245 1.50 0.070

65 SVT nmos 1.1 471 128 0.532 0.200 1.30 0.098

40 SVT nmos 1.0 400 270 0.585 0.246 1.58 0.1247

90 SVT pmos 1.2 215 259 0.457 0.278 1.38 0.116

65 SVT pmos 1.1 233 58.9 0.540 0.304 1.34 0.188

40 SVT pmos 1.0 203 271 0.569 0.231 1.60 0.2667

ITRS 22nm Bulk LOP modelCross-model comparisons

Vertical versus planar FET

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.5

1

1.5

2

2.5

3

3.5

4x 10

-5

Vds (V)

Ids (

A)

0 5 10 15 20 25 30 35 40-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Time (ns)

Voltage (

V)

Local interconnect

0 5 10 15 20 25 30 35 400

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Time (ns)

Voltage (

V)

No

Local interconnect

Variability studies


VIRTUAL CELLS & LIBRARIES

• vCells do possess

- Height, width, timing, power and pin locations

• vCells do not possess

- detailed metal routing

- DfM complience

- GDSII view

• vCells can be used within synthesis, static

timing and place/route standard flows

• vCells are extremely fast to generate

12

FA1D1FA1D1


vLIB SPECIFICATION

CO_EN1R

CO_S3R

CO_W1

M2_W1

M2_S1

NP_EX1

NP_S2

NW_S6

NW_EN2

OD_S1

OD_W1

PO_EX1

PO_S2RN

PO_S4

PO_W1

Track height

N/P ratio

Power strap

Restricted Design Rules

Cell options

vLib design style

13


SEDFKCND4 vCELLLargest library cell, 48 transistors, run time 4-7min

14

SEDFKCND4 initial ordering

SEDFKCND4 final ordering

10.22 um

6.86 um


vCell AREA BENCHMARKING

15

0

2

4

6

8

TSMC045 - CELL AREA (um^2)

TSMC045-reference VCGF

-20

-10

0

10

20

30TSMC045 - AREA ERROR RARIO (%)

VCGF-area error

0

2

4

6

8

10

12

14



-20

-10

0

10

20


VCGF-area error

0

5

10

15

20

25



-20

-10

0

10

20

30

40


VCGF-area error

45nm average cell area error 1.1%




vLIB APPLICATIONS

16

0 0.2 0.4 0.6 0.8 1 1.2 1.4

x 10-5

-1

0

1

2

3

4

5

6x 10

-6

M1INCPBnet43VSSM2Dnet072net43 M3INCPnet072net50M4net051net50VSS M5INCPBnet053net055M6INCPnet055net051 M7net068net053VSSM8INCPBINCPVSSM9CPVSSINCPB M10

net053QNVSSM11net068QVSS M12

net055VSSnet068M13net072VSSnet051

M14net068net053VDDM15INCPBVDDINCPM16CPVDDINCPB M17net053QNVDDM18

net068VDDQ M19net055VDDnet068M20

net072VDDnet051M21Dnet74net072 M22

INCPVDDnet74M23INCPBnet051net055 M24INCPnet055net053M25INCPBnet072net86 M26net051net86VDD

Distance 0.000241

0 0.2 0.4 0.6 0.8 1 1.2 1.4

x 10-5

-1

0

1

2

3

4

5

6x 10

-6

M1INCPBVSSnet43

M2D

net43net072M3INCPnet072net50M4net051net50VSS M5INCPBnet053net055M6INCPnet055net051M7

net068VSSnet053 M8INCPBINCPVSS M9

CPINCPBVSSM10

net053VSSQN

M11net068VSSQ

M12net055

net068VSSM13

net072net051VSS

M14net068net053VDD M15

INCPBVDDINCP M16CPINCPBVDD

M17net053VDDQN

M18net068VDDQ

M19net055

net068VDDM20

net072VDDnet051M21

Dnet072net74M22

INCPnet74VDD M23

INCPBnet055net051M24INCPnet053net055 M25INCPBnet072net86M26net051VDDnet86

Distance 0.00036421

10 Track 140nm

10 Track 110nm

0 0.2 0.4 0.6 0.8 1 1.2 1.4

x 10-5

-1

0

1

2

3

4

5

6x 10

-6

M1net10net4net14M2

A1net14net6M3A2

VSSnet4 M4net4net6VSSM5net14

VSSZ M6A1VSSnet10

M7A1net4net14M8

net10net14net6M9A2

VDDnet4 M10net4net6VDDM11net14ZVDD M12A1net10VDD

Distance 0.00039825

M1net10net14net4M2

A1net6net14 M3A2

VSSnet4M4net4VSSnet6M5net14

VSSZ M6A1net10VSS

M7A1net14net4M8

net10net14net6M9A2

net4VDDM10net4net6VDDM11net14ZVDD M12A1VDDnet10

M1INCPBnet43VSS M2

Dnet43net072M3INCPnet50net072M4net051VSSnet50M5INCPBnet055net053 M6INCPnet051net055M7net068net053VSS M8INCPBINCPVSSM9CPVSSINCPBM10net053QNVSSM11

net068VSSQM12

net055VSSnet068 M13

net072net051VSS

M14net068net053VDD M15INCPBVDDINCPM16CPINCPBVDDM17

net053QNVDD

M18net068

QVDDM19

net055VDDnet068

M20net072

net051VDDM21Dnet072net74M22

INCPVDDnet74 M23INCPBnet055net051M24INCPnet055net053 M25INCPBnet86net072M26net051net86VDD

M1INCPBnet43VSSM2

Dnet43net072 M3INCPnet50net072 M4net051net50VSSM5INCPBnet053net055M6INCPnet055net051 M7net068VSSnet053M8INCPBVSSINCPM9CPVSSINCPBM10net053QNVSS M11

net068QVSSM12net055VSSnet068M13

net072net051VSS

M14net068VDDnet053M15INCPBVDDINCPM16CPVDDINCPBM17

net053QNVDD

M18net068VDDQ

M19net055VDDnet068

M20net072

net051VDDM21Dnet74net072M22

INCPVDDnet74 M23INCPBnet055net051M24INCPnet053net055 M25INCPBnet072net86 M26net051net86VDD

M1

INCPBVSSnet43

M2

Dnet072net43M3

INCPnet50net072M4net051net50VSS M5

INCPBnet053net055M6INCPnet055net051M7

net068VSSnet053 M8INCPBINCPVSSM9

CPINCPBVSSM10

net053VSSQN

M11

net068QVSS

M12

net055net068VSS

M13

net072VSSnet051

M14net068VDDnet053 M15

INCPBINCPVDDM16CPVDDINCPB

M17

net053VDDQN

M18

net068VDDQ

M19

net055net068VDD

M20

net072VDDnet051

M21

Dnet072net74

M22

INCPnet74VDDM23

INCPBnet055net051M24INCPnet053net055 M25INCPBnet072net86M26net051net86VDD

10 Track 90nm

FA1D4

SEDFD1

9-Track

N/P=0.5

12-Track

N/P=0.5

12-Track

N/P=1.0

VFET

VFET

Device comparison

Node comparison

Library optimization


0.0224 0.0294 0.0423 0.0672 0.1180 0.2182 0.4196

0.0252 0.0322 0.0452 0.0702 0.1211 0.2215 0.4227

0.0319 0.0387 0.0515 0.0766 0.1277 0.2282 0.4291

0.0436 0.0513 0.0651 0.0901 0.1409 0.2417 0.4426

0.0553 0.0685 0.0886 0.1172 0.1685 0.2690 0.4706

0.0711 0.0882 0.1169 0.1603 0.2237 0.3236 0.5267

0.0851 0.1102 0.1498 0.2084 0.3037 0.4382 0.6270

0.0192 0.0258 0.0390 0.0649 0.1169 0.2204 0.4278

0.0228 0.0295 0.0429 0.0692 0.1208 0.2246 0.4315

0.0308 0.0375 0.0507 0.0768 0.1287 0.2323 0.4395

0.0452 0.0538 0.0672 0.0930 0.1452 0.2491 0.4564

0.0654 0.0785 0.0983 0.1268 0.1785 0.2823 0.4897

0.0926 0.1129 0.1433 0.1865 0.2460 0.3492 0.5565

0.1292 0.1594 0.2055 0.2714 0.3622 0.4844 0.6902

0.0008 0.0017 0.0036 0.0073 0.0147 0.0295 0.0591

0.0075

0.0195

0.0436

0.0917

0.1880

0.3806

0.7657

0.0075

0.0195

0.0436

0.0917

0.1880

0.3806

0.7657

0.0008 0.0017 0.0036 0.0073 0.0147 0.0295 0.0591

CloadCload

Ttrans Trans

Di,j TCBN90LPHDBWPWC Di,j TCBNLP65LPWC

INVD1 rise delay INVD1 rise delay

DATA VISUALIZATION

90nm matrix recalculated for 65nm indices

Cload

Ttrans0.0075

0.0195

0.0436

0.0917

0.1880

0.3806

0.7657

0.0008 0.0017 0.0036 0.0073 0.0147 0.0295 0.0591

17


INVERTER INTRINSIC DELAY SURFACES ∆DI,JLP SVT, 90NM (7-TRACK) VERSUS 65NM (9-TRACK)

INVD1 rise INVD1 fall

Intrinsic cell delay when driven and loaded

by 1x drive-strength inverter

18


MUX INTRINSIC DELAY SURFACES ∆DI,JLP SVT, 90NM (7-TRACK) VERSUS 65NM (9-TRACK)

MUX2D1 rise MUX2D1 fall

Larger “green zone” for MUX

19


INTRINSIC DELAY BUBBLE PLOTS

20

0 5 10 15 20 250

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Cell area (m2)

Cell

dela

y (

ns)

simple

complex

sequential

90nm LP (7-track)

65nm LP (9-track)


INTRINSIC DELAY BUBBLE PLOTSymbol size ~ leakage

21

0 1 2 3 4 5 6 7 80

0.2

0.4

0.6

0.8

1

1.2

1.4

Cell area (m2)

Cell

dela

y (

ns)

simple

complex

sequentialHVT

SVT

LVT


IP LEVEL ANALYSISSynthesis and static timing analysis, 32bit DSP

50 100 150 200 2500

1

2

3

4x 10

4

Clock rate (MHz)

Are

a (

m2)

tcbn65lpwc

tcbn65lpbwp12twc

tcbn90lphdbwpwc

50 100 150 200 2500

10

20

30

40

Clock rate (MHz)

Sta

tic p

ow

er

(W

)

tcbn65lpwc

tcbn65lpbwp12twc

tcbn90lphdbwpwc

Targeting IP library of 28 IP blocks


[delay(1) , slew(1) ] = timing( lib.EDFQD4, 6.768000e-15, 0) ;

[delay(2) , slew(2) ] = timing( lib.INVD6, 1.496000e-14, slew(1)) ;

[delay(3) , slew(3) ] = timing( lib.INVD16, 4.006100e-14, slew(2)) ;

[delay(4) , slew(4) ] = timing( lib.INR2D2, 4.412000e-15, slew(3)) ;

[delay(5) , slew(5) ] = timing( lib.XOR2D1, 3.002000e-15, slew(4)) ;

[delay(6) , slew(6) ] = timing( lib.FA1D4, 2.986000e-15, slew(5)) ;















[delay(21) , slew(21) ] = timing( lib.XOR2D4, 1.004700e-14, slew(20)) ;

cpu_mac/xm_reg[1]/Q (EDFQD4) 0.006768 0.180590 0.180590 r

cpu_mac/U101/ZN (INVD6) 0.014960 0.031485 0.212075 f

cpu_mac/U111/ZN (INVD16) 0.040061 0.036124 0.248199 r

cpu_mac/mult_134/U62/ZN (INR2D2) 0.004412 0.105305 0.353504 r

cpu_mac/mult_134/U233/Z (XOR2D1) 0.003002 0.149182 0.502686 r

cpu_mac/mult_134/S2_2_13/CO (FA1D4) 0.002986 0.130179 0.632865 r






cpu_mac/mult_134/S2_8_13/S (FA1D1) 0.003002 0.252774 2.033267 f

cpu_mac/mult_134/S2_9_12/S (FA1D4) 0.002986 0.158560 2.191826 r







cpu_mac/mult_134/S4_11/S (FA1D1) 0.005175 0.265554 3.833626 f

cpu_mac/mult_134/U173/Z (XOR2D4) 0.010047 0.175475 4.009101 f

CRITICAL PATH IMPORT TO MATLABPortion of DSP54 critical path at max clock rate synthesized using

65nm LP SVT technology

Design Compiler timing report Matlab script


100 SLOWEST PATHS DSP5490nm 9T, 65nm12T , 65nm 9T

24

Enables efficient multiple (10-100) library re-characterizations

and variability analysis

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7

x 10-9

0

10

20

Path delay (sec)

Insta

nce

s

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7

x 10-9

0

10

20

Path delay (sec)

Insta

nce

s

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7

x 10-9

0

5

10

15

Path delay (sec)

Insta

nce

s

100 slowest paths synthesized using 70 cells

10 slowest paths synthesized using 25 cells

Slowest path synthesized using 13 cells


TEMPERATURE AND VOLTAGE VARIATION Critical path variability visualization (DSP delay paths, 65nm LP SVT 9T, WC)

Can include gate length (global and local) variation, ...

Fast

Slow


POINTS TO REMEMBER

•There is no silver bullet, no tool, or software

program

• Employ standard EDA flows and formats but

with innovations in the use of

▸ device modeling

▸ library generation

▸ data visualization

▸ IP-level analysis

• Only the beginning of this program and

encourage collaboration and feedback

26

Power efficient design imec

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