PG- CMOS Fabrication Technology
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Transcript of PG- CMOS Fabrication Technology
• Purpose
– To provide an insight in to the methods and means for materializing circuits
designs in silicon. Which includes
• Silicon Semiconductor Technology: An Overview
• Fundamental Processing Steps in MOS Fabrication
• Basic CMOS fabrication Technology.
• To introduce the CMOS designer to the technology that is responsible for the
semiconductor devices that might be designed.
• MOS design rules and scaling factor for circuit design processes
• Basic circuit concept -- sheet resistance,capacitance,delay and other issues.
• Enhancements to the basic CMOS technology are described.
• MOS Mask layer, Stick diagram , scaling factor and scaling of MOS circuits are
introduced.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
1. Silicon Semiconductor Technology: An Overview MOS transistor material: Silicon
• It is a semiconductor in its pure state with resistance somewhere between that
of a conductor and insulator.
• Conductivity can be varied over several orders of magnitude by introducing
impurity atoms into the silicon crystal lattice.
• Dopants may either supply free electrons or holes.
• Acceptors are impurity elements (dopants) that accept some of the electrons
already in the silicon, leaving vacancies or holes.
• Donors are impurity elements that provide electrons.
• Silicon that contains a majority of donors is known as n-type.
• Silicon that contains a majority of acceptors is known as p-type.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
CONTD….
• A junction is the region where the silicon changes from n-type to p-type
material where n-type and p-type materials are brought together.
• By arranging junction in certain physical structures and combining these
with other physical structures, various semiconductor devices may be
constructed.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Fundamental Processing Steps in MOS Fabrication:
Basic steps
• Crystal Growth
• Wafer Processing
• Oxide growth
• Thermal diffusion
• Ion implantation
• Deposition
• Etching
• Epitaxy
Photolithography
Photolithography is the means by which the above steps are applied to
selected areas of the silicon wafer.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Crystal Growth
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
• Silicon must be crystal to be
used in IC’s Crystal growth - the
process of creating crystalline
silicon
• Seed crystal (solid piece of
crystalline silicon) “brought into
contact with the surface of the
same material in liquid phase,
and then pulled slowly from the
melt”
• Liquid cools, solidifies following
crystal form
• Czochralski method
Wafers are cut from ingots of single-crystal silicon that have been pulled
from a
crucible melt of pure molten polycrystalline silicon. Ingot cut to uniform diameter, then sliced into wafersWafers machined into uniformed thicknessChemically and mechanically smoothed during
“lapping” and “polishing” phasesCompleted silicon wafer is known as the substrate
material
• wafer diameter: 75 mm to 300 mm.
• wafer thickness: 0.25 mm to 1.0 mm.
• crystal orientation determined by a seed crystal.
• Ingot growth rate: 30 to 180 mm/hour.
• see Figure 3.1:Czochralski method for
manufacturing silicon Ingot Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Wafer Processing
Unmodified ingots
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Wafer Processing
Fig: Silicon wafer
. CONTD….
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Oxidation (Produce Isolation Layer SiO2)
Description:
Oxidation is the process by which a layer of silicon dioxide is
grown on
the surface of a silicon wafer.
Oxidation of silicon is achieved by heating silicon wafer in an
oxidizing
atmosphere such as oxygen or water vapor.
Uses:
• Protect the underlying material from contamination.
• Provide isolation between two layers. Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
contd..
Properties of silicon dioxide
• It is an excellent electrical insulator
• It can be grown on a silicon wafer or deposited on top of the wafer
Forming silicon dioxide (SiO2)
o Two common approaches to oxidation of silicon:
•Wet oxidation:
1. wafer vapor. (Si+2H2O SiO2+2H2 )
2. The temperature between 900oC and 1000 oC.
3. This is a rapid process.
• Dry oxidation:
• Pure oxygen (Si+O2 SiO2).
• Temperatures of 1200 oc to achieve an acceptable growth rate. • This is a slow process
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
• Contd….
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
• NOTE: Since SiO2 has approximately twice the volume of silicon, the SiO2 layer
grows almost equally in both vertical directions. (see Figure 3.2)
Figure:3.2 An NMOS transistor showing the growth of the field oxide below the silicon surface
Epitaxy, Deposition, Ion-Implantation, and Diffusion
Epitaxy : It involves growing a single-crystal film on the silicon surface by
subjecting the silicon wafer surface to elevated temperature and a source of
dopant material.
Deposition : Evaporating dopant material onto the silicon surface followed by
a thermal cycle, which is used to drive the impurities form the silicon surface
into the bulk.
Ion implantation: It involves subjecting the silicon substrate to highly
energized donor or acceptor atoms. When these atoms strike on the silicon
surface, they travel below the surface of the silicon, forming regions with
varying doping concentrations.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Epitaxy, Deposition, Ion-Implantation, and Diffusion
Diffusion : At temp. > 800ºc, Impurities will diffuse from areas of
high concentration to area of low concentration. It's important once
the doped areas have been put in place, to keep the remaining
process steps at as low a temperature as possible.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Fig: doping Fig: diffusion
Epitaxy, Deposition, Ion-Implantation, and Diffusion
Construction of transistors depends on:
● Impurities: Boron: Acceptors
Arsenic, phosphorous: Donors
● Amount is controlled by
1. Energy and time of “Ion implantation”.
2. Time and temperature of “deposition” and “diffusion”.
● Lithography One of the most critical problems in CMOS fabrication is the technique used to create a pattern
• Photolithography The photolithographic process starts with the desired pattern definition for the layer A mask is a piece of glass that has the pattern defined using a metal such as
chromium
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Contd.. The common materials used as mask include:
• Photoresist
• Polysilicon
• Silicon dioxide (sio2)
• Silicon nitride (si3n4)
Selective diffusion entails:
• Patterning windows in a mask material on the surface of the
wafer.
• Subjecting exposed area to a dopant source.
• Removing any unrequired mask material.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
• Step 1: Covering the surface of the oxide with an
acid resistant coating (called photoresist), and on top
of this covering a mask which contains desired oxide
windows.
• Step 2: Polymerizing the acid resistant coating by
passing the coated silicon through the UV light.
• Step 3: Removing the polymerized areas with an
organic solvent. This is called a positive resist.
if removing the unexposed photoresist area by the
solvent .This is called a negative resist..
• Step 4: Etching of exposed SiO2.
• Figure 3.3 shows an example of negative resist
process.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Example: The process of creating an oxide mask
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Using photoresist in conjunction with UV light sources, diffraction around the edges
of the mask patterns and alignment tolerances limit line widths to around 0.8 um.
Electron beam lithography (EBL) can produce line widths smaller than 0.5 um.
– Main advantages of EBL:
• Patterns are derived directly from digital data.
• No intermediate hardware image such as masks is needed (i.e., masks are stored
as the form of data).
• Different patterns may be accommodated in different sections of wafers.
• Changes to patterns can be implemented quickly.
– Main disadvantages of EBL:
• Cost of the equipment.
• Requiring the large amount of time (i.e., the desired patterns are generated
sequentially and only one wafer can be handled at a time).
Contd..
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Silicon Gate Process Si Single-crystal form
Poly crystalline form (Polysilicon)
Polysilicon can be used as interconnect in silicon IC’S and as the gate electrode on
MOS transistors.
Polysilicon gate can be further used as a mask to allow precise definition of source
and drain electrodes.
Polysilicon is formed when silicon is deposited on SiO2 or other surface.
Undoped polysilicon has high resistivity.
Polysilicon gate and source/drain regions are doped at the same time to increase
their conductivity.
Figure 3.4 shows the processing steps after the initial patterning of the SiO2.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Contd…..
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Contd…..Fig: Fabrication steps for an nMOS
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Contd.. Two kinds of silicon oxides:
• Gate-oxide (thinox): A thin highly controlled layer of SiO2
which
defines the gate area of a transistor.
• Field-oxide: A thick layer of SiO2 is required elsewhere to
isolate the
individual transistors.
Figure 3.4(b) forms gate oxide.
Figure 3.4(c) grows polysilicon gate.
Figure 3.4(d) dopes the gate and source/drain regions.
Doping of substrate only occurs at the regions where the
polysilicon gate
does not shadow the underlying substrate or where is not covered
by SiO2.
The case of using silicon gate as a mask is referred to as self-
aligned
process because the source and drain do not extend under the
gate.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Figure 3.4(e) forms the contact cuts.
Figure 3.4(f) forms the contacts and interconnect.
Note that parasitic MOS transistors exist between unrelated
transistors
as shown in Figure 3.5.
These transistors have very thick gate oxide such that their
threshold
voltage is much higher than that of a regular transistor.
Contd..
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
The four main CMOS technologies:
1. n-well process
2. p-well process
3. twin-tub process
4. silicon on insulator(SOI)
3.2 Basic CMOS fabrication Technology***
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Figure 3.6 summarizes the drawing convention for presenting CMOS process
technology.
3.2 Basic CMOS Technology***
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Major steps involved in a typical n-well CMOS process.
1. Start with a lightly doped p-type substrate (wafer)
2. Create the n-type well for the p-channel device.
3. Build the n-channel transistor in the "native" p-substrate
4. CMOS process and layout drawing conventions
Figures below illustrates the major steps involved in a typical
n-well CMOS process.
3.2.1 Basic n-well CMOS fabrication process**
(a) Define n-well (n-tub)
• n-well for PMOS
• n-well-shallow is better
• Well is extended by
lateral
diffusion
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Contd…
(b) Define Active Region
• Grow SiO2/Si3N4
(c) Channel-stop Implant:
• Use p-well Mask
• Dope the p-sub with p+ in areas
where no nMOS using
photoresisit
• Prevent conduction between
unrelated transistor source/drain(d) Strip Photoresist• Grow thick field oxide where Si3N4 layer is absent• (LOCOS) (Bird’s break): Final field oxide and Gate Oxide• interface is very planar smaller L
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
(e) Define Polysilicon gate
• Lead to “Self-aligned” Source/
Drain Region
(f) Define NMOS
• Use N+ mask
• Poly is doped
(g) Light-Doped Drain(LDD)
Contd…
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
(h) P+ mask
• (LDD is not required),
• Less Hot-carrier susceptibility.
(i)
• Grow SiO2
• Define contact cut: Etch
• SiO2 down to surface to be
conducted.
(j) Metallization:
•Add metal to produce
•circuit connectivity
Contd…
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
The cross section of a CMOS inverter is shown in Figure 3.8.
● Substrate Contact (Well contacts, Body ties, Tub ties)
1. Place n+ region in the n-well (Vdd contacts)
2. Place p+ region in the p-type substrate (Vss contacts)
Contd…
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
The cross section of a CMOS inverter is shown in Figure 3.8.
● Substrate Contact (Well contacts, Body ties, Tub ties)
1. Place n+ region in the n-well (Vdd contacts)
2. Place p+ region in the p-type substrate (Vss contacts)
Contd…
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Contd…(EXTRA)
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Contd…
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Contd…(EXTRA)
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Typical p-well fabrication steps are similar to an n-well process, except
that a p-well is implanted to form n-transistors rather than an n-well.
n-well process is more popular in recent years
(p-well process is popular in the past)
The device in the substrate has better characteristics
• p-well process has better p devices than the n devices
• Note p-devices have lower gain than the n devices
• n-well process exacerbates the difference, but p-well process can
balance the difference
P-well processes are preferred in circumstances where the
characteristics
of the n- and p-transistors are required to be more balanced than that
achievable in an n-well process.
3.2.2 The P-well Process
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
3.2.2 The P-well Process
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
1. Provide separate optimization of the n-type and p-type transistors
2. Make it possible to optimize "Vt", "Body effect", and the "Gain" of
n, p devices, independently.
3. Processing steps:
Starting material: an n+ or p+ substrate with lightly doped -> "epitaxial" or "epi"
layer -> to protect "latch up“
Epitaxy"
a. Grow high-purity silicon layers of controlled thickness
b. With accurately determined dopant concentrations
c. Electrical properties are determined by the dopant and its
concentration in Si
3.2.3 Twin-Tub Processes
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Process sequence
1. Tub formation
2. Thin-Oxide construction
3. Source & drain implantations
4. Contact cut definition
5. Metallization
● Balanced performance of n and p devices can be constructed.
3.2.3 Twin-Tub Processes
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Process sequence
1. Tub formation
2. Thin-Oxide construction
3. Source & drain implantations
4. Contact cut definition
5. Metallization
● Balanced performance of n and p devices can be constructed.
3.2.3 Twin-Tub Processes
Fig: Twin well CMOS process Cross section
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
3.2.4 Silicon On Insulator (SOI)***– Rather than using silicon as the substrate, use an insulating substrate to improve process
characteristics such as latch up and speed.
– The steps used in typical SOI CMOS process are as follows (see Figure 3.11):
• A thin film (7-8 um) of very lightly doped n-type Si is epitaxial grown over an
insulator. Sapphire or SiO2 is a commonly used insulator. (Figure 3.11(a))
• An anisotropic etch is used to etch away the Si except where a diffusion area will be
needed. (Figure 3.11(b) & (c).
• Implantation of the p-island where an n-transistor is formed. (Figure 3.11(d))
• Implantation of the n-island where a p-transistor is formed. (Figure 3.11(e))
• growing of a thin gate oxide (100 - 250 Å).
• Depositing of phosphorus-doped polysilicon film over the oxide. (Figure 3.11(f))
• Patterning of polysilicon gate. (Figure 3.11(g))
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
3.2.4 Silicon On Insulator (SOI)
• Patterning of polysilicon gate. (Figure 3.11(g))
• Forming of the n-doped source and drain of the n-channel devices in the p- islands.
(Figure 3.11(h))
• Forming of the p-doped source and drain of the p-channel devices in the n-islands.
(Figure 3.11(i))
• Depositing of a layer of insulator material such as phosphorus glass or SiO2 over the
entire structure.
• Etching of the insulator at contact-cut locations. The metallization layer is formed
next. (Figure 3.11(j))
• Depositing of pssivation layer and etching of bonding pad location.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
3.2.4 Silicon On Insulator (SOI)• Patterning of polysilicon gate. (Figure 3.11(g))
• Forming of the n-doped source and drain of the n-channel devices in the p- islands.
(Figure 3.11(h))
• Forming of the p-doped source and drain of the p-channel devices in the n-islands.
(Figure 3.11(i))
• Depositing of a layer of insulator material such as phosphorus glass or SiO2 over
the entire structure.
• Etching of the insulator at contact-cut locations. The metallization layer is formed
next. (Figure 3.11(j))
• Depositing of pssivation layer and etching of bonding pad location.
– Because the diffusion regions extend down to the insulating substrate, only “sidewall”
areas
associated with source and drain diffusions contribute to the parasitic junction capacitance.
– Since sapphire and SiO2 are extremely good insulators, leakage currents between
transistors
and substrate and adjacent devices are almost eliminated
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Fig: SOI Process flow
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Fig: SOI Process flow
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
3.2.4 Silicon On Insulator (SOI)
In order to improve the yield, some processes use “preferential etch,”
where the island edges are tapered (Figure 3.12).
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Fig: SOI Process flow
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Fig: SOI Process flow
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
3.2.4 Silicon On Insulator (SOI)
Advantages of SOI:
• Due to the absence of wells, transistor structures denser than bulk silicon are feasible.
• Lower substrate capacitance.
• No field-inversion problems (the existence of parasitic transistor between two normal
transistors)
• No latch up is possible because of the isolation of transistors by insulating substrate.
• No body-effect problems because of no conducting substrate.
• With enhanced radiation tolerance.
Disadvantages of SOI :
• Lack of substrate diodes makes I/O protection difficult.
• Coupling capacitance still exists.
• More expensive to build.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
MOS mask layero MOS design is aimed at turning a specification in to Masks for processing silicon
to meet the specification
o MOS Circuits are formed on four basic layers
1. n-diffusion
2. p-diffusion
3. Polisilicon
4. Metal
Above layers are isolated by silicon dioxide(sio2)
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram• A stick diagram is a cartoon of a layout.• Does show all components/vias (except possibly tub ties), relative placement.• Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.
• VLSI design aims to translate circuit concepts onto silicon
• Stick diagrams are a means of capturing topography and layer
information – simple diagrams
• Stick diagrams convey layer information through colour codes (or
monochrome encoding
• Used by CAD packages, including Microwind Stick diagrams may be
used to convey layer information through the use of a color code
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram• Fig: Monochrome encoding schemes for stick diagram
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram•Fig: color encoding schemes for stick diagram
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram•Fig: encoding schemes for double Metal CMOS P well process
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram•Fig: color encoding schemes for double Metal CMOS P well process
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram•Fig: Additional encoding schemes for double Metal BiCMOS process
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram•Fig: Additional encoding schemes for double Metal BiCMOS process
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram•Fig: Additional encoding schemes for double Metal BiCMOS process
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
nMOS design style Single metal single polysilicon nMOS technology: the stick layout of nMOS
involves
• n-diffusion and other thinox region
• polysilicon 1
• Metal 1
• Implant
• Contacts
A trasistor is formed whenever poly crosses n-diffusion.
N+ N+
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
nMOS design style
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
CMOS design style In this depletion mode transistor are not used.
Two types of transistor s used- n and p
Both the transistor are separated by demarcation line in stick diagram
demarcation line representing the p-well boundary (dotted line)
P- device must be place below the demarcation line and n-device must be place
above the demarcation line
Diffusion paths must not cross the demarcation line and n-diffusion and p-diffusion
wires must not join, but joined by metal
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
CMOS design style
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
CMOS design style
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram for basic gates (both nMOS and CMOS)
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram for basic gates (both nMOS and CMOS)
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Stick diagram for basic gates (both nMOS and CMOS)
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Design Rules
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Design rules
Allow translation of circuits (usually in stick diagram or symbolic form) into actual
geometry in silicon
Guidelines for constructing process masks
Interface between circuit designer and fabrication engineer
the rules are defined in terms of feature size, separation and overlaps
Compromise
Designer - tighter, smaller
Fabricator - controllable, reproducible
Two types of design rules
Lambda Based Design Rules –scalable design rules
Micron Based Design Rules – absolute dimensions
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Design rules
We can specify the design rules using some convenient units, e.g., microns but what happens if we want to manufacture the chip using different manufacturers?
One suggestion: use an abstract unit, the lambda, and scale the design to the appropriate actual dimensions when the chip is to be manufactured.
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Lambda Based Design Rules
Design rules based on single parameter, λ Simple for the designer Wide acceptance Provide feature size independent way of setting out mask If design rules are obeyed, masks will produce working circuits Minimum feature size is defined as 2 λ Used to preserve topological features on a chip Prevents shorting, opens, contacts from slipping out of area to be
contacted
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Lambda Based Design Rules
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Lambda Based Design Rules
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Lambda Based Design Rules
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Lambda Based Design Rules
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Lambda Based Design Rules
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Lambda Based Design Rules
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Lambda Based Design Rules
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Lambda Based Design Rules
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
Scaling of MOS Circuits
Scaling: VLSI technology is constantly evolving towards smaller line
widths Reduced feature size generally leads to
Better / faster performance More gate / chip
More accurate description of modern technology is ULSI (ultra large scale integration)