Part II Lectures 8-14 Bipolar Junction Transistors (BJTs) and ......The dc biasing is necessary to...

Part II Lectures 8-14

Bipolar Junction Transistors (BJTs) and Circuits

University of Technology Bipolar Junction Transistors Electrical and Electronic Engineering Department Lecture Eight - Page 1 of 8

Second Year, Electronics I, 2009 - 2010 Dr. Ahmed Saadoon Ezzulddin

(Emitter) (Collector)

(Base)

CE

B

E

B

C

n p n

C-B junctionE-B junction

CE

B

E

B

C

np p

Bipolar Junction Transistors (BJTs) Basic Construction: The transistor is a three-layer semiconductor device consisting of either two n- and one p-type layers of material or two p- and one n-type layers of material. The former is called an npn transistor, while the latter is called a pnp transistor. Both (with symbols) are shown in Fig. 8-1. The middle region of each transistor type is called the base (B) of the transistor. Of the remaining two regions, one is called emitter (E) and the other is called the collector (C) of the transistor. For each transistor type, a junction is created at each of the two boundaries where the material changes from one type to the other. Therefore, there are two junctions: emitter-base (E-B) junction and collector-base (C-B) junction. The outer layers of the transistor are heavily doped semiconductor materials having widths much greater than those of the sandwiched p- or n-type material. The doping of the sandwiched layer is also considerably less than that of the outer layers (typically 10:1 or less). This lower doping level decreases the conductivity (increases the resistance) of this material by limiting the number of "free" carriers.

Fig. 8-1 The dc biasing is necessary to establish the proper region of operation for ac amplification or switching purposes. Table 8-1 shows the transistor operation regions and the purpose with respect to the biasing of the E-B and C-B junctions.

Table 8-1

Junctions biasing Operation region Purpose E-B junction bias C-B junction bias

1 Active region Amplification Forward-biased Reverse-biased 2 Cutoff region Reverse-biased Reverse-biased 3 Saturation region

Switching Forward-biased Forward-biased

The abbreviation BJT, from bipolar junction transistor, is often applied to this three-terminal device. The term bipolar reflects the fact that holes and electrons participate in the injection process into the oppositely polarized material. If only one carrier is employed (electron or hole), it is considered a unipolar device. Such a device is the field-effect transistor (FET).



Active Region Operation: The basic operation of the transistor will now be described using the pnp transistor of Fig. 8-2. The operation of the npn transistor is exactly the same if the roles played by the electron and hole are interchanged. When the E-B junction is forward-biased, a large number of majority carriers will diffuse across the forward-biased p-n junction into the n-type material (base). Since the base is very thin and has a low conductivity (lightly doping), a very small number of these carriers will take this path of high resistance to the base terminal. The larger number of these majority carriers will diffuse across the reverse-biased C-B junction into the p-type material (collector). The reason for the relative ease with which the majority carriers can cross the reverse-biased C-B junction is easily understood if we consider that for the reverse-biased diode the injected majority carriers will appear as minority carriers in the n-type base region material. Combining this with the fact that all the minority carriers in the depletion region will cross the reverse-biased junction of a diode accounts for the flow indicated in Fig. 8-2.

Fig. 8-2 Applying Kirchhoff's current law to the transistor of Fig. 8-2, we obtain BCE III += [8.1] The collector current, however, is comprised of two components: the majority and minority carriers as indicated in Fig. 8-2. The minority-current component is called the leakage current and is given the symbol ICO (IC current with emitter terminal Open). The collector current, therefore, is determined in total by Eq. [8.2]. = IC majority + ICO minority [8.2] CI



EEV CCV

EI CI

BI+

−EBV

−

+BCV

E

B

C

EEV CCV

EI CI

BI

−

+BEV

+

−CBV

E

B

C

Common-Base (CB) Configuration: The common-base configuration with npn and pnp transistors are indicated in Fig. 8-3. The common-base terminology is derived from the fact that the base is common to both input and output sides of the configuration. In addition, the base is usually terminal closest to, or at, the ground potential.

Fig. 8-3 In the dc mode the levels of IC and IE due to the majority carriers are related by a quantity called alpha (αdc) and defined by the following equation:

E

Cdc I

I=α [8.3]

Where IC and IE are the levels of current at the point of operation and αdc ≈ 1, or for practical devices: 0.900 ≤ αdc ≤ 0.998. Since alpha is defined solely for the majority carriers and from Fig. 8-4, Eq. [8.2] becomes CBOEC III += α [8.4] Fig. 8-4 The input (emitter) characteristics for a CB configuration are a plot of the emitter (input) current (IE) versus the base-to-emitter (input) voltage (VBE) for a rage of values of the collector-to-base (output) voltage (VCB) as shown in Fig. 8-5. Since, the exact shape of this IE-VBE carve will depend on the reverse-biasing output voltage, VCB. The reason for this dependency is that the grater the value of VCB, the more readily minority carriers in the base are swept through the C-B junction. The increase in emitter-to-collector current resulting from an increase in VCB means the emitter current will be greater for a given value of base-to-emitter voltage (VBE). Fig. 8-5



The output (collector) characteristics for CB configuration will be a plot of the collector (output) current (IC) versus collector-to-base (output) voltage (VCB) for a range of values of emitter (input) current (IE) as shown in Fig. 8-6. The collector characteristics have three basic region of interest, as indicated in Fig. 8-6, the active, cutoff, and saturation regions.

Active region: VCB > 0 and EC II α= .

Cutoff region: IE = 0 and . CBOC II =

Saturation region: Fig. 8-6 VCB < 0 and . .)(.)( satEsatC II ≈

For ac situations where the point of operation moves on the characteristic carve, an ac alpha (αac) is defined by

.constVE

Cac

CBII

=ΔΔ

=α [8.5]

The ac alpha is formally called the common-base, short-circuit, amplification factor, and for most situations the magnitudes of αac and αdc are quite close, permitting the use of the magnitude of one for other. Fig. 8-7 shows how the common-base output characteristics appear when the effects of breakdown are included. Note the sudden upward swing of each curve at a large value of VCB. The collector-to-base breakdown voltage when IE = 0 (emitter open) is designed BVCBO. Fig. 8-7 Transistor Amplification Action: The basic voltage-amplifying action of the CB configuration can now be described using the circuit of Fig. 8-8. The dc biasing does not appear in the figure since our interest will be limited to the ac response. For the CB configuration, the input resistance between the emitter and the base of a transistor will typically vary from 10 to 100 Ω, while the output resistance may vary from 100 kΩ to 1 MΩ. The difference in resistance is due to the forward-biased junction at the input (base to emitter) and the reverse-biased junction at the output (base to collector). Using effective values and a common value of 20 Ω for the input resistance, we find that



BBV

CCV

EI

CI

BI

+

−BEV

+

−CEV

E

B

C+

−CBV

BBV

CCV

EI

CI

BI

−

+EBV

−

+ECV

E

B

C−

+BCV

. mAmVRVI iii 1020/200/ =Ω==If we assume for the moment that

αac = 1 (Ic = Ie), mAII iL 10==and . VkmARIV LL 50)5)(10( =Ω==The voltage amplification is Fig. 8-8 . 250200/50/ === mVVVVA iLv

Typical values of voltage amplification for the common-base configuration vary from 50 to 300. The current amplification (IC/IE) is always less than 1 for the CB configuration. This latter characteristic should be obvious since IC = αIE and α is always less than 1. The basic amplifying action was produced by transferring a current I from a low-to a high-resistance circuit. The combination of the two terms in italics results in the label transistor; that is, transfer + resistor → transistor. Common-Emitter (CE) Configuration: The common-emitter configuration with npn and pnp transistors are indicated in Fig. 8-9. The external voltage source VBB is used to forward bias the E-B junction and the external voltage source VCC is used to reverse bias C-B junction. The magnitude of VCC must be greater than VBB to ensure the C-B junction remains reverse biased, since, as can be seen in the Fig. 8-9, .BBCCCB VVV −=

Fig. 8-9

From Eqs. [8.1] and [8.4], we obtain CBOBCC IIII ++= )(α Rearranging yields

αα

α−

+−

=11

CBOBC

III [8.6]

From Fig. 8-10, Eq. [8.6] becomes

01 =−

=BI

CBOCEO

IIα

[8.7] Fig. 8-10



In the dc mode the levels of IC and IB are related by a quantity called beta (βdc) and defined by the following equation:

B

Cdc I

I=β [8.8]

Where IC and IB are the levels of current at the point of operation. For practical devices the levels of βdc typically ranges from about 50 to over 500, with most in the mid range. On specification sheets βdc is usually included as hFE with h derived from an ac hybrid equivalent circuit. For ac situation an ac beta (βac) has been defined as follows:

.constVB

Cac

CEII

=ΔΔ

=β [8.9]

The formal name for βac is common-emitter, forward-current, amplification factor and on specification sheets βac is usually included as hfe. A relationship can be developed between β and α using the basic relationships introduced thus far. Using BC II /=β we have β/CB II = , and from EC II /=α we have α/CE II = . Substituting into BCE III += we have βα /CI/ CC II += and dividing both sides of the equation by IC will result in βα /11/1 = + or

αβααββ )1( +=+= so that

1+

=ββα or

ααβ−

=1

[8.10]

In addition, recall that )1/( α−= CBOCEO II but using an equivalence of

1)1/(1 +=− βα derived from the above, we find that CBOCEO II )1( += β or CBOCEO II β≅ [8.11] Beta is particularly important parameter because it provides a direct link between current levels of the input and output circuits for CE configuration. That is, BCEOBC IIII ββ ≈+= [8.12] and since BBBCE IIIII +=+= β we have BE II )1( += β [8.13]



The input (base) characteristics for the CE configuration are a plot of the base (input) current (IB) versus the base-to-emitter (input) voltage (VBE) for a range of values of collector-to-emitter (output) voltage (VCE) as shown in Fig. 8-11. Note that IB increases as VCE decreases, for a fixed value of VBE. A large value of VCE results in a large reverse bias of the C-B junction, which widens the depletion region and makes the base smaller. When the base is smaller, there are fewer recombinations of injected minority carriers and there is a corresponding reduction in base current (IB). Fig. 8-11 Fig. 8-12 The output (collector) characteristics for CE configuration are a plot of the collector (output) current (IC) versus collector-to-emitter (output) voltage (VCE) for a range of values of base (input) current (IB) as shown in Fig. 8-12. The collector characteristics have three basic region of interest, as indicated in Fig. 8-12, the active, cutoff, and saturation regions.

Active region: IB > 0 and BC II β= . Cutoff region: IB = 0 and CEO . C II = Saturation region: VCE ≈ 0 and β/.)(.)( satCsatB II = .

Common-Collector (CC) Configuration: The third and final transistor configuration is the common-collector configuration, shown in Fig. 8-13 with npn and pnp transistors. The CC configuration is used primarily for impedance-matching purposes since it has a high input impedance and low output impedance, opposite to that which is true of the common-base and common-emitter configurations. From a design viewpoint, there is no need for a set of common-collector characteristics to choose the circuit parameters. The circuit can be designed using the common-emitter characteristics. For all practical purposes, the output characteristics of the CC configuration are the same as for the CE configuration. For the CC configuration the output characteristics are a plot of emitter (output) current (IE) versus collector-to-emitter (output) voltage (VCE), for a range of values of base (input)



current (IB). The output current, therefore, is the same for both the common-emitter and common-collector characteristics. There is an almost unnoticeable change in the vertical scale of IC of the common-emitter characteristics if IC is replaced by IE for the common-collector characteristics (since 1≅α , CE II ≈ ).

BBV

CCV

EI

CI

BI

−

+BEV

−

+CEV

E

B

C

−

+CBV

BBV

CCV

EI

CI

BI

+

−EBV

+

−ECV

E

B

C

+

−BCV

Fig. 8-13 Transistor Casing and Terminal Identification: Whenever possible, the transistor casing will have some marking to indicate which leads are connected to the emitter, collector, or base of a transistor. A few of the methods commonly used are indicated in Fig. 8-14.

Fig. 8-14 Exercises: 1. Given an αdc of 0.998, determine IC if IE = 4 mA.

2. Determine αdc if IE = 2.8 mA and IB = 20 µA.

3. Find IE if IB = 40 µA and αdc is 0.98.

4. Given that αdc = 0.987, determine the corresponding value of β.

5. Given βdc = 120, determine the corresponding value of α.

6. Given that βdc = 180 and IC = 2.0 mA, find IE and IB.

7. A transistor has ICBO = 48 nA and α = 0.992. i. Find β and ICEO. ii. Find its (exact) collector current (IC) when IB = 30 μA. iii. Find the approximate collector current, neglecting leakage current.

University of Technology DC Biasing Circits of BJTs Electrical and Electronic Engineering Department Lecture Nine - Page 1 of 10


DC Biasing Circuits of BJTs Basic Concepts: The analysis or design of a transistor amplifier requires a knowledge of both the dc and ac response of the system. Too often it is assumed that the transistor is a magical device that can raise the level of the applied ac input without the assistance of an external energy source. In actuality, the improved output ac power level is the result of a transfer of energy from the applied dc supplies. The analysis or design of any electronic amplifier therefore has two components: the dc portion and the ac portion. Fortunately, the superposition theorem is applicable and the investigation of the dc conditions can be totally separated from the ac response. However, one must keep in mind that during the design or synthesis stage the choice of parameters for the required dc levels will affect the ac response, and vice versa. The term biasing appearing in the title of this lecture is an all-inclusive term for the application of dc voltages to establish a fixed level of current and voltage. For transistor amplifiers the resulting dc current and voltage establish an operating point on the characteristics that define the region that will be employed for amplification of the applied signal. Since the operating point is a fixed point on the characteristics, it is also called the quiescent point (abbreviated Q-point). By definition, quiescent means quiet, still, inactive. Fig. 9-1 shows a general output device characteristic with four operating points indicated. The biasing circuit can be designed to set the device operation at any of these points or others within the active region. The maximum ratings are indicated on the characteristics of Fig. 9-1 by a horizontal line for the maximum collector current ICmax and a vertical line at the maximum collector-to-emitter voltage VCEmax. The maximum power constraint is defined by the curve PCmax in the same figure. At the lower end of the scales are the cutoff region, defined by IB ≤ 0 μA, and the saturation region, defined by VCE ≤ VCE(sat).

Fig. 9-1



VCEQ

ICQ

Standard Biasing Circuits: 1. Fixed-Bias Circuit: Fig. 9-2a shows a fixed-bias circuit. Analysis:

For the input (base-emitter circuit) loop as shown in Fig. 9-2b:

0=−−+ BEBBCC VRIV

B

BECCB R

VVI −= [9.1a]

For the output (collector-emitter circuit) (a) loop as shown in Fig. 9-2c:

BC II β= 0=−++ CCCCCE VRIV

CCCCCE RIVV −= [9.1b] For the transistor terminal voltages:

CECCCCC

BEBBCCB

E

VRIVVVRIVV

VV

=−==−=

= 0 [9.1c]

(b) (c) Load-Line Analysis:

From Eq. [9.1b] and Fig. 9-3: Fig. 9-2 At cutoff region:

0==CICCCE VV [9.2a]

At saturation region:

0=

=CEVC

CCC R

VI [9.2b]

Design:

For an optimum design:

C

CCsatCCQ

CCCEQ

RVII

VV

22121

)( ==

= [9-3]

Fig. 9-3



VCEQ

ICQ

2. Emitter-Stabilized Bias Circuit: Fig. 9-4a shows an emitter-stabilized bias circuit. Analysis:


0=−−−+ EEBEBBCC RIVRIV BE II )1( += β

EB

BECCB RR

VVI)1( ++

−=

β [9.4a]


0=−+++ CCCCCEEE VRIVRI CE II ≅

)( ECCCCCE RRIVV +−= [9.4b] For the transistor terminal voltages:

CEECCCCC

BEEBBCCB

EEE

VVRIVVVVRIVV

RIV

+=−=+=−=

= [9.4c]

(b) (c) Load-Line Analysis:

From Eq. [9.4b] and Fig. 9-5: Fig. 9-4 At cutoff region:

0==CICCCE VV [9.5a]

At saturation region:

0=+=

CEVEC

CCC RR

VI [9.5b]

Design:


CCE

EC

CCsatCCQ

CCCEQ

VV

RRVII

VV

101

)(22121

)(

=

+==

=

[9-6] Fig. 9-5



3. Voltage-Divider Bias Circuit: Fig. 9-6a shows a voltage-divider bias circuit. Analyses:

For the input (base-emitter circuit) loop: Exact Analysis: From Fig. 9-6b:

21 RRRTh = [9.7a] From Fig. 9-6c:

21

22 RR

VRVE CCRTh +== [9.7b]

From Fig. 9-6d: (a) 0=−−−+ EEBEThBTh RIVRIE

BE II )1( += β

ETh

BEThB RR

VEI)1( ++

−=

β [9.7c]

BC II β= Approximate Analysis: (b) (c) From Fig. 9-6e: If => . 2RRi >> BII >>2

Since => . 0≈BI 21 II ≅Thus R1 in series with R2. That is,

21

2

RRVRV CC

B += [9.8a] (d)

Since EEi RRR ββ ≅+= )1( the condition that will define whether the approximation approach can be applied will be the following:

210RRE ≥β [9.8b] and

E

EEC

BEBE

RVII

VVV

=≅

−= [9.8c] (e)

For the output (collector-emitter circuit) loop: Fig. 9-6 )( ECCCCCE RRIVV +−= [9.9]



Load-Line Analysis: The similarities with the output circuit of the emitter-biased configuration result in the same intersections for the load line of the voltage-divider configuration. The load line will therefore have the same appearance as that of Fig. 9-5. The level of IB is of course determined by a different equation for the voltage-divider bias and the emitter-bias configuration. Design:


E

CCE

EC

CCsatCCQ

CCCEQ

RR

VV

RRVII

VV

β101

101

)(22121

2

)(

≤

=

+==

=

[9.10]

Example 9-1: Determine the dc bias voltage VCE and the current IC for the voltage-divider configuration of Fig. 9-6a with the following parameters: VCC = +22 V, β = 140, R1 = 39 kΩ, R2 = 3.9 kΩ, RC = 10 kΩ, and RE = 1.5 kΩ. Solution: Exact: Ω=== 55.39.33921 kkRRRTh

Vkk

kRR

VRE CCTh 2

9.339)22)(9.3(

21

2 =+

=+

=

ETh

BEThB RR

VEI)1( ++

−=

β

Akk

μ05.6)5.1)(141(55.3

7.02=

+−

=

mAII BCQ 85.0)05.6)(140( === μβ )( ECCCCCEQ RRIVV +−= )5.110)(85.0(22 kkm +−= V23.12=

Approximate: Testing: 210RRE ≥β )9.3(10)5.1)(140( kk ≥ Ω>Ω kk 39210 (satisfied)

Vkk

kRR

VRV CCB 2

9.339)22)(9.3(

21

2 =+

=+

=

VVVV BEBE 3.17.02 =−=−=

mAkR

VIIE

EECQ 867.0

5.13.1====

)( ECCCCCEQ RRIVV +−= )5.110)(867.0(22 kkm +−= V03.12=



4. Voltage-Feedback Bias Circuit: Fig. 9-7a shows a voltage-feedback bias circuit. Analysis:


0=−−−′−+ EEBEBBCCCC RIVRIRIV BCEBCC IIIIII β=≅=+=′

0=−−−−+ EBBEBBCBCC RIVRIRIV ββ

)( ECB

BECCB RRR

VVI++

−=

β [9.11a]


0=−′+++ CCCCCEEE VRIVRI CEC III ≅=′

)( ECCCCCE RRIVV +−= [9.11b] Load-Line Analysis: Continuing with the approximation CC II =′ will result in the same load line defined for the voltage-divider and emitter-biased configurations. The levels of IBQ will be defined by the chosen base configuration. (b) Design:


)(101

)(22121

)(

ECB

CCE

EC

CCsatCCQ

CCCEQ

RRR

VV

RRVII

VV

+≤

=

+==

=

β

[9-12]

(c) Fig. 9-7



Other Biasing Circuits: Example 9-2: (Negative Supply) Determine VC and VB for the circuit of Fig. 9-8. Solution:

0=+−− EEBEBB VVRI (KVL)

AkR

VVIB

BEEEB μ83

1007.09=

−=

−=

mAII BC 735.3)83)(45( === μβ VkmRIV CCC 48.4)2.1)(735.3( −=−=−= Fig. 9-8

VkRIV BBB 3.8)100)(83( −=−=−= μ Example 9-3: (Two Supplies) Determine VC and VB for the circuit of Fig. 9-9a. Solution: From Fig. 9-9b:

Ω=== kkkRRRTh 73.12.22.821

mAkkRR

VVI EECC 85.32.22.8

202021

=++

=++

= (a)

VkmVIRE EETh 53.1120)2.2)(85.3(2 −=−=−= From Fig. 9-9c:

0=+−−−− EEEEBEThBTh VRIVRIE (KVL) BE II )1( += β

ETh

BEThEEB RR

VEVI)1( ++

−−=

β (b)

Akk

μ39.35)8.1)(121(73.1

7.053.1120=

+−−

=

mAII BC 25.4)39.35)(120( === μβ VkmRIVV CCCCC 53.8)7.2)(25.4(20 =−=−=

)73.1)(39.35()53.11( kRIEV ThBThB μ−−=−−= V59.11−= (c)

Fig. 9-9



Example 9-4: (Common-Base) Determine VCB and IB for the common-base configuration of Fig. 9-10. Solution: Applying KVL to the input circuit:

0=++− BEEEEE VRIV

mAkR

VVIE

BEEEE 75.2

2.17.04=

−=

−=

Applying KVL to the output circuit: 0=−++ CCCCCB VRIV

CCCCCB RIVV −= with EC II ≅

VkmVCB 4.3)4.2)(75.2(10 =−= Fig. 9-10

AmII CB μ

β8.45

6075.2

===

Example 9-5: (Common-Collector) Determine IE and VCE for the common-collector (emitter-follower) configuration of Fig. 9-11. Solution: Applying KVL to the input circuit:

0=+−−− EEEEBEBB VRIVRI BE II )1( += β

EB

BEEEB RR

VVI)1( ++

−=

β

Akk

μ73.45)2)(91(240

7.020=

+−

=

mAII BE 16.4)73.45)(91()1( ==+= μβ Fig. 9-11 Applying KVL to the output circuit:

0=++− CEEEEE VRIV VkmRIVV EEEECE 68.11)2)(16.4(20 =−=−=



Example 9-6: (PNP Transistor) Determine VCE for the voltage-divider bias configuration of Fig. 9-12. Solution: Testing: 210RRE ≥β )10(10)1.1)(120( kk ≥ )(100132 satisfiedkk Ω≥Ω

Vkk

kRR

VRV CCB 16.3

1047)18)(10(

21

2 −=+−

=+

=

VVVV BEBE 46.2)7.0(16.3 −=−−−=−=

mAkR

VIIE

EEC 24.2

1.146.2

====

0=+−+− CCCCCEEE VRIVRI (KVL) )( ECCCCCE RRIVV ++−= Fig. 9-12

Vkkm 16.10)1.14.2)(24.2(18 −=++−= Exercises: 1. For the fixed-biased configuration of Fig. 9-2a with the following parameters:

VCC = +12 V, β = 50, RB = 240 kΩ, and RC = 2.2 kΩ, determine: IBQ, ICQ, VCEQ, VB, VC, and VBC.

2. Given the device characteristics of Fig. 9-13a, determine VCC, RB, and RC for the

fixed-bias configuration of Fig. 9-13b. (a) (b)

Fig. 9-13



3. For the emitter bias circuit of Fig. 9-4a with the following parameters: VCC = +20 V, β = 50, RB = 430 kΩ, RC = 2 kΩ, and RE = 1 kΩ, determine: IB, IC, VCE, VC, VE, VB and VBC.

4. Design an emitter-stabilized circuit (Fig. 9-4a) at ICQ = 2 mA. Use VCC = +20 V

and an npn transistor with β =150. 5. Determine the dc bias voltage VCE and the current IC for the voltage-divider

configuration of Fig. 9-6a with the following parameters: VCC = +18 V, β = 50, R1 = 82 kΩ, R2 = 22 kΩ, RC = 5.6 kΩ, and RE = 1.2 kΩ.

6. Design a beta-independent (voltage-divider) circuit to operate at VCEQ = 8 V and

ICQ = 10 mA. Use a supply of VCC = +20 V and an npn transistor with β = 80. 7. Determine the quiescent levels of ICQ and VCEQ for the voltage-feedback circuit

of Fig. 9-7a with the following parameters: VCC = +10 V, β = 90, RB = 250 kΩ, RC = 4.7 kΩ, and RE = 1.2 kΩ.

8. Prove that )( ECB RRR +≤ β is the required condition for an optimum design of

the voltage-feedback circuit. 9. Prove mathematically that ICQ for the voltage-feedback bias circuit is approximately

independent of the value of beta. 10. Fig. 9-14 shows a three-stage circuit with a VCC supply of +20 V. GND stands for

ground. If all transistors have a β of 100, what are the IC and VCE of each stage?

iv

ov

GND

V20+

Ωk100 Ωk56.0

Ωk2 Ωk3

Ωk68.0Ωk3

Ωk50

Ωk8

Fμ10Fμ10

Fμ10

Fμ10

Fig. 9-14

University of Technology Bias Stabilization Electrical and Electronic Engineering Department Lecture Ten - Page 1 of 5


Bias Stabilization Basic Definitions: The stability of system is a measure of sensitivity of a circuit to variations in its parameters. In any amplifier employing a transistor the collector current IC is sensitive to each of the following parameters:

ICO (reverse saturation current): doubles in value for every 10oC increase in temperature.

|VBE| (base-to-emitter voltage): decrease about 7.5 mV per 1oC increase in temperature.

β (forward current gain): increase with increase in temperature. Any or all of these factors can cause the bias point to drift from the design point of operation. Stability Factors, S(ICO), S(VBE), and S(β): A stability factor, S, is defined for each of the parameters affecting bias stability as listed below:

.,

)(constVCO

C

CO

CCO

BEII

IIIS

=∂∂

=ΔΔ

=β

[10.1a]

.,

)(constIBE

C

BE

CBE

COVI

VIVS

=∂∂

=ΔΔ

=β

[10.1b]

.,

)(constVI

CC

BECO

IIS=∂

∂=

ΔΔ

=ββ

β [10.1c]

Generally, networks that are quite stable and relatively insensitive to temperature variations have low stability factors. In some ways it would seem more appropriate to consider the quantities defined by Eqs. [10.1a - 10.1c] to be sensitivity factors because: the higher the stability factor, the more sensitive the network to variations in that parameter. The total effect on the collector current can be determined using the following equation: ββ Δ+Δ+Δ=Δ )()()( SVVSIISI BEBECOCOC [10.2]



Derivation of Stability Factors for Standard Bias Circuits: For the voltage-divider bias circuit, the exact analysis (using Thevenin theorem) for the input (base-emitter) loop will result in: , 0=−−− EEBEThBTh RIVRIEand => BCE III += , ThBEThEBEC EVRRIRI =+++ )(and COBC III )1( ++= ββ ,

or COC

B IIIβ

ββ

1+−= =>

ThBEThE

COThE

C EVRRIRRI =+⎥⎦

⎤⎢⎣

⎡ ++−⎥

⎦

⎤⎢⎣

⎡ ++β

ββ

β ))(1()1( [10.3]

The partial derivation of the Eq. [10.3] with respect to ICO will result:

0))(1()1(=

++−

++⋅

∂∂

ββ

ββ ThEThE

CO

C RRRRII

ThE

ThECO RR

RRIS++++

=)1(

))(1()(ββ

[10.4a]

Also, the partial derivation of the Eq. [10.3] with respect to VBE will result:

01)1(=+

++⋅

∂∂

ββ ThE

BE

C RRVI

ThE

BE RRVS

++−

=)1(

)(β

β [10.4b]

The mathematical development of the last stability factor S(β) is more complex than encountered for S(ICO) and S(VBE). Thus, S(β) is suggested by the following equation:

ThE

ThEC

RRRRI

S++

+=

)1())(/(

)(2

11

β

ββ [10.4c]



For the emitter-stabilized bias circuit, the stability factors are the same as these obtained above for the voltage-divider bias circuit except that RTh will replaced by RB. These are:

BE

BECO RR

RRIS++++

=)1(

))(1()(ββ

[10.5a]

BE

BE RRVS

++−

=)1(

)(β

β [10.5b]

BE

BEC

RRRRI

S++

+=

)1())(/(

)(2

11

β

ββ [10.5c]

For the fixed-bias circuit, if we plug in RE = 0 the following equation will result: 1)( += βCOIS [10.6a]

B

BE RVS β

−=)( [10.6b]

1

1)(β

β CIS = [10.6c]

Finally, for the case of the voltage-feedback bias circuit, the following equation will result:

BEC

BECCO RRR

RRRIS++++++

=))(1(

))(1()(ββ

[10.7a]

BEC

BE RRRVS

+++−

=))(1(

)(β

β [10.7b]

BEC

BECC

RRRRRRI

S+++

++=

))(1())(/(

)(2

11

β

ββ [10.7c]



CCV V18+

1R

2R

Ωk36

Ωk5

CR Ωk5.7

ER Ωk5.1

iv

ov

80=βiC

oC

Example 10-1: 1. Design a voltage-divider bias circuit using a VCC supply of +18 V, and an npn silicon

transistor with β of 80. Choose RC = 5RE, and set IC at 1 mA and the stability factor S(ICO) at 3.8.

2. For the circuit designed in part (1), determine the change in IC if a change in

operating conditions results in ICO increasing from 0.2 to 10 μA, VBE drops from 0.7 to 0.5 V, and β increases 25%.

3. Calculate the change in IC from 25o to 75oC for the same circuit designed in part (1),

if ICO = 0.2 μA and VBE = 0.7 V. Solution: Part 1:

VVV CCCE 92/182/ === . )( ECCCCCE RRIVV +−= , => EC RR 5=

)5)(1(189 EE RRm +−= => Ω= kRE 5.1 . Ω== kkRC 5.7)5.1(5 .

mAII CE 1=≅ , V VkmRI EEE 5.1)5.1)(1( === . VVVV BEEB 2.27.05.1 =+=+= .

21

2

RRVRV CC

B += =>

182.2

21

2 ==+ CC

B

VV

RRR

[10.8a]

ThE

ThECO RR

RRIS++++

=)1(

))(1()(ββ => Fig. 10-1

Th

Th

RkRk++

=)5.1)(81(

)5.1)(81(8.3 => Ω= kRTh 4.4 .

21

21

RRRRRTh +

= => 1121

2 4.4R

kRR

RRR Th ==+

[10.8b]

From Eqs. [10.8a] and [10.8b]:

182.24.4

1=

Rk => . Ω= kR 361

From Eq. [10.8a]:

182.2

36 2

2 =+ Rk

R => . Ω= kR 52

Fig. 10-1 shows the final circuit.



Part 2: 8.3)( =COIS ,

AICO μμμ 8.92.010 =−=Δ .

mSkkRR

VSThE

BE 635.04.4)5.1)(81(

80)1(

)( −=+

−=

++−

=β

β ,

VVBE 2.07.05.0 −=−=Δ . 100)80(25.125.1)100/251( 112 ===+= βββ ,

Akkkkm

RRRRI

SThE

ThEC μβ

ββ 473.0

4.4)5.1)(101()4.45.1)(80/1(

)1())(/(

)(2

11 =++

=++

+= ,

2080100 =−=Δβ . ββ Δ+Δ+Δ=Δ )()()( SVVSIISI BEBECOCOC

mAm 174.0)20)(473.0()2.0)(635.0()8.9)(8.3( =+−−+= μμ . Part 3:

Since ICO, doubles in value for every 10oC increase in temperature.

Thus 510

257510

=−

=Δ

=TN , . ACICI o

CONo

CO μμ 4.6)2.0)(2()25(2)75( 5 ==⋅=

AICO μμμ 2.62.04.6 =−=Δ . Since VBE, decreases about 7.5 mV per 1oC increase in temperature. Thus CT o502575 =−=Δ , => VCV o

BE 7.0)25( =

VmCV oBE 325.0)5.7(507.0)75( =−= .

BEBECOCOC VVSIISI Δ+Δ=Δ )()( mAm 262.0)375.0)(635.0()2.6)(8.3( =−−+= μ .

Exercises: 1. Derive a mathematical expression to determine the stability factor

CCCCC VIVS ΔΔ=)( for the emitter-stabilized bias circuit.

2. Discuss and compare (by equations) between the relative levels of stability for the following biasing circuits: i. the fixed-bias circuit, ii. the emitter-stabilized bias circuit, iii. the voltage-divider bias circuit, and iv. the voltage-feedback circuit.

University of Technology BJT Switching Circuits Electrical and Electronic Engineering Department Lecture Eleven - Page 1 of 3


iV

CCV V5+

+

−CEV

CVCR

BR+

−BEV

V0V5+ V0

V5+

BJT Switching Circuits Basic Concepts: The application of transistors is not limited solely to the amplification of signals. Through proper design it can be used as a switch for computer and control applications. The circuit of Fig. 11-1a can be employed as an inverter in computer logic circuitry. Note that the output voltage VC is opposite to that applied to the base or input terminal. In addition, note the absence of a dc supply connected to the base circuit. The only dc source is connected to the collector or output side and for computer applications is typically equal to the magnitude of the "high" side of the applied signal-in this case 5V. (a) (b)

Fig. 11-1 Proper design for the inversion process requires that the operating point switch from cutoff to saturation along the load line depicted in Fig. 11-1b. For our purposes we will assume that mA when 0≈= CEOC II 0=BI μA (an excellent approximation in light of improving construction techniques), as shown in Fig. 11-1b. In addition, we will assume that 0)( ≈= satCEVCEV V rather than the typical 0.1 to 0.3 V level. When Vi = 5 V, the transistor will be "on" and the design must ensure that the circuit is heavily saturated by a level of IB greater than that associated with the IB curve appearing near the saturation level. The base current IB for the circuit of Fig. 11-1a is determined by

B

BEiB R

VVI −= [11.1]

The saturation level for collector current IC(sat) for the same circuit is defined by

C

CCsatC R

VI =)( [11.2]

The level of IB in the active region just before saturation results can be approximated by the following equation:

β

)((max)

satCB

II ≅ [11.3]

For the saturation level we must therefore ensure that the following is satisfied: (max)BB II > [11.4]



iV

CCV V10+

oVCR

BR

Ωk2.6

Ωk22050=β

iV

CCV V20−

oV

CR Ωk6.1

V4−

V4+

1R

Ωk5Ωk202R

1D 2D

Si Ge

Example 11-1: Verify that the circuit shown in Fig. 11-2 behaves like an inverter when the input switches between 0 V and +10 V. Assume that the transistor is silicon and that β = 50. Solution: It is only necessary to verify that the transistor is saturated when Vi = +10 V.

AkR

VVIB

BEiB μ3.42

2207.010=

−=

−= .

AkR

VII

C

CCsatCB μ

ββ3.32

)2.6)(50(10)(

(max) ==== .

Thus, we have , therefore the transistor is (max)BB II >saturated, and the circuit is inverter. Fig. 11-2 Example 11-2: Verify that the circuit shown in Fig. 11-3 is an inverter when the input switches between 0 V and -5 V. What minimum value of β is required? Assume that the transistor is silicon. Solution:

When , VVi 0= Vkk

kVB 8.0520)5)(4(=

+= , hence the

transistor is at cutoff, so that D1 and D2 are on and VVo 53.07.04 −=−−−= .

When , VVi 5−= Ω== kkkRTh 4205 ,

Vkkk

kkkETh 2.3

520)20)(5(

520)5)(4(

−=+

−+

++

= ,

AkR

VEITh

BEThB μ625

47.02.3=

−=

−= .

We assume the transistor is at saturation, VVo 0= , Fig. 11-3 so that D1 and D2 are off and

mAkR

VIC

CCsatC 5.12

6.120

)( === ,

ββ /5.12/)((max) mAII satCB == . For the transistor to be in saturation,

(max)BB II > => 20625

5.12)( ==>μ

β mI

I

B

satC .



Exercise: 1. Design the transistor inverter of Fig. 11-4 to operate with a saturation current of

8 mA using a transistor with a beta of 100. Use a level of IB equal to 120% of IB(max) and standard resistor values.

iV

CCV V5+

oV

CR

BR100=β

5

0

iV

t

Fig. 11-4 2. Verify that the circuit shown in Fig. 11-5 is a positive NAND when the input

switches between 0 V and +12 V. Neglect source impedance and junction saturation voltages and diode voltages in forward direction. Find the minimum value of β.

CCV V12+

oV

CR Ωk2.2

V12−

1R

Ωk15Ωk100

2R

V12+

3R

Ωk15

AV

BV

1D

2D

Fig. 11-5

University of Technology BJT Modeling and AC Equivalent Circuit Electrical and Electronic Engineering Department Lecture Twelve - Page 1 of 9


BJT Modeling and AC Equivalent Circuit Basic Concepts: The key to the transistor small-signal analysis is the use of ac equivalent circuits or models. A model is the combination of circuit elements, properly chosen, that best approximates the actual behavior of a semiconductor device (BJT) under specific operating conditions. Once the ac equivalent circuit has been determined, the graphical symbol of the device can be replaced in the schematic by this circuit and the basic methods of ac circuit analysis (mesh analysis, nodal analysis, and Thevenin's theorem) can be applied to determine the response of the circuit. There are two schools of thought in prominence today regarding the equivalent circuit to be substituted for the transistor: hybrid and re model. In summary, the ac equivalent circuit of the BJT amplifier is obtained by (see Fig. 12-1): 1. Setting all dc sources to zero and replacing them by a short-circuit equivalent. 2. Replacing all capacitors by a short-circuit equivalent. 3. Removing all elements bypassed by the short-circuit equivalents introduced by

stapes 1 and 2. 4. Redrawing the circuit in a more convenient and logical form. 5. Use the hybrid or re equivalent circuit of the BJT to complete the equivalent circuit

of the amplifier. 6. Finally, the following parameters are determined for the amplifier: a. Input impedance (Zi). b. Output impedance (Zo). c. Voltage gain (Av). d. Current gain (Ai). e. Phase relationship (θ). (a) (b)

(c)

Fig. 12-1



The Hybrid (h-parameters) Equivalent Model: For the general hybrid two-port system of Fig. 12-2: [12.1a] oii VhIhV 1211 += [12.1b] oio VhIhI 2221 +=

Fig. 12-2 where

)(0

11 Ω===

iVi

i hIVh

o

, short-circuit input impedance parameter.

)(0

12 unitlesshVVh r

Io

i

i

===

, open-circuit reverse transfer voltage ratio parameter.

)(0

21 unitlesshIIh f

Vi

o

o

===

, short-circuit forward transfer current ratio parameter.

)(0

22 ShVIh o

Io

o

i

===

, open-circuit output admittance parameter.

From the BJT hybrid equivalent circuit of Fig. 12-3, Eqs. [12.1a] and [12.1b] becomes: [12.2a] oriii VhIhV += [12.2b] ooifo VhIhI +=

Fig. 12-3



+

−SV

SR ih

+

−orVh if Ih oh/1 LR

+

−oV

oIiI

oZiZ+

−iV

Gain and Impedance Computation of the Complete Hybrid Equivalent Circuit: For the circuit of Fig. 12-4,

Fig. 12-4 the voltage gain (Av = Vo/Vi);

i

orii h

VhVI −= ,

L

oo R

VI −= , and ooifo VhIhI += =>

Lrfoii

Lf

i

ov Rhhhhh

RhVVA

)( −+

−== [12.3a]

the current gain (Ai = Io/Ii);

Lo

if

Lo

oifo Rh

IhRh

hIhI+

=+

=11

1 =>

Lo

f

i

oi Rh

hIIA

+==

1 [12.3b]

the input impedance (Zi = Vi/Ii);

i

ori

i

i

IVhh

IV

+= , and => Loo RIV −= iLrii

oLri

i

i ARhhIIRhh

IV

−=−= =>

Lo

Lrfi

i

ii Rh

Rhhh

IVZ

+−==

1 [12.3c]

the output impedance (Zo = Vo/Io when VS = 0 V);

0)( =++= oriSiS VhhRIV => iS

ori hR

VhI+

−= , and ooifo VhIhI += =>

oiS

rfooo V

hRhh

VhI+

−= =>

iS

rfo

o

oo

hRhh

hIVZ

+−

==1

[12.3d]



Types of Hybrid Parameters: Since there are three types of BJT configuration (CE, CC, and CB), there are three different ways that the input and output can be defined and therefore three corresponding sets of h-parameters as shown in Table 12-1. If all of the h-parameters values in one configuration are known, then the values corresponding to any other configuration can be determined. The common-emitter values of the h-parameters are the ones most often given.

Table 12-1 BJT configuration h-parameters sets

1 Common-Emitter hie , hfe , hre , hoe 2 Common-Collector hic , hfc , hrc , hoc 3 Common-Base hib , hfb , hrb , hob

The hybrid equivalent circuits of the CE and CB transistor configuration are shown in Fig. 12-5 (a) and (b) respectively.

(a)

(b)

Fig. 12-5



Table 12-2 lists typical parameter values in each of the three transistor configurations (CE, CC, and CB) for the broad range of transistors available today.

Table 12-2 h-parameters CE CC CB

hi 1kΩ 1kΩ 20kΩ hr 2.5×10-4 ≈ 1 3.0×10-4 hf 50 −50 −0.98 ho 25 μS 25 μS 0.5 μS

1/ho 40 kΩ 40 kΩ 2 MΩ Graphical Determination of the CE Hybrid Parameters: The parameters hie and hre are determined from the input or base characteristics, while the parameters hfe and hoe are obtained from the output or collector characteristics as shown in Fig. 12-6.

Ω=ΔΔ

==

kivh

constVb

beie

CE

5.1.

4

.

104 −

=

×=ΔΔ

=constIce

bere

Bvvh

100.

=ΔΔ

==constVb

cfe

CEiih S

vih

constIce

coe

B

μ33.

=ΔΔ

==

Fig. 12-6



ieh bfeIh LR+

−oV

cIbI

oZiZ+

−iV

b

e

c

e

oZ ′

oI

For the transistor whose characteristics have appeared in Fig. 12-6, the resulting hybrid small-signal equivalent circuit is shown in Fig. 12-7.

Fig. 12-7 The typical values of h-parameters for CE transistor configuration are shown in Table 12-3.

Table 12-3 hxe parameters Min. Max. Unit

Input impedance hie 0.5 7.5 kΩ Voltage feedback ratio hre 0.1 8.0 ×10-4

Small-signal current gain hfe 20 250 − Output admittance hoe 1.0 30 μS

Approximate CE Hybrid Equivalent Model: Since hre is normally a relatively small quantity, its removal is approximated by hre ≈ 0 and hreVce = 0, resulting in a short-circuit equivalent for the feedback element. The resistance determined by 1/hoe is often large enough to be ignored in comparison to a parallel load permitting its replacement by an open-circuit equivalent for the CE model as shown in Fig. 12-8.

Fig. 12-8 For the circuit of Fig. 12-8, , and . iei hZ = ∞=oZ

feb

ci h

IIA == , and

i

oi

ie

Lfe

ieb

Lc

ieb

Lo

i

ov Z

ZAhRh

hIRI

hIRI

VVA

′−=−=−=−== .



The re Equivalent Model: CB Transistor Configuration: From Fig. 12-9, the input impedance at the emitter of CB transistor configuration (dynamic resistance of the forward diode) can de determined by:

E

e ImVr 26

= [12.4]

the output impedance at the collector (dynamic resistance of the reverse diode) is: ∞≈or also; ei rZ = , and ∞=oZ . LeLcLoo RIRIRIV α=−−=−= )( , and eeiei rIZIV == =>

e

L

e

L

i

ov r

RrR

VVA ≈==

α .

ec II α= , and e

c

i

oi I

IIIA −== =>

1−≈−= αiA . (a) (b) (c) (d) (e)

Fig. 12-9



CE Transistor Configuration: From Fig. 12-10; bc II β= , bbbbbce IIIIIII βββ ≈+=+=+= )1( , and ebeebe rIrIV β≈= .

eb

be

i

ii r

IV

IVZ ⋅=== β .

∞≈= oo rZ . LbLcLoo RIRIRIV β−=−=−= ,

e

L

eb

Lb

be

o

i

ov r

RrIRI

VV

VVA −=−===

ββ

.

ββ====

b

b

b

c

i

oi I

III

IIA .

(a) (b) (c) (d) (e) (g)

Fig. 12-10



Hybrid Versus re Model: The hybrid versus re model for CE and CB transistor configurations are shown in Figs. 12-11 (a) and (b) respectively.

(a)

(b)

Fig. 12-11 Approximate Conversion Formulas for Hybrid and re Models: The approximate conversion formulas for hybrid and re models for CB and CC configurations are listed in Table 12-4.

Table 12-4 CB Configuration CC Configuration

efeieib rhhh ≅+≅ )1( eieic rhh β≅≅

refeoeierb hhhhh −+≅ )1( 11 ≅−≅ rerc hh α+ −≅−≅ )1( fefefb hhh β−≅+−≅ )1( fefc hh

)1( feoeob hhh +≅ ooeoc rhh /1≅≅ Exercise: Given IE = 1.3 mA, β = 100, and ro = 40 kΩ, sketch:

1. The CE and CB hybrid equivalent models. 2. The CE and CB re equivalent models.

University of Technology BJT Small-Signal Analysis Electrical and Electronic Engineering Department Lecture Thirteen - Page 1 of 12


CCV+

1R

2R

CR

ER

SR+

−sV

SC

EC

LR

CC

+

−oV

+

−iV

iI

oIC

E

B oZ ′oZ

bZiZ

inZ

LR+

−oV

oZiZ+

−iV

oZ ′

oI

bIβ

cIbIb c

e bfe Ihiehor

oeh/1R′SR

+

−sV

CR

iI

bZ

inZ

erβ

BJT Small-Signal Analysis Common-Emitter Configuration: The voltage divider circuit of Fig. 13-1 includes an emitter resistor (RE) that may or may not be bypassed by an emitter capacitor (CE) in the ac domain.

Fig. 13-1 Bypassed (absence of RE): For the ac equivalent circuit of Fig. 13-2,

Fig. 13-2 Using re equivalent model: Input impedance: 21 RRR =′ eb rZ β= ebi rRZRZ β′=′= )( eSiSin rRRZRZ β′+=+=



Output impedance: Approximate (neglecting ro); Exact (including ro); Co RZ = oCo rRZ = CLoLo RRZRZ ==′ oCLo rRRZ =′ Voltage gain: Approximate (neglecting ro); Exact (including ro);

)( CLboco RRIZIV β−=′−= e

oCLv r

rRRA −=

e

i

b

ib r

VZVI

β==

e

CL

i

ov r

RRVVA −==

Si

iv

s

i

i

o

s

ov RZ

ZAVV

VV

VVA

s +⋅=⋅==

Current gain: Approximate (neglecting ro); Exact (including ro);

i

b

b

c

c

o

i

oi I

III

II

IIA ⋅⋅==

))()](([ eLCLCo

Coi rRRRRRr

RRrAβ

β+′++

′=

bLC

C

ZRR

RRR

+′′

⋅⋅+

= β

))(( eLC

C

rRRRRR

ββ

+′+′

=

iS

Si

s

i

i

o

s

oi ZR

RAII

II

IIA

s +⋅=⋅==

As an option:

i

Li

i

L

i

o

ii

Lo

i

ov Z

RAZR

II

ZIRI

VVA ⋅−=⋅−=

−==

L

iv

L

i

i

o

ii

Lo

i

oi R

ZARZ

VV

ZVRV

IIA ⋅−=⋅−=

−==

Phase relationship:

The negative sign in the resulting equation for Av reveals that a 180o phase shift occurs between the input and output voltage signals.



LR+

−oV

oZiZ+

−iV

oZ ′

oI

erβ bIβ

cIbIb c

e bfe IhiehR′SR

+

−sV

CR

iI

bZ

EReI

Using hybrid equivalent model: Approximate (neglecting hoe); Exact (including hoe); ieb hZ =

ie

CLfev h

RRhA

)(−=

ie

oeCLfev h

hRRhA

)/1(−=

))(( ieLC

Cfei hRRR

RRhA

+′+

′=

))()]((/1[/

ieLCLCoe

oeCfei hRRRRRh

hRRhA

+′++

′=

Unbypassed (include of RE): For the approximate ac equivalent circuit ( Ω∞≈= oeo hr /1 ) of Fig. 13-3,

Fig. 13-3 Using re equivalent model: Input impedance: ])1([ EebEeebi RrIRIrIV ++=+= βββ

EEeEeb

ib RRrRr

IVZ ββββ ≈+≈++== )()1(

EEeEebi RRRrRRrRZRZ ββββ ′≈+′≈++′=′= )(])1([ Output impedance: Co RZ = CLoLo RRZRZ ==′ Voltage gain: )( CLboco RRIZIV β−=′−=

)( Ee

i

b

ib Rr

VZVI

+==β



SR+

−sV

SC

LR

CC

+

−oV

+

−iV

iI oI

B

oZ ′oZiZ

ER CR

EEV CCV

CE

bZ

E

CL

Ee

CL

i

ov R

RRRrRR

VVA −≈

+−==

Current gain:

i

b

b

c

c

o

i

oi I

III

II

IIA ⋅⋅==

bLC

C

ZRR

RRR

+′′

⋅⋅+

= β

))(()]()[( ELC

C

EeLC

C

RRRRRR

RrRRRRR

ββ

ββ

+′+′

≈++′+

′=

Phase relationship: Vo and Vi are out-of-phase by 180o. Using hybrid equivalent model: EfeEfeieEfeieb RhRhhRhhZ ≈+≈++= )1(

E

CL

Efeie

CLfev R

RRRhh

RRhA −≈

+−=

)(

))(())(( EfeLC

Cfe

EfeieLC

Cfei RhRRR

RRhRhhRRR

RRhA

+′+

′≈

++′+

′=

Common-Base Configuration: The common-base configuration of Fig. 13-4 is characterized as having a relatively low input and a high output impedance and a current gain less than 1. The voltage gain, however, can be quite large.

Fig. 13-4



LR+

−oV

oZiZ+

−iV

oZ ′

oI

er eIα

cIeIe c

bER

SR+

−sV

CR

iI

bZ

LR+

−oV

oZiZ+

−iV

oZ ′

oI

ibh efb Ih

cIeIe c

bER

SR+

−sV

CR

iI

bZ

Using re equivalent model: For the approximate ac equivalent circuit ( Ω∞≈or ) of Fig. 13-5, Input impedance: eb rZ = eEi rRZ = [low] Output impedance: [high] Co RZ = CLo RRZ =′ Fig. 13-5 Voltage gain: )( CLeoco RRIZIV α=′= eie rVI /=

e

CL

e

CLv r

RRr

RRA ≅=

)(α [high]

Current gain:

eE

E

LC

C

i

e

e

c

c

o

i

oi rR

RRR

RII

II

II

IIA

+⋅⋅

+−=⋅⋅== α

))(( eELC

EC

rRRRRR

++−=

α [less than 1]

Phase relationship: Vo and Vi are in-phase. Using hybrid equivalent model: For the approximate ac equivalent circuit ( Ω∞≈obh/1 ) of Fig. 13-6, ibb hZ = ibEi hRZ =

ib

CLfbv h

RRhA

)(−=

))(( ibELC

ECfbi hRRR

RRhA

++= Fig. 13-6

[hfb: -ve quantity]



CCV+

BR

ER

SR+

−sV

SC

LR

CC

+

−oV

+

−iV

iI

oI

C

E

B

oZ ′oZ

bZiZ

LR+

−oV

oZ

iZ+

−iV

oI

erβ bIβ

cIbIb c

e bfe IhiehBR

SR+

−sV

iI

bZ

ER

eI

Common-Collector (Emitter-Follower] Configuration: When the output is taken from the emitter terminal of the transistor, an amplifier circuit is referred to as emitter-follower as shown in Fig. 13-7. The emitter-follower configuration is frequently used for impedance-matching purposes. It presents a high impedance at the input and a low impedance at the output. Also, the output voltage is always slightly less than the input signal with an in-phase relationship between them.

Fig. 13-7 Using re equivalent model: For the ac equivalent circuit of Fig. 13-8,

Fig. 13-8 Input impedance: EL RRR =′ ])1([ RrIRIrIV ebeebi ′++=′+= βββ RrIVZ ebib ′++== )1(/ ββ RRre ′≈′+≈ ββ )( [high] bBi ZRZ =



BRSR

+

−sV

Thevenin

oZ ′+

−oV LRER

oZ

oIeIβ/SR er

+

−sV

feie hh /feS hR /+

−iV

Output impedance: 0=′−−− RIrIRIV eebSis β [KVL] For the circuit of Fig. 13-9a,

BSTh RRR = , and BS

BsTh RR

RVE+

=

where RB >> RS => , , and STh RR ≈ sTh VE ≈ bi II ≈ (a) 0)1( =′+−−− RIrIRIV bebSbs ββ

RrR

VIeS

sb ′+++=

)1(ββ

RrR

VIIeS

sbe ′+++

+=+=

)1()1()1(ββ

ββ

RrR

V

eS

s

′++≈

β/ (b)

Fig. 13-9 Drawing the circuit to "fit" the above last equation will result in the configuration of Fig. 13-9b. Thus

)/( eSEo rRRZ += β [low] oLo ZRZ =′ Voltage gain:

eee

e

i

ov rR

RrRI

RIVVA

+′′

=+′′

==)(

[less than 1]

ess

ov rRR

RVVA

s ++′′

==β/

Current gain:

bB

B

LE

E

i

b

b

e

e

o

i

oi ZR

RRR

RII

II

II

IIA

+⋅+⋅

+−=⋅⋅== )1(β

))(( RRRR

RR

BLE

BE

′++−≈

ββ [high]

Phase relationship: Vo and Vi are in-phase.



CCV

1R

2R

CR

2ER

SR+

−sV

SC

EC

LR

CC

+

−oV

+

−iV

iI

oI

oZ ′oZ

bZiZΩ750

mV25

Ωk91

Ωk10 1ER Ω180

Ω820

Ωk12

Ωk3

V20+

Using hybrid equivalent model: RhRhhZ fefeieb ′≈′++= )1( feieSEo hhRRZ /)( +=

feie

v hhRRA

/+′′

=

feies

v hhRRRA

s /)( ++′′

=

))(( RhRRR

RRhA

feBLE

BEfei ′++

−=

Example 13-1: For the BJT amplifier circuit of Fig. 13-10 with the following parameters: VBE = 0.7 V, β = hfe ≈ 250, and ro = 1/hoe ≈ ∞ Ω, determine: (a) re, and dc output voltage (VC). (b) hie, Zb, Zi, Zo, and oZ ′ . (c) Av = Vo/Vi, and Ai = Io/Ii. (d) so VV / , and ac output voltage (Vo). vA

s=

Fig. 13-10



CCV

1R

2R

CR

ER

SR+

−sV

SCLR

CC

+

−oV

+

−iV

iI

oI

oZ ′oZ

bZiZ

V20+

Solution: Testing: 210RRE ≥β , Ω=+=+= kkkRRR EEE 182.018.021 , )10(10)1(250 kk ≥ , kk 100250 > Satisfied,

Vkk

kRRRVV CC

B 1.989110

)10(2021

2 =+

=+⋅

= , mAkR

VVIE

BEBE 28.1

17.098.1=

−=

−= ,

Ω=== 3.2028.1

2626m

mImVrE

e , mAII EC 28.1=≈ , and

VkmRIVV CCCCC 16.61)3(28.120 =−=−= . Ω=== krh eie 075.5)3.20(250β ,

Ω=+=++= kRhhZ Efeieb 075.5)1( 1 kk 26.05)18.0(251 , Ω===′ kkkRRR 01.9109121 , Ω==′= kkkZRZ bi 64.726.5001.9 ,

Ω== kRZ Co 3 , and Ω===′ kkkRRZ CLo 4.2312 .

94.1126.50

)4.2(250−=−=

′−=

kk

ZZh

Ab

ofev , and .6.7

12)64.7(94.11==−=

kk

RZAA

L

ivi

87.1075.064.7

)64.7(94.11−=

+−

=+

==kkk

RZZA

VVAA

Si

iv

s

ivvs

, and

mVmVAV svo s75.271)25(87.10 −=−=⋅= .

Example 13-2: Design the BJT amplifier circuit shown in Fig. 13-11 to have a voltage gain magnitude of 4, Zi = 3.37 kΩ, Zo = 3 kΩ, and oZ ′ = 2kΩ. Assume that the transistor is silicon with 100=β , hie = 1 kΩ, ro = 1/hoe ≈ ∞ Ω, and 210RRE >β .

Fig. 13-11



CCV

SR

ER

CC

LR

V9−

Ω20

EEV V4+

SC

CR

+

−sV iV

+

−

oV+

−

oZ

iZ

oZ

mV10

Solution:

Ω== kZR oC 3 , Ω=⇒=⇒=′ kRkRkRRZ LLCLo 632 .

Ω≈⇒≈⇒′

≈ kRRR

ZA EEE

ov 5.024 .

Ω=⇒=⇒= 101001 eeeie rrkrh β , mAII

mImVr E

EEe 6.2261026

=⇒=⇒= .

VkmRIV EEE 3.1)5.0(6.2 === , VVVV BEEB 27.03.1 =+=+= .

1.020210

21

2

21

2

21

22 =

+⇒

+=⇒

+=⇒>

RRR

RRR

RRR

VVRR

CC

BEβQ ----- [a]

Ω=+=++= kkkRhZ Eieb 5.51)5.0(1011)1(β .Ω=′⇒′=⇒′= kRkRkZRZ bi 6.35.5137.3 .

21

2

121

2121

6.3RR

RR

kRR

RRRRR+

=⇒+

==′ ----- [b]

From Eqs. [a] and [b]: Ω=⇒= kRR

k 361.06.31

1.

From Eq. [a]: Ω=⇒=+

kRRk

R 41.036 2

2

2 .

Example 13-3: Complete the design of the BJT amplifier circuit shown in Fig. 13-12 for a voltage gain of 125, Zo = 2.4 kΩ, = 2 kΩ. Assume that oZ ′ 985.0=α , |VBE| = 0.7 V, and ro = 1/hob ≈ ∞ Ω. Calculate , and Vo. svA

Fig. 13-12



CCV+

CR

ER

SR+

−s

SC

EC

LR

CC

V

+

−oV

+

−iV

iI

oI

oZ ′oZ

bZiZ

1FR 2FR

FC

CCV+

1R

2R

CR

ER

SR+

−sV

SC

LR

CC

+

−oV

+

−iV

iI

oI

oZ ′oZ

bZiZ

Solution:

Ω== kZR oC 4.2 . Ω=⇒=⇒=′ kRkRkRRZ LLCLo 124.22 .

Ω=⇒=⇒′

= 76.15)2(985.0125 eee

ov r

rk

rZA α .

mAII

mImVr E

EEe 65.12676.1526

=⇒=⇒= .

Ω=−

=−

= kmI

VVRE

BEEEE 2

65.17.04 .

Ω=== 64.15276.15 kRrZ Eei .

552064.15

)64.15(125=

+=

+=

si

ivv RZ

ZAAs

.

mVmVAV svo s550)10(55 ==⋅= .

Exercises:

1. For each one of the circuits shown in Fig. 13-13, write a mathematical expression to determine each of the following parameters by using hybrid or re equivalent model. (a) Zb and Zi. (b) Zo and oZ ′ . (c) Ai and Av.

(a) (b)

Fig. 13-13



2. For the common-base amplifier of Fig. 13-14, determine the following parameters using the complete hybrid equivalent model and compare the results to these obtained using the approximate model. (a) Zb and Zi. (b) Zo and oZ ′ . (c) Ai and . (d) Ai and .

svAsiA

SR+

−sV

SC

LR

CC

+

−oV

+

−iV

iI oI

oZ ′oZiZ

ER CR

EEV CCV

bZΩk1Ωk3

V6 V12

Ωk3 Ωk2.8

Ω= khie 6.14102 −×=reh

110=fehShoe μ20=

Fig. 13-14

3. Complete the design of the BJT amplifier circuit shown in Fig. 13-15 for a voltage gain magnitude of 205, Zi =1.5k Ω, and oZ ′= 3.2 kΩ. Assume that 100=β , VBE = 0.7 V, RF1/RF2 =1.95, and ro = 1/hoe ≈ ∞ Ω. Sketch Vo to the same time scale as Vs.

CCV

CR

SR

+

−sV

SCLR

CC

+

−oV

+

−iV

iI

oI

oZ ′oZ

bZiZ

1FR 2FR

FC

Ωk1

Sinwt2 mV

V10+

Fig. 13-15

University of Technology Frequency Response of BJT Amplifiers Electrical and Electronic Engineering Department Lecture Fourteen - Page 1 of 8


)(Hzf

dB0,1dB3,707.0 −

)(, dBGAv

Lf

C

R+

−oV

+

−iV

Frequency Response of BJT Amplifiers Low-Frequency Response of BJT Amplifiers: For the high-pass filter circuit of Fig. 14-1a, the output and the input voltages are related by the voltage-divider rule in the following manner:

C

io XR

RVV+

= ,

with the magnitude of Vo determined by

22C

io

XR

VRV

+

⋅= .

For special case where XC = R,

io VV2

1= , and

RXi

ov CV

VA

==== 707.0

21 .

In "deciBel" (dB):

dBAdBG v 32

1log20log20)( 1010−=== .

(a) (b)

Fig. 14-1 At the frequency of witch XC = R, the output will be 70.7 % of the input (a 3 dB drop in gain, see Fig. 14-1b) for the RC circuit. The frequency (fL) at witch this occurs is determined from:

RfCC

X C ===πω 211 =>

RC

fL π21

= fL: the low-cutoff frequency.



CCV+

1R

2R

CR

ER

SR+

−sV

SC

EC

LR

CC

+

−oV

+

−iV

iI

oIC

E

B oR

iR

eR

The Capacitors CS, CC, and CE will determine the lower-cutoff frequency (fL) of the loaded voltage divider BJT bias configuration shown in Fig. 14-2, but the results can be applied to any BJT configuration. For the amplifier circuit of Fig. 14-2: The cutoff-frequency of CS,

SiS

L CRRf

S )(21+

=π

where iei hRR ′= , and 21 RRR =′ . The cutoff-frequency of CC,

CoL

L CRRf

C )(21+

=π

Fig. 14-2

where oeCo hRR /1= . The cutoff-frequency of CE,

Ee

L CRf

E π21

=

where 1+

+′=

fe

ieSEe h

hRRR , and

RRR = . SS ′′ The lower-cutoff frequency, ],,.[

ECS LLLL fffMaxf =



i

ov V

VA =+

−oV

+

−iV

iI oI

FC

iMCoMC

i

ov V

VA =+

−oV

+

−iV

FZ2I

iI 1I

iZ iR oR oZ

oI

Miller's Theorem and Its Dual: For the circuit of Fig. 14-3a,

i

ii Z

VI = , i

i

RVI =1 , and

)1/()1(

2vF

i

F

iv

F

ivi

F

oi

AZV

ZVA

ZVAV

ZVVI

−=

−=

−=

−= .

=> 21 IIIi +=)1/( vFi

i

i

i

AZVi

RV

ZV

−+= =>

)1/(111

vFii AZRZ −+= .

when => FF RZ =iMii RRZ

111+= , where

v

FM A

RRi −=

1.

As shown in Fig. 14-3b,

when => FCF XZ =

iMCii XRZ111

+= , where Fvv

CC CAA

XX F

iM )1(1

1 −=

−=

ω =>

FvM CACi

)1( −= (a) (b)

Fig. 14-3 In a similar way,

)/11/(

111

vFoo AZRZ −+= =>

v

FM A

RRo /11−= , and

Fvv

CC CAA

XX F

oM )/11(1

/11 −=

−=

ω =>

FvM CACo

)/11( −= The above shows us that: For any inverting amplifier (phase shift of 180o between input and output resulting in a negative value for Av), the input and output capacitance will be increased by a Miller effect capacitance sensitive to the gain of the amplifier and the interelectrode capacitance connected between the input and output terminals of the active device.



)(Hzf

dB0,1dB3,707.0 −

)(, dBGAv

Hf

C

R

+

−oV

+

−iV

CCV+

1R

2R

CR

ER

SR

+

−sV

SC

EC

LR

CCC

E

B

beC

bcC

ceC

oWC

iWC

High-Frequency Response of BJT Amplifiers: A frequency response of the low-pass filter circuit of Fig. 14-4a is given by Fig. 14-4b, where the high-cutoff frequency is determined from:

RC

fH π21

= fH: the high-cutoff frequency.

(a) (b)

Fig. 14-4 At the high-frequency end, there are two factors that will define the -3 dB point: the circuit capacitance (parasitic and introduced) and the frequency dependence of hfe. Circuit (Capacitances) Parameters: In high-frequency region the capacitive elements of the importance are the inter-electrode (between terminals) capacitances internal to the active device and the wiring capacitance between leads of the circuit. In Fig. 14-5, the various parasitic capacitances (Cbe, Cbc, and Cce) of the transistor have been included with the wiring capacitances ( and C ) introduced during construction.

iWCoW

Fig. 14-5



LRbIβ

SR

+

−sV oR oCiCiR

oV

iThRoThR

ii MbeWi CCCC ++=oo MceWo CCCC ++=

+

−oThE

oThR

oC

iThR

+

−iThE iC

The high-frequency equivalent model for the amplifier circuit of Fig. 14-5 appears in Fig. 14-6. Note the absence of the capacitors CS, CC, and CE, which are all assumed to be in the short circuit state at these frequencies.

Fig. 14-6 For the circuit of Fig. 14-6: The input high cutoff frequency,

iTh

H CRf

ii π2

1=

where iSTh RRR

i= , and iei hRRR 21= .

bcvbeWMbeWi CACCCCCCiii

)1( −++=++= . The output high cutoff frequency,

oTh

H CRf

oo π2

1=

where oLTh RRR

o= , and oeCo hRR /1=

bcvceWMceWo CACCCCCCooo

)/11( −++=++= . The higher-cutoff frequency, ],.[

oi HHH ffMinf =



CCV

1R

2R

CR

ER

SR+

−sV

SC

EC

LR

CC

Ωk1 Fμ10

Ωk40

Ωk10

Ωk4

Ωk2 Fμ20

Fμ1Ωk2.2

V20+

100=β

hfe (β) Variation: The beta cutoff frequency (fβ) is another important transistor cutoff frequency. The fβ, the frequency where the β of the transistor drop to 0.707 of its low-frequency value, is given by

)(2

1

bcbee CCrf

+≅

πββ

If the frequency of operation is increased above the fβ of the transistor, the β will continue to decrease. Eventually, we find a frequency where the β = 1; this frequency is called the fT of the transistor. The fT of a transistor is much higher than the fβ. The relation between these two frequencies is BWhff feT ⋅≈⋅≅ ββ fT: the gain-bandwidth product frequency. Finally, in data sheet, the CB high-frequency parameters rather than CE parameters are often specified for a transistor. The following equation permits a direct conversion for determining fβ if fα and α are specified. )1( ααβ −= ff Example 14-1: For the BJT amplifier circuit shown in Fig. 14-7, with the following parameters: Cbe = 36 pF, Cbc = 4 pF, Cce = 1 pF, = 6 pF, C = 8 pF, and ro = 1/hoe = ∞ Ω.

iWCoW

1. Determine fL, fH, BW, fβ, and fT. 2. Sketch the frequency response.

Fig. 14-7



Solution: Testing: 210RRE ≥β , )10(10)2(100 kk ≥ , Ω>Ω kk 100200 Satisfied.

Vkk

kRRRVV CC

B 41040

)10(20

21

2 =+

=+⋅

= , .65.12

7.04 mAkR

VVRVI

E

EBB

E

EE =

−=

−==

Ω=== 76.1565.1

2626m

mImVrE

e , Ω=== krh eie 58.1)76.15(100β .

9076.1542.2

−=−=−=kk

rRR

Ae

CLvmid

.

Ω=== kkkkhRRR iei 32.158.1104021 ,

HzkkCRR

fSiS

LS7

)10)(32.11(21

)(21

=+

=+

=μππ

.

Ω== khRR oeCo 4/1 ,

HzkkCRR

fCoL

LC26

)1)(42.2(21

)(21

=+

=+

=μππ

.

Ω===′ kkkkRRRR SS 89.01040121 ,

Ω=+=+′

= 35.24]76.1510089.0[2][ kkrRRR e

SEe β

.

HzCR

fEe

LE327

)20)(35.24(21

21

===μππ

.

The lower-cutoff frequency, ],,.[ECS LLLL fffMaxf =

HzMax 327]327,26,7.[ == .

Ω=== kkkRRR iSThi57.032.11 .

pFpppCACCCCCC bcvbeWMbeWi iii406)4)(901(366)1( =+++=−++=++= .

kHzpkCR

fiTh

Hi

i732.687

)406)(57.0(21

21

===ππ

.

Ω=== kkkRRR oLTho42.142.2 .

pFpppCACCCCCC bcvceWMceWo ooo13)4)(90/11(18)/11( =+++=−++=++= .

MHzpkCR

foTh

Ho

o622.8

)13)(42.1(21

21

===ππ

.

The higher-cutoff frequency, ],.[oi HHH ffMinf =

kHzMkMin 732.687]622.8,732.687.[ == . The bandwidth, kHzkffBW LH 405.687327732.687 =−=−= .



The beta cutoff frequency, )(2

1

bcbee CCrf

+=

πββ

MHzpp

52.2)436)(76.15)(100(2

1=

+=

π.

The gain-bandwidth product, MHzMffT 252)52.2(100 ==⋅= ββ . The frequency response for the low- and high-frequency regions, bandwidth, beta cutoff frequency, and gain-bandwidth product frequency are shown in Fig. 14-8.

10 100 1k 10k 100k 1M 10M10

100M

dBAA

midv

v

f (log scale)- 5

- 10

- 15

BW

- 3 dB

SLfCLf

ELfiHf βf

oHf

Tf

Lf Hf

Fig. 14-8 Exercise: For the BJT amplifier circuit of Fig. 14-9, determine the lower- and higher-cutoff frequencies.

SR+

−sV

SC

LR

CC

ER CR

EEV CCV

Ωk1.0 Ωk2.1

V4 V16

Ωk3.3 Ωk7.4

Fμ10Fμ10

80=βpFCpFCpFC

ce

be

bc

122418

===

pFC

pFC

o

i

W

W

10

8

=

=

Fig. 14-9

Part II Lectures 8-14 Bipolar Junction Transistors (BJTs) and ......The dc biasing is necessary to...

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Transcript of Part II Lectures 8-14 Bipolar Junction Transistors (BJTs) and ......The dc biasing is necessary to...