١ of 45 MANF360 Ch.4 Biasing of BJTs

MANF360

Electronics and Instrumentation

CHAPTER 4

DC Biasing of BJTs

Prof. Ismail Mohammed Hafez

Electronics and Communication Department College of Engineering

Ain Shams University (ASU)

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Chapter Contents

4.1 Introduction 4.2 Operating Point 4.3 Fixed Bias Circuit 4.4 Emitter Stabilized Bias Circuit 4.5 Voltage Divider Bias 4.6 Design Operations

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4.1 Introduction • The term biasing means that for the transistor to be utilized as an

amplifier, a fixed level of dc voltage and current has to be stabilized. • The analysis or design of a transistor amplifier requires a knowledge

of both dc and ac response of the system. • The analysis or design of any electronic amplifier has two

components: the dc portion and the ac portion. • The superposition theorem is applied and the investigation of the dc

conditions can be totally separated from the ac response. • The improved output ac power level is the result of a transfer energy

from the applied dc supplies. • This chapter is concerned with the dc level of operation of the

transistor, while the ac analysis will be studied in the next course. • It is very important to remember the transistor relationships that are

derived in Chapter 3:

VBE = 0.7 V (4.1)

IE = IC + IB (4.2)

IC = β IB = αIE , α = β / (β +1) and β = α / (1- α) (4.3a)

IE = IC + IB = IB (β + 1) ≅ IC (4.3b)

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4.2 Operating Point

• For transistor amplifiers, the dc current and voltage determine the operating point or quiescent point (Q-point) on the transistor characteristics.

• This (Q-point) defines the region that will e employed for amplification of the applied signal. Various operating points are shown in Fig. 4.1.

Notes (Refer to Fig. 4.1): 1. If no bias are used, the device is initially completely off, resulting in a Q-point

at A which means zero current through the device and zero voltage across it. 2. For point B, the device allows amplifying both positive and negative input

signals without driving the device into cutoff or saturation regions. 3. Point C raises some concern about the nonlinearities introduced by the fact

that the spacing between IB curves is rapidly changing in this region. 4. Point D sets the device operation point near the maximum voltage and power

level. 5. Therefore, Point B seems to be the best operating point in terms of linear gain

and largest possible voltage and current swing. 6. As discussed earlier in Chapter 3, the BJT operating regions are as follows: a) Cutoff region operation: BEJ reverse biased and BCJ reverse biased. b) Linear region operation: BEJ forward biased and BCJ reverse biased. c) Saturation region operation: BEJ forward biased and BCJ forward biased.

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4.2 Operating Point (Continued)

Fig. 4.1 Various operating points within the limits of operation of a transistor 3/5/2012

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4.3 Transistor Fixed-Bias Circuit • Fixed bias of Fig. 4.2 provides a relatively straightforward and simple

introduction to transistor dc bias analysis employing npn transistor. • The equations and calculations apply equally well to pnp transistor

configuration by changing all current directions and voltage polarities. • For the dc analysis the network can be isolated from the indicated ac levels

by replacing the capacitors, C1 and C2, with an open circuit equivalent as shown in Fig. 4.3.

Fig. 4.2 Fixed-bias circuit dc and ac signals

Fig. 4.3 DC equivalent of Fig.4.2 3/5/2012

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4.3.1 Analytical Method for Transistor Circuit Anal ysis

Forward Bias of Base Emitter • Consider the Base – Emitter loop shown in Fig. 4.4, writing KVL we

have: VCC = IB RB + VBE The base current IB is given by IB = (VCC – VBE) / RB (4.4) Note: When the transistor is on VBE = 0.7 V Collector – Emitter Loop • The collector current is given by: IC = β IB • Apply KVL for the Collector-Emitter loop of Fig 4.5: VCE + IC RC = VCC (4.5) • VCE is given by: VCE = VCC – IC RC (4.6) • Note that: VCE = VC – VE = VC since VE = 0 (4.7) VBE = VB – VE = VB since VE = 0 (4.8)

4.3 Transistor Fixed-Bias Circuit (Continued)

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Fig. 4.5 Collector-emitter loop

4.3 Transistor Fixed-Bias Circuit (Continued) 4.3.1 Analytical Method for Transistor Circuit Anal ysis (Continued)

Fig. 4.4 Base-emitter loop

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Example 4.1: Consider the circuit shown in Fig. 4.6, if β =50, analyze this circuit

analytically and then determine: a) IBQ, and ICQ

b) VCEQ

c) VB and VC

d) VBC then determine the transistor region of operation.

Fig. 4.6 dc fixed-bias circuit for Example 4.1.

4.3 Transistor Fixed-Bias Circuit (Continued) 4.3.1 Analytical Method for Transistor Circuit Anal ysis (Continued)

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Example 4.1 Solution:

Forward Bias of Base Emitter a) From Equ. (4.4) IBQ = (VCC – VBE)/ RB = (12 – 0.7)/240kΩ = 47.08 µA

Collector – Emitter Loop ICQ = β IC = (50) x 47.08 = 2.35 mA b) From Equ. (4.6) VCEQ = VCC – ICRC = 12 –(2.35*2.2 x 103) = 6.83 V c) VB = VBE = VB – VE = 0.7 V d) VC = VCE = VC – VE = VC = 6.83 V VBC = VB – VC = 0.7 – 6.83 V = – 6.13 V

• Therefore VBE is positive, hence B-E junction is forward biased. VBC is negative, hence B-C junction is reverse biased. The transistor is working in active or linear region.

4.3 Transistor Fixed-Bias Circuit (Continued) 4.3.1 Analytical Method for Transistor Circuit Anal ysis (Continued)

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4.3.2 Load Line Method Transistor Circuit Analysis • Consider the circuit shown in Fig. 4.7 (a) and the transistor

characteristics shown in Fig.4.7 (b) • From Equ. (4.4), find IBQ = (VCC – VBE) / RB to determine the IB line

on the characteristics .

Fig. 4.7 Load-line analysis: (a) the network; (b) the device characteristics.

4.3 Transistor Fixed-Bias Circuit (Continued)

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• The output equation (4.6) is : VCE = VCC – IC RC

• This also called the load line equation, plot this equation on the characteristics as follows:

as IC = 0 gives VCE = VCC

as VCE = 0 gives IC = VCC/RC

• Draw the load line on the transistor characteristics as shown in Fig. 4.8. • From the graph find VCEQ and ICQ and β.

Fig. 4.8 Fixed-bias Load-line

4.3 Transistor Fixed-Bias Circuit (Continued) 4.3.2 Load Line Method Transistor Circuit Analysis (Continued)

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Notes: • IB is changed by varying RB, the Q-points moves up or down as

shown in Fig.4.9 • If VCC is fixed and RC changed, the load line moves as in Fig. 4.10 • If RC is fixed and VCC is varied, the load line shifts as in Fig. 4.11

Fig. 4.9 Movement of the Q-point with increasing levels of IB.

Fig. 4.10 Effect of an increasing levels of RC on the load line and the Q-point.

Fig. 4.11 Effect of lower values of VCC on the load line and the Q-point.

4.3 Transistor Fixed-Bias Circuit (Continued) 4.3.2 Load Line Method Transistor Circuit Analysis (Continued)

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Fig. 4.12 (b) Transistor characteristics Fig. 4.12 (a) fixed Bias CE

4.3 Transistor Fixed-Bias Circuit (Continued) 4.3.2 Load Line Method Transistor Circuit Analysis (Continued) Example 4.2: Consider the circuit shown in Fig. 4.12(a) and its characteristics of Fig. 4.12 (b),

if VCC=15 V, RC=2.5 kΩ and RB=750 kΩ using the load method determine: a) IBQ, and ICQ and β

b) VCEQ, VB and VC

c) VBC then determine the transistor region of operation.

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4.3 Transistor Fixed-Bias Circuit (Continued) 4.3.2 Load Line Method Transistor Circuit Analysis (Continued) Example 4.2 Solution: Forward Bias of Base Emitter a) From Equ. (4.4) IBQ = (VCC–VBE)/RB = (15–0.7)/750kΩ = 20 µA determine the IB line on the characteristics of Fig. 4.12(c). Collector – Emitter Loop The load line equation Equ.(4.6) is: VCE = VCC – IC RC Plot this equation as in Fig 4.12(c). From the Q-point: ICQ = 3.2 mA. β = ICQ/ IBQ =3.2 mA/20µA=160 b) VCEQ =VC=7V and VB=0.7 c) VBC=VB–VC = – 6.3 V

Therefore The B-E junction is forward biased. The B-C junction is reverse biased. The transistor is working in active or

linear region.

Fig. 4.12 (c) Load Line for Example 4.2.

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4.3.3 Transistor Saturation • For a transistor operating in the saturation region, the current is a maximum

value for the particular design. • The highest saturation level is defined by the maximum collector current

provided by the specification sheet. • Saturation conditions are normally avoided since the output amplified signal

is distorted. • An operating point in the saturation region is depicted in Fig. 4.14 (a) where

VCEsat = 0.2 V and its approximate in Fig. 4.14 (b) where VCEsat = 0 V. • The approximate collector saturation current, ICsat, is calculated by setting

VCEsat = 0 V as shown in Fig. 4.15 then: ICsat = VCC / RC (4.9)

Example 4.3: Determine the saturation level for the network shown in Fig. 4.15 if VCC = 12 V,

RC = 2.2 KΩ and RB = 200 KΩ. Solution: Set VCEsat = 0 V, then apply Equ. (4.9) we get: ICsat = VCC / RC = 12 V / 2.2 KΩ = 5.45 mA.

4.3 Transistor Fixed-Bias Circuit (Continued)

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4.3 Transistor Fixed-Bias Circuit (Continued) 4.3.3 Transistor Saturation (Continued)

Fig. 4.14 Saturation regions: a) actual and (b) approximate.

Fig. 4.15 Determination of ICsat for fixed-bias configuration

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4.4 Emitter Stabilized-Bias Circuit

• The dc bias network of Fig. 4.16 contains an emitter resistor to improve the stability level over that of the fixed bias configuration as will be demonstrated through Example 4.6 later.

Base-Emitter Loop • The base-emitter loop of the network of Fig. 4.16 can be redrawn as

shown in Fig. 4.17. Writing the KVL, we get VCC – IBRB – VBE – IERE= 0 (4.10) We know that IE= ( β+1) IB (4.11) Substitute (4.10) into (4.11) and grouping the terms, we have: IB [RB + ( β+1) RE] = VCC – VBE Solve for IB gives IB = (VCC – VBE) / [RB + (β+1) RE] (4.12) Analysis of Equ. (4.12) yields to the following: 1. The difference between this equation for IB and that obtained for the fixed-

bias configuration is the term (β+1) RE. 2. The resistor RE is reflected back to the input base circuit by a factor (β+1).

This means that the emitter resistor, which is part of the collector-emitter loop appears as (β+1) RE in the base-emitter loop.

4.4.1 Analytical Method for Transistor Circuit Anal ysis

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4.4 Emitter Stabilized-Bias Circuit 4.4.1 Analytical Method for Transistor Circuit Anal ysis

Fig. 4.16 BJT bias circuit with emitter resistor.

Fig. 4.17 Base-emitter loop.

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4.4.1 Analytical Method for Transistor Circuit Anal ysis (Continued)

3. Since β is typically 50 or more, the emitter resistance appears to be more a great deal larger in the base circuit.

4. The input resistance as shown in Fig. 4.18 is given by: Ri = (β+1) RE (4.13) Collector – Emitter Loop The collector-emitter loop is shown in Fig. 4.16, apply KVL ew have: IERE + VCE + IC RC = VCC (4.14)

Substituting IE ≅ IC and grouping terms, we get:

VCE = VCC – IC (RC + RE ) (4.15)

VE Is given by: VE = IERE (4.16) While the voltage from collector to ground can be determined from VCE = VC – VE And VC =VCE + VE (4.17) Or VC =VCC - IC RC (4.18) Similarly the voltage at the base with respect to ground can be determined from VB =VCC - IB RB (4.19) Or VB = VBE + VE (4.20)

4.4 Emitter Stabilized-Bias Circuit (Continued)

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4.4 Emitter Stabilized-Bias Circuit 4.4.1 Analytical Method for Transistor Circuit Anal ysis (Continued)

Fig. 4.19 Collector-emitter loop.

Fig. 4.18 Reflected resistance of RE.

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a) IB b) IC

c) VCE

d) VC

e) VE

f) VB

9) VBC then determine the transistor region of operation.

Fig. 4.20 Emitter-stabilized bias circuit for Example 4.4.

4.4 Emitter Stabilized-Bias Circuit (Continued) 4.4.1 Analytical Method for Transistor Circuit Anal ysis (Continued) Example 4.4: For the emitter bias network of Fig. 4.20, analyze this circuit and then

determine analytically the following:

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Example 4.4 solution: a) Equ. (4.12): IB=(VCC–VBE)/[RB+(β+1)RE] = (20-0.7)V/(430+51x1)

KΩ = 19.3 V / 481 KΩ = 40.1 µA b) IC = βIB = (50)(40.1) = 2.01 mA

c) Equ. (4.15): VCE= VCC–IC(RC+RE)= 20–2.01mA x (2+1)KΩ =13.97 V d) Equ. (4.18): VC =VCC - IC RC =20 – 2.01mA x (2 KΩ ) =15.98 V e) Equ. (4.16) VE = IERE ≅ ICRE = 2.01mA x (1 KΩ ) =2.01 V or VE =VC - VCE = 15.98 – 13.97 = 2.01 V f) Equ. (4.20) VB = VBE + VE = 0.7 + 2.01 = 2.71 V 9) Equ. (4.8) VBC = VB - VC = 2.71 - 15.98 = - 13.27 V VBE is positive, hence B-E junction is forward biased. VBC is negative, hence B-C junction is reverse biased. The transistor is working in active or linear region.

4.4 Emitter Stabilized-Bias Circuit (Continued) 4.4.1 Analytical Method for Transistor Circuit Anal ysis (Continued)

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4.4.2 Load Line Method Transistor Circuit Analysis • Consider the circuit shown in Fig. 4.21 (a) and the transistor

characteristics shown in Fig.4.21 (b) • From Equ. (4.12): IB=(VCC–VBE)/[RB+(β+1)RE] to determine the IB line

on the characteristics.

Fig. 4.21Load-line analysis: (a) the network; (b) the device characteristics.

4.4 Emitter Stabilized-Bias Circuit (Continued)

(a) (b)

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• The output equation Equ. (4.15): VCE= VCC–IC(RC +RE)

• This also called the load line equation, plot this equation on the characteristics as follows:

as IC = 0 gives VCE = VCC

as VCE = 0 gives IC = VCC/(RC +RE) • Draw the load line on the transistor characteristics as shown in Fig. 4.22. • From the graph find VCEQ and ICQ.

Fig. 4.22 Emitter-bias Load-line

4.4 Emitter-Stabilized Bias Circuit (Continued) 4.4.2 Load Line Method Transistor Circuit Analysis (Continued)

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Fig. 4.23 (b) Device characteristics Fig. 4.23 (a) Emitter

stabilized CE circuit

4.4 Emitter Stabilized-Bias Circuit (Continued) 4.4.2 Load Line Method Transistor Circuit Analysis (Continued) Example 4.5: Consider the circuit shown in Fig. 4.23 (a) and its characteristics of Fig. 4.23

(b), if VCC=15 V, RC=1 kΩ, RB=376 kΩ, IB=30 and ICmax=8 mA, using the load method determine:

a) VCEQ, ICQ and β

b) RE, VB and VC

d) VBC and the region of operation.

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Example 4.5 solution: a) IB= 30 µA which determines the IB line on the characteristics of Fig. 4.23(c).

The load line equation Equ.(4.6) is: VCE = VCC – IC(RC + RE) Plot this equation as in Fig 4.23(c). From the Q-point: ICQ = 4.8 mA. β = ICQ / IBQ = 4.8 mA / 30µA = 160 VCEQ = 6V b) VCEQ = VCC – ICQ (RC+ RE) 6 = 15 – 4.8 (1 + RE) RE = 0.875 KΩ Or ICmax = VCC / (RC+ RE) then 8 = 15 / (1 KΩ + RE) gives RE = 0.875 KΩ c) Equ. (4.18): VC = VCC - IC RC =15 – 4.8 mA x (1 KΩ ) = 10.2 V Equ. (4.16) VE = IERE ≅ ICRE = 4.8mA x (0.875 KΩ ) = 4.2 V or VE = VC - VCE = 10.2 – 6 = 4.01 V Equ. (4.20) VB = VBE + VE = 0.7 + 4.2 = 4.9 V Equ. (4.8) VBC = VB - VC = 4.9 - 10.2 = - 5.3 V Hence B-E junction is forward biased and B-C junction is reverse biased. Therefore, transistor is working in active or linear region.

4.4 Emitter Stabilized-Bias Circuit (Continued) 4.4.2 Load Line Method Transistor Circuit Analysis (Continued)

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4.4 Emitter Stabilized-Bias Circuit (Continued) 4.4.2 Load Line Method Transistor Circuit Analysis (Continued)

Fig. 4.23 (c) Load Line for Example 4.5. 3/5/2012

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• The addition of the emitter resistor to the dc bias of the BJT provides improved stability, that is, the dc bias currents and voltages remain closer to where they were set by the circuit when outside conditions, such as temperature, and the transistor beta change.

Example 4.6: Compare the bias voltage and currents (VCE, IB and IC) of the fixed-bias

circuit of Fig. 4.24 (a) to that of stabilized-bias circuit of Fig. 4.24 (b) for the given value of β = 50 and a new value of β = 100.

4.4 Emitter Stabilized-Bias Circuit (Continued) 4.4.3 Improved Bias Stability (Continued)

Fig. 4.24 (a) Fixed-bias circuit. Fig. 4.24 (b) Stabilized-bias circuit.

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4.4.3 Improved Bias Stability (Continued) Example 4.6 solution: a) Using the results calculated in Example 4.1 and then repeating for a value

of β = 100 yields the following:

VCE (V) IC (mA) IB (µA) β

6.83 2.35 47.08 50

1.64 4.71 47.08 100

4.4 Emitter Stabilized-Bias Circuit (Continued)

b) Using the results calculated in Example 4.5 and then repeating for a value of β = 100 yields the following:

VCE (V) IC (mA) IB (µA) β

13.97 2.01 40.1 50

9.11 3.63 36.3 100

The BJT collector current is changed by 100% due to 100% change in the value of β. IB is the same and VCE decreased by 76%.

The BJT collector current is increased by 81% due to 100% change in the value of β. IB is deceased, helping to maintain the value of IC or at least reducing the overall change of IC due to the change in β and VCE has dropped by 35%.

The Stabilized-bias circuit of Fig. 4.24 (b) is therefore more stable than that of the fixed-bias circuit shown in Fig. 4.24 (a) for the same change in β.

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4.4.4 Transistor Saturation

• The collector saturation level or maximum collector current for an emitter-bias design can be determined using the same approach applied to the fixed-bias configuration.

• The approximate collector saturation current, ICsat, is calculated by setting VCEsat = 0 V as shown in Fig. 4.25 then:

ICsat = VCC / (RC+ RE) (4.21) • The addition of the emitter resistor reduces the collector saturation

level below that obtained with a fixed-bias configuration using the same collector resistor.

Example 4.7: Determine the saturation level for the network shown in Fig. 4.20 if

VCC = 20 V, RC = 2 KΩ, RB = 430 KΩ and RE = 1 KΩ.

Solution: Set VCEsat = 0 V, then apply Equ. (4.21) we get: ICsat = VCC / (RC+ RE) = 20 V / (2+1) KΩ = 6.67 mA. which is about three times level of ICQ.

4.4 Emitter Stabilized-Bias Circuit (Continued)

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• The voltage-divider bias configuration is shown in Fig. 4. 25. This bias circuit is less dependant on the value of β.

• A Q-point is defined by a fixed level of ICQ and VCEQ as shown in Fig.4.26. The level of IBQ will change with change in β, but the operation point on the characteristics defined by ICQ and VCEQ can remain fixed if the proper circuit parameters are employed.

Fig. 4.25 A voltage-divider bias configuration

4.5 Voltage-Divider Bias

Fig. 4.26 Defining the Q-point for the voltage-divider bias configuration

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• The input side of the network of Fig. 4.26 is redrawn as shown in Fig. 4.27 (a) • The Thevenin equivalent for circuit to the left of base terminal is found as: Step #1 RTH: The voltage source is replaced by a short circuit as in F.4.27(b). RTH = R1 // R2 (4.22) Step #2 ETH: The open-circuit Thevenin voltage as in F.4.27(c) is given by: ETH = VR2 = (VCC R2) / (R1 + R2) (4.23) Step #3 IB can be determined as in F.4.27(d) by applying KCL, we get: ETH - IB RTH - VBE - IE RE = 0 Substituting IE = (β + 1) IB and solve for IB) yields: IB = (ETH - VBE) / [RTH + (β + 1) RE] (4.24) • Once IB is known the remaining quantities of the network can be found in the

same manner as developed for the emitter-biased configuration, that is, VCE = VCC – IC (RC + RE) (4.25)

4.5 Voltage-Divider Bias (Continued)

Fig. 4.27 Analysis of voltage-divider bias configuration: (a) input side; (b) Determining of RTH; (c) Determining of VTH (d) Inserting Thevenin equivalent circuit.

4.5.1 Analytical Method for Transistor Circuit Anal ysis

(a) (b)

(c) (d)

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Fig. 4.28 Beta-stabilized circuit for Example 4.8.

4.5 Voltage-Divider Bias (Continued) 4.5.1 Analytical Method for Transistor Circuit Anal ysis (Continued)

Example 4.8: Consider the voltage-divider bias configuration shown in Fig. 4.28, if VCC=22 V,

R1=39 kΩ, R2=3.9 kΩ, RC=10 kΩ, RE=1.5 kΩ, and β = 140 determine VCE and IC.

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Example 4.8 Solution: Step #1 From Equ. (4.22) calculate the Thevenin equivalent resistance as:

RTH = R1 // R2 = (39 kΩ x 3.9 kΩ) / (39 kΩ + 3.9 kΩ) = 3.55 kΩ

Step #2 From Equ. (4.23) calculate the Thevenin equivalent voltage as:

ETH = (VCC R2) / (R1 + R2) = (22 V x 3.9 kΩ) / (39 kΩ + 3.9 kΩ )= 2 V

Step #3 From Equ. (4.24) calculate the base current as:

IB = (ETH - VBE) / [RTH + (β + 1) RE] = (2 – 0.7) V / [3.55 kΩ + 141 x 1.5 kΩ] = 6.05 µA

• Calculation of the collector current:

IC = βIB = 140 x 6.05 = 0.85 mA

• From Equ. (4.24) calculate the collector emitter voltage as:

VCE = VCC – IC (RC + RE)= 22 V – 0.85 mA x (10 kΩ + 1.5 kΩ) = 22 V – 9.78 V = 12.22 V

• The remaining equations for VE, VC and VB are also the same as obtained for the emitter-bias configuration.

4.5 Voltage-Divider Bias (Continued) 4.5.1 Analytical Method for Transistor Circuit Anal ysis

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4.5 Voltage-Divider Bias (Continued) 4.5.1 Analytical Method for Transistor Circuit Anal ysis (Continued) Example 4.9: Repeat the analysis of (Example 4.8) for the voltage-divider bias

configuration shown in Fig. 4.28, if VCC=22 V, R1=39 kΩ, R2=3.9 kΩ, RC=10 kΩ, RE=1.5 kΩ, and β is reduced to 70 determine VCE and IC. What is the effect of changing the value of β?

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Example 4.9 Solution: Step #1 From Equ. (4.22) calculate the Thevenin equivalent resistance as:

RTH = R1 // R2 = (39 kΩ x 3.9 kΩ) / (39 kΩ + 3.9 kΩ) = 3.55 kΩ (the same)

Step #2 From Equ. (4.23) calculate the Thevenin equivalent voltage as:

ETH = (VCC R2) / (R1 + R2) = (22 V x 3.9 kΩ) / (39 kΩ + 3.9 kΩ )= 2 V (the same)

Step #3 From Equ. (4.24) calculate the base current as:

IB = (ETH - VBE) / [RTH + (β + 1) RE] = (2 – 0.7) V / [3.55 kΩ + 71 x 1.5 kΩ] = 11.81 µA (increased)

• Calculation of the collector current:

IC = βIB = 70 x 11.81 = 0.83 mA (almost the same)

• From Equ. (4.24) calculate the collector emitter voltage as:

VCE = VCC – IC (RC + RE)= 22 V – 0.83 mA x (10 kΩ + 1.5 kΩ) = 22 V – 9.78 V = 12.46 V (almost the same)

• The results clearly show the relative insensitivity of the circuit to the change in β. Even though β is drastically cut in half, from 140 to 70, the levels of and are essentially the same.

4.5 Voltage-Divider Bias (Continued) 4.5.1 Analytical Method for Transistor Circuit Anal ysis

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• The similarities with the output circuit of the emitter-biased configuration results in the same intersection for the load line of voltage divider configuration.

• The load line has the same appearance as that of Fig. 4.24 as shown again in Fig. 4.29.

4.5 Voltage-Divider Bias (Continued) 4.5.2 Load Line Method Transistor Circuit Analysis

Fig. 4.29 Voltage-divider bias Load-line

• The level of IB is determined by Equ. (4.24):

IBQ = (ETH - VBE) / [RTH + (β + 1) RE] which determines the IB line on the

characteristics of Fig. 4.29. • The load line equation Equ.(4.6) is: VCE = VCC – IC(RC + RE) Plot this equation as in Fig 4.29. • From the Q-point the desired

voltages and currents are determined.

4.5.3 Transistor Saturation The saturation current for the voltage-divider configuration is the same as Emitter-Stabilized bias circuit.

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Given: 1. The network or all circuit elements. 2. The input (inputs). Desired: • Solving for the current and voltage

levels for the configuration.

Given: The circuit input / output relationship (currents or voltages) Desired: The network or the circuit elements.

• The design or synthesis process requires a clear understanding of: 1. device characteristics 2. basic laws of circuit analysis such as: Ohm’s law, KVL and KCL,Thevenin, etc. • If the transistor and supplies are specified, the design process will simply

determine the required passive elements (R, C and L). • Once the theoretical values are determined, the nearest standard commercial

vales are normally chosen and recalculate the performance.

4.6 Design Operations

Electronic Circuit

Circuit Analysis Circuit Design or synthesis

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Example 4.10: For the fixed Bias CE configuration shown in Fig. 4.30 (a) and its load

line of Fig. 4.30 (b) that defines operating point, determine the required values of VCC, RC, RB and β.

Solution: From Fig. 4.30 (b) VCE = VCC = 20 V at IC = 0 IC = VCC/RC =10 mA at VCE=0 RC = VCC / IC = 20/10 = 2 KΩ IB = (VCC – VBE) /RB = 25 µA RB=(20–0.7)/25x10-6 =772 KΩ β = IC / IB =10 mA / 25 µA =400

Fig. 4.30 (b) Load Line for Example 4.10. Fig. 4.30 (a) fixed Bias CE

4.6 Design Operations (Continued)

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Example 4.11: Given the device characteristics of Fig. 4.31 (a), determine the required values

of VCC, RC and RB for the fixed-Bias CE configuration of Fig. 4.31 (b). Solution: From the load line Fig. 4.31 (a) VCE = VCC = 20 V at IC = 0 IC = VCC/RC =8 mA at VCE=0 RC = VCC / IC = 20/ 8 = 2.5 KΩ IB = (VCC – VBE) /RB = 40 µA RB=(20–0.7)/40x10-6 =482 KΩ • Standard resistor values: RC = 2.4 KΩ and RB = 470 KΩ • Using the standard resistor values gives: IB = (VCC – VBE) /RB = 41.1 µA which is well within 5% of the specified value.

Fig. 4.31 (a) Load Line for Example 4.10; (a) fixed Bias CE network.

4.6 Design Operations (Continued)

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Example 4.12: Given that ICQ = 2 mA and VCEQ = 10 V, determine the required values of R1

and RC for the voltage-divider network of Fig. 4.32. Solution: VE = IERE ≅ ICRE = (2 mA)(1.2 KΩ ) =2.4 V VB = VBE + VE = 0.7 + 2.4 = 3.1 V VB = (VCC R2) / (R1 + R2) = (18 V x 18 kΩ) / (R1 + 18 kΩ ) = 3.1 V 324 KΩ = 3.1 R1 + 55.8 KΩ gives 3.1 R1 = 268.2 KΩ R1 = 268.2 / 3.1 = 86.52 KΩ RC = VRC / IC = (VCC - VC) / IC VC = VCE + VE = 10 + 2.4 = 12.4 V RC = (18 - 12.8) V / 2 mA = 2.8 KΩ The nearest standard commercial values: R1 = 82 KΩ and 91 KΩ.

Fig. 4.32 Voltage-divider bias CE network.

4.6 Design Operations (Continued)

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Example 4.13: The emitter-bias configuration of Fig. 4.33 has the following specifications:

ICQ = (1/2) Isat, Isat = 8 mA, VC = 18 V and β= 110, determine the required values of RC, RE and RB.

Solution: ICQ = (1/2) Isat = 4 mA RC = VRC / ICQ = (VCC - VC) / ICQ = (28 - 18) V / 4 mA = 2.5 KΩ ICsat = VCC / (RC + RE) gives RC + RE = 28 V / 8 mA = 3.5 KΩ RE = 3.5 KΩ - RC = 3.5 KΩ - 2.5 KΩ = 1 KΩ IBQ = ICQ / β = 4 mA / 110 = 36.36 µA IBQ = (VCC - VBE) / [RB + (β + 1) RE] RB + (β + 1) RE = (VCC - VBE) / IBQ RB = (VCC - VBE) / IBQ - (β + 1) RE

= (28 – 0.7) / 36.36 µA - (111) (1 KΩ) = 27.3 V / 36.36 µA - 111 KΩ = 639.8 KΩ

The nearest standard commercial values: RC = 2.4 KΩ, RE = 1 KΩ and RB = 620 KΩ .

Fig. 4.33 Emitter bias network.

4.6 Design Operations (Continued)

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Example 4.14: The emitter-bias configuration of Fig. 4.34 has the following specifications: ICQ

= 2 mA, VCEQ = 10 V and β= 150, determine the required values of RC, RE and RB.

Solution: Note: practically the voltage from the emitter to the gro und (V E =1/10 to ¼ of

VCC)

Fig. 4.34 Emitter bias network.

4.6 Design Operations (Continued)

VE =(1/10 )VCC =(1/10) 20 = 2 V

RE = VE / IE ≅ VE / ICQ = 2 V / 2 mA= 1 KΩ

RC = VRC / ICQ = (VCC - VC) / ICQ

= (20 – 10 - 2) V / 2 mA = 4 KΩ

IBQ = ICQ / β = 2 mA / 150 = 13.33 µA

RB = (VCC - VBE - VE) / IBQ

= (20 – 0.7 – 2) V/ 13.33 µA

= 1.3 MΩ

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Example 4.15: The voltage-divider configuration of Fig. 4.35 has the following specifications:

ICQ = 10 mA, VCEQ = 8 V and β= 80, determine the required values of RC, RE, R1 and R2.

Solution: Note: practically the resistor R2 must be much smaller that the input

resistance [R 2 ≤≤≤≤ (1/10) ββββ RE]

Fig. 4.34 Emitter bias network.

4.6 Design Operations (Continued)

VE =(1/10 )VCC =(1/10) 20 = 2 V

RE = VE / IE ≅ VE / ICQ = 2 V / 10 mA= 200 KΩ

RC = VRC / ICQ = (VCC - VC) / ICQ

= (20 – 8 - 2) V / 10 mA = 1 KΩ

R2 ≤ (1/10) β RE) =1/10) x 80x 0.2 = 1.6 KΩ VB = VBE + VE = 0.7 + 2 = 2.7 V VB = (VCC R2 )/(R1 + R2) 2.7V = (20V x 1.6 KΩ)/(R1 + 1.6 KΩ)

2.7R1 + 4.3 KΩ = 32 KΩ R1 = 10.25 KΩ

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