Ovonyx Technology- 2007 revision.ppt [Read-Only] · High endurance, low power, nonvolatile RAM ......
Transcript of Ovonyx Technology- 2007 revision.ppt [Read-Only] · High endurance, low power, nonvolatile RAM ......
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Introduction
Ovonic Unified Memory technology
OUM advantages
Risk factors
Product/manufacturing technology
Conclusion
Outline
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Ovonic Unified Memory is a new approach to high-speed,non-volatile memory
Reduced cost/bit
High endurance, low power, nonvolatile RAM
Readily scaled – avoids scaling barriers of DRAM/Flash
Merged memory/logic simplified
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Ovonic Unified Memory is a new semiconductor memory technology, originally invented by Energy Conversion Devices, Inc. (ECD), andnow licensed exclusively to Ovonyx, Inc.
OUM uses a reversible structural phase-change --from the amorphous phase to a crystalline phase --in a thin-film chalcogenide alloy material as the data storage mechanism.
The small volume of active media in each memory cell acts as a fast programmable resistor, switching between high and low resistance with >40X dynamic range.
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Phase-change technology is well established, and is the basis for the current CD RW, PD, DVD-RAM and DVD+RW optical disk memory products.
OUM offers advantages in cost and performance over conventional DRAM and Flash memories, and it is compatible with merged memory/logic.
OUM technology uses a conventional CMOS processwith the addition of a few additional layers to form thethin-film memory element.
OUM products are now being commercialized througha number of licensing agreements and jointdevelopment programs with Ovonyx.
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Binary Ternary QuaternaryGa Sb Ge2Sb2Te5 Ag In Sb TeIn Sb In Sb Te (Ge Sn)Sb TeIn Se Ga Se Te Ge Sb (Se Te)Sb2 Te3 Sn Sb2 Te4 Te81Ge15Sb2S2
Ge Te In Sb Ge Ge2Sb2Te5:OGe Sb Ga Sb Te Ge2Sb2Te5:N
Many phase-change alloys have been described in the technical literature
OUM Devices typically use the GeSbTe alloy system
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Congruent Crystallization in the GexSbyTez System
Rapid, reversible changes between the disordered andordered atomic structure can be made to happen forcompositions along the pseudobinary tie-line shown above.
Te Ge
Sb
Sb Te2 3
GeTe
147
225
124
415
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Amorphous Phase Crystalline Phase
TEMImages
ElectronDiffractionPatterns
Material CharacteristicsShort-range atomic orderLow free electron densityHigh activation energyHigh resistivity
Long-range atomic orderHigh free electron densityLow activation energyLow resistivity
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Annealing Dependence of Ge2Sb2Te5Electrical Resistivity
1E+0
1E+1
1E+2
1E+3
1E+4
150 170 190 210 230 250
Ea = 0.21eV
Vitreous State Crystalline State
Ea = 0.02 eV
Annealing Temperature ( C)o
Rel
ativ
e R
esis
tivity
(ten minute isochronal anneal)
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Phase-Change Properties of “tie-line” GeSbTeAlloys From DTA Measurements
Alloy System GeSb2Te4 Ge2Sb2Te5 Ge2Sb2.Te5 Ge4SbTe5
solid -> liquid:melting point: (oC) 617 632 634 690 heat of fusion: (J/cm3) 587 622 559 576
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Thermal and Mechanical Propertiesof Ge2Sb2Te5 Alloys
Thermal Conductivity (W/m K): 0.3 (amorph)0.45 – 0.95 (fcc) 1.4 – 1.53 (hcp)
Heat Capacity (J/cm3K): 1.25
Density (g/cm3): 6.20 (fcc)
Linear Thermal ExpansionCoefficient (K-1) [300K - 900K] 23.5 ppm
H.K. Lyeo et al., Appl. Phys. Lett. 89 (2006) 151904
Kuo/Favro WSU Thermal Wave Laboratory measurement
N. Nobokuri et. al, J. Appl. Phys. 78, 690 (1995)
W. Porter ORNL
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Selected Material Properties
Material
Thermal Conductivity
K (J/cm K s)
Specific Heat
C (J/cm3 K)
Thermal Diffusivity
α (cm2/s)
Electrical Resistivity
ρ (Ω cm)
Thermal Expansion Coefficient
(ppm/K)
Al 0.56 2.43 0.230 3 x 10-6 23.6
*Si 1.41 1.61 0.870 doping dependent 2.33
*Poly Si 0.34 1.61 0.185 doping dependent 2.33
TiW 0.6 2.04 0.290 7 x 10-5
TiAlN 0.3 0.7 0.420 2 x 10-3
*Si1.0N1.1 0.02 1.4 0.014 comp. dependent 3.0
*SiO2 0.014 3.1 0.004 1 x 1016 0.6
(ZnS).8 – (SiO2).2 0.0066 2.04 0.003 1 x 1015 (est)
BCB 0.0015 0.7 0.002 1 x 1019 52
Polyimide 0.0016 0.7 (est) 0.002 4 x 1016
* C.H. Mastrangelo PhD Thesis “Thermal Applications of Microbridges” UCB (1991)
Selected Material Properties
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V thV h
V O LTA G E
CU
RR
EN
T
Ith
Threshold Switching in Chalcogenide Alloys
Chalcogenide alloys (alloys that contain elements such as Se and Te from Group VI of the Periodic Table) exhibitelectronic threshold switching.This phenomenon allows GeSbTe – based OUM cells to be programmed at low voltage whether they are in the resistive or conductive state.
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The OUM cell is programmed by application of a current pulse at a voltage above the switchingthreshold.
The programming pulse drives the memory cell into a high or low resistance state, depending on currentmagnitude.
Information stored in the cell is read out by measurement of the cell’s resistance.
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Programming of OUM Device
Time
Tem
pera
ture
Ta
T
T
m
x
AmorphizingRESET Pulse
Crystallizing(SET) Pulse
t1
t2
(schematic)
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OUM devices are programmed by electricallyaltering the structure (amorphous or crystalline)of a small volume of chalcogenide alloy.
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Data Storage Region in a Planar OUM Memory Cell
ResitiveElectrode
Amorphous Chalcogenide
Crystalline Chalcogenide
OUM device whenprogrammed to theRESET or(high-resistance) state.
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SiO2
TiWTi A lN
SiO2
SiO2
TiW
TiW
GeTeSb Phase Change Alloy
Simple planar offset structures have been used to investigate basic device physics
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Programming Curves for Planar Offset Device
1E+3
1E+4
1E+5
1E+6
0.0 0.5 1.0 1.5 2.0
Programming Current (mA)
Res
ultin
g Pr
ogra
mm
ed R
esis
tanc
e (O
hms)
Device Voltage (V)
Cur
rent
(mA
)
Programming CurrentRange
Read VoltageRange
1.2
0.8
0.4
1.6
0 0.2 0.4 0.6 0.8 1
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Programming Curves for Low Current Device
Programming Current (µA)
Res
ultin
g Pr
ogra
mm
e d R
esis
tanc
e (O
h ms)
Device Voltage (V)
Cur
rent
(µA
)
0
50
100
150
200
250
0 0.2 0.4 0.6 0.8 1 1.2
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Temperature Dependence ofProgramming Characteristics
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
0 50 100 150
Operating Temperature (oC)
Res
ista
nce
(Ohm
s)
The high resistance, “Reset,” state shows activated, semiconductor – like behavior while the low resistance, “Set,” state shows essentially temperature independent metallic behavior
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Excellent data retention has been reported on large arrays of OUM devices :
B. Gleixner, A. Pirovano, I. Sarkur, F. Ottogalli, E. Tortorelli, M. Tosi, and R. Bez, “Data Retention Characterization of Phase-Change Memory Arrays,” Proc. Intl. Rel. Phys. Symp. 542 (2007).
Array data shows intrinsic retention failure < 1 PPB at 85C for 1E5 hours – adequate for high-density array applications.
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OUM cells can have extraordinary cycle life – single cells have been tested to more than 1013 write/erase cycles without failure.
.
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Cycle Life > 1013 Write/Erase CyclesLo
g D
evic
e R
esis
tanc
e
Log Number of Programming Cycles
6
3
5
4
2108 12 14642
Programming Pulse Width: 50 nsec
Programming Current: 1 and 1.7 mA
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OUM devices have a very large dynamic rangeand can be programmed to intermediateresistance values for multi-state data storage.
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Multi-State Storage
Multiple-bit storage in each memory cell (10 pulses per step, repeated ten times.)
1E+3
1E+4
1E+5
1E+6
2.202.322.442.562.682.802.923.043.163.283.403.523.643.763.884.00
PROGRAMMING CURRENT (mA)
DEV
ICE
RES
ISTA
NC
E (o
hms)
1E+3
1E+4
1E+5
1E+6
2.202.322.442.562.682.802.923.043.163.283.403.523.643.763.884.00
PROGRAMMING CURRENT (mA)
DEV
ICE
RES
ISTA
NC
E (o
hms)
1.42
1 .51
1.60
1.70
1.79
1.88
1.98
2.07
2.16
2.26
2.35
2.45
2.54
2.63
2.7 3
2.82
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Simple analytical models are used to show trends with material properties and size for spherical equivalent structure.
Numerical model includes complete device geometry and detailed mesh evaluation.
Device Modeling
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Numerical simulation is used to predict the behavior of OUM devices
Chalcogenide behavior is based on bulkproperties of the alloy.Bulk properties can be quantified.
ObjectiveModel well-understood bulk properties.Predictive capability for alternate device structures.Sensitivity analysis of device structure variations.
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Model Considerations
Phase-change
Electrical
Thermal
NucleationCrystal growthHeat of fusion
Electric fieldCurrent densityPercolation conduction
Heat equationsPercolation conduction
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Crystalline volume fraction as a function oftemperature and time is given by theJohnson-Mehl- Avrami equation.
Ea: activation energy T: temperature
p: nucleation rate t: time
Ko scaling factor0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-10
-9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10Log t (sec)
400 C
200 C
250 C
300 C
Crystalline Volume Fraction vs. Log (t)
350 C
150 C
to = 2E-36 secp = 1Ea = 3.7 eV
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Both electrical and thermal conductivity aredescribed by a two-component percolationsystem.
ratio=6
ratio=104
electricalconductivity
thermal conductivity
(σ)
(k)
1E4
1E3
1E2
1E1
1E00 20 40 60 80 100
17%
Volume Fraction of High Conductivity Component
Ove
rall
Con
duct
ivity
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The device can be broken into a mesh, with finite differencecalculations performed at each mesh point.
The mesh has variable spacing to allow both detailed electricalanalysis and accurate thermal accounting with the least number ofmesh points.
The mesh has variable spacing to allow both detailedelectrical analysis and accurate thermal accountingwith the least number of mesh points.
The device can be broken into a mesh, withfinite difference calculations performed ateach mesh point.
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Initial Conditions
Increment Time
ComputeElectrical Solutionof Array
Iterate Heat Equation for this Timestep
Modify Heat- TimeDependent Variables
Significant Change?
Yes No
Implicit electrical solution of the mesh followed by explicit calculation of temperature allows time/temperature/ electrical phase-dependent properties to be varied in time.
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Speed Power Tradeoff
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-05 1.E-04 1.E-03 1.E-02
Power to reset in 5ns (W)
Que
nch
time
(s)
Speed Power Tradeoff
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-05 1.E-04 1.E-03 1.E-02
Power to reset in 5ns (W)
Que
nch
time
(s)
SiOBPSG
SiN
Polymer
100
200
400
600
800
1000
1200
1500
1900
.
Simulation results for different device structure and dielectric materials and scaling the device equivalent spherical diameter from 1,900 to 100 A.Scaling results in lower power and faster memory operation.
Speed Power Tradeoff
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Strong Ovonyx Proprietary Position
020406080
100120140160180200220
'99 '00 '01 '02 '03 '04 '05 '06
Patents Issued Applications Filed
Licensable Patents (115 issued + 81 filed) as of Dec06
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Ovonyx Ranked 8th Worldwide in Semiconductor Manufacturing Category in 2006 by IEEE Spectrum in terms of Originality, Growth, Generality and Impact of IP.
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Cost/Bit Reduction
Small active storage medium
Small cell size – small die size
Simple manufacturing process – low step count
Simple planar device structure
Low voltage – single supply
Reduced assembly and test costs
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Non-volatileHigh endurance – >1013 demonstratedLong data retention – >10 yearsStatic – no refresh overhead penaltyRandom accessible – read and writeHigh switching speedNon-destructive readDirect overwrite capabilityLow standby current (<1µA)Large dynamic range for data (>40X)Actively driven digit-line during readGood array efficiency expectedNo memory SER – RAD hardNo charge loss failure mechanisms
Near-Ideal Memory Qualities
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Highly Scalable
Performance improves with scaling
Only lithography limited
Low voltage operation
Multi-state demonstrated
3D multi-layer potential with thin films
Small storage active medium
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Logic Process Compatible
Late low-temperature processing– Doesn’t compromise P-channel devices
Adds 2 to 4 mask steps to conventional CMOS logicprocess with low topography
Low-voltage operation
Enables economic merged memory/logic
Enables realistic System-On-a-Chip (SOC) products:– Logic/Non-volatile memory/Data memory/Linear
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MDL and MFL– 16-64Mbit, .5-2M gates
Provides higher performance, reduced power, reduced package count, and increased reliability
Costly and difficult with DRAM or Flash
OUM substitutes for DRAM a/o Flash– Enabling reduction in cost/complexity
Merged Memory Logic
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System-On-a-Chip (SOC) Compatible
Linear, SRAM, DRAM, Flash, DSP, CPU, FPLD, ROM
4M to 64M, 2M gates on 100mm2 die
OUM unified solution, 24 to 26 masks with five metal layers
Reduction to realistic cost/complexity
Simplicity reduces development time– Keeps technology and products current
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Reset current < min W switch current
Standard CMOS process integration
Alloy optimization for robust high temp operation and speed
Cycle life endurance consistency
Endurance testing to 1014 – DRAM
Defect density and failure mechanisms
Risk Factors
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Read operations are performed at a voltage belowthe threshold voltage, Vt, to avoid upset, so control ofVt in a memory array is a critical manufacturing issue.
Vt is seen to be stable with changes in temperature of teststructures.
Vt can also be adjusted by tailoring reset current if needed.
Variations in programming characteristics due to layer thickness and compositional uniformity of the chalcogenide alloy have been investigated.
OUM arrays have demonstrated manufacturability
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0
0.5
1
1.5
2
2.5
3
0 0.5 1
Device Voltage (v)
Dev
ice
Cur
rent
(mA
) 38 C60 C80 C100 C120 C140 C160 C180 C
Current - Voltage vs. Temperature
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R-I Curve & Threshold Voltage vs. Current
1E+3
1E+4
1E+5
1E+6
1E+7
0 1 2 3 4 5
Programming Current (mA)
Res
ista
nce
(OH
MS)
0
0.2
0.4
0.6
0.8
1
1.2
0 1 2 3 4 5
Reset Current (mA)
Thre
shol
d Vo
ltage
(V)
(breakdown structure)
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0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5
Device Voltage (v)
Dev
ice
Cur
rent
(m
A)Current - Voltage vs. Reset
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0
0.5
1
1.5
0E+0 2E-6 4E-6 6E-6 8E-6 1E-5
Electrode Spacing (cm)
Volta
ge (v
olts
)
HOLDING
THRESHOLD
Vh and Vth vs. Electrode Spacing
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R-I Scanned Across Wafer
1E+3
1E+4
1E+5
1E+6
0 1 2 3 4
Programming Current (mA)
Res
ista
nce
(OH
MS)
fixed reset level(4 mA, 40 nsec)
6 die, two devices per die, scanned diagonally across 3” wafer
(non-breakdown structure)
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Compositional Dependence of Laser-Induced Crystallization Speed in GeTeSb Alloy Films
50
50
40
40
30
30
20
20
10
100
Ge Sb Te2 2 5
GeSb Te2 4
GeSb Te4 7
GeTe
Te
Sb Te2 3Sb(at%)
Ge(
at%
)
200ns
100ns70ns
50ns30ns
Noboru Yamada, “Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording”, pp28-37. (1997).SPIE v.3109,
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Disturb Considerations
Read Disturb– Read is performed in the OFF mode for the reset state – For the set state, read is mildly constructive – For the reset state, read current is negligibly small
– I read < I setWrite Disturb– ∆T = 20oC at 1000Å spacing – simulationConclusion– No known disturb issue with the presently-planned
array architecture and read/programming scheme as long as:
- Vread < Vth- Matchstick space > ~1000Å
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DC Read Effect
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1 1E+2 1E+3 1E+4 1E+5 1E+6Time (sec)
Res
ista
nce
(ohm
s)
no set states
Vread = 0.5VVth = 0.8V
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Flash - pin compatible
FPLD, FPLA - pin compatible
DRAM - pin compatible
Embedded macros
SOC macros
SRAM -cache, battery, fast
ROM - pin compatible
Initial Target Markets
Encryption
Neural computing
Digital Signal Processing
Power switching
Smart cards
Serial EEPROM
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Conclusion
Near ideal memory qualities
Broadens system applications – Embedded, System-On-a-Chip (SOC), other products
Highly scalable
Risk factors have been identified
Time to productize
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For additional information:
Phone: 248.299.6022Fax: 248.659.1500E-mail: [email protected]: 2956 Waterview Drive; Rochester Hills, MI 48309