Overview of CMOS Device Behavior and Modeling

for Mixed-Signal/RF Circuit Design

Yuhua Cheng

Siliconlinx, Inc.Bridging the gap between IC designers and foundries

2 Yuhua Cheng

________________________________Outline

• CMOS Technology Trends

• Device Behavior Overview

• Device Modeling Challenges

• Figures of Merit and Model Validation

• Summary

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________________________________• CMOS has been in nanoscale era.

• Silicon CMOS is still the mainstream IC technology in the next 7-10 years before othernano devices play roles.

1990 1995 2000 2005 20100.01

0.1

1

22nm

Micro-scale Technology Regime

Nano-scale Technology Regime30nm

45nm65nm

90nm0.13µm

0.18µm0.25µm

0.35µm0.5µm

Year

Mic

rom

eter

10

100

1000

Nanometer

Source: Intel

CMOS Technology Trends -- Nano-scale

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________________________________Semiconductor Industry (SI) TrendPC -> Communication (wireless)

Intel Inside Communication Everywhere

• The data of voice, video and other information will be exchanged through any media at any time and any places

by wireless devices!

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________________________________SI Trend (CONT.)IC -> Application Integration

– The revenue ratio of the system chip to overall semiconductor industry will increase to 21.9% (with a total revenue of 65.6 billions) in 2008 from 16.6% in 2002

– Product integration is to integrate different products such smart phone, camera, cell phone, PDA, TV, music player, based on one platform such as cell phone.

– The integration of end market will be the merge of markets such as computer, consumer, wired and wireless communications.

Power CPU

WLAN

3D Graphics

GPS

PDA

MovieTVVideo

Integration of Chips Integration of Applications (End Market)

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________________________________CMOS Technology Trends -- RF CMOS• Recent speed improvements and better noise behavior of

CMOS transistors have made it feasible to implement RF circuits for wireless products, such as cell phones, Global Positioning System, and Bluetooth.

• CMOS is one of the best suitable technologies to ingrate RF circuits with analog and base-band digital circuits.

• Tremendous research effort is dedicated to RF CMOS, driven by System-on-Chip (SoC).

CMOS:High integration densityHigh yieldLow power consumptionLow cost

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________________________________An Illustration of RF SoC on CMOS

K. Muhammad et al. “Digital RF Processing: Toward Low-Cost Reconfigurable Radios,” IEEE Communication Magazine, Vol. 43, pp. 105-113, 2005.

• RF SoC - Integrate a chipset system onto a same chip:

• RF Front End (RFFE)• Analog Based-band (ABB)• Power Management and Audio Codecs (PMAC) • Digital Base-band (DBB)

• RFCMOS implementation challenges:

• low cost• high performance

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________________________________

Need to Well Understand the Device Behavior in Advanced Technology

Nodes

Need to Develop Physical and Accurate Device

Models for RF/Analog Design

Design IC in Nano-scale/RF Era

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________________________________MOSFET High Frequency Behavior

0.1 110

100

0.18um

0.35um

0.13um

90nm

0.25um

0.25um

0.5um

0.18um

0.12um

0.35um

90nm

Channel Length (µm)

Cut

off F

requ

ency

(GHz

)

0.1

1

NFmin (dB)

• Today’s MOSFETs show high Ft and low NF

(Yuhua Cheng, “Challenges in Bridging Manufacturing and Design for RF applications-An Overview of Advanced Device Modeling for RF Circuit Design”, RFIC/IMS workshop, June 2004)

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________________________________Leakage in Different Technology Node

• Leakage increases significantly as technology advances.

0 20 40 60 80 100 120 140 16010-1

100

101

102

103

104

0.25µm

0.18µm

0.13µm

90nm

J off (n

A/µm

2 )

Temperature (oC)(Yuhua Cheng, “Challenges in Bridging Manufacturing and Design for RF applications-An Overview of

Advanced Device Modeling for RF Circuit Design”, RFIC/IMS workshop, June 2004)

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________________________________MOSFET Gate Leakage

0.0 0.5 1.0 1.5 2.0 2.5 3.010-910-810-710-610-510-410-310-210-1100101102103104

Tox=2.5nm

Tox=2.0nm

Tox=1.4nm

VDS=0V

J gat

e (A

/cm

2 )

Vgate (V)

• In today’s MOSFETs, gate leakage increases by orders for the decrease of Tox

(Yuhua Cheng, “Challenges in Bridging Manufacturing and Design for RF applications-An Overview of Advanced Device Modeling for RF Circuit Design”, RFIC/IMS workshop, June 2004)

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________________________________

100 200 300 400 500 600 700 800 90010-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

NFETPFETIo

ff (A

)

IDsat (mA)

IDsat/Ioff Universal Curves

• A trade-off between IDsat and Ioff.• Better device design and material selection to reduce the slope

of the universal curves.

Better Device Design

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________________________________Layout Dependent Device Performance

• Effects different to nfet and pfet.• Impact both digital (changing drive current) and

analog (changing both Gm and matching).

(C. H. Diaz et al., “Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era,”, IEEE J. of Solid-State Circuits, Vol. 38 , Pages:444–449, 2003)

14 Yuhua Cheng

________________________________Layout Dependent Device Performance (CONT.)

• Irregular device layouts are used in digital (even analog) cell libraries.

• The layouts of the devices in the cell libraries may be different from those for device modeling

(C. H. Diaz et al., “Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era,”, IEEE J. of Solid-State Circuits, Vol. 38 , Pages:444–449, 2003)

15 Yuhua Cheng

________________________________HF Behavior – Parasitic Effects

trench trench trenchtrench

SB DB

RSB RDB

RDSB

RDS

RS RD

G

RG

DSB DDB

CGSO CGDO

N+ N+ P+P+

P-SUB

N- N-

• Parasitic components need to be well understood at HF.

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________________________________HF Behavior: Effective Rg• Effective RG extracted by:

• Effective RG does not follow equation below when Lf is long:

• Significant increase in effective RG due to non-quasi-static (NQS) effect.

)(,α

+=f

extff

GshpolyG

WWLN

RR

}Im{}Im{}Re{

1211

12

YYYRG =

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60

10

20

30

40

50

~LF/W

F~W

F/L

F

VGS

=0.8V

1.0V

1.8V

VDS

=1.0V

VBS

=0V

WF=6µm

NF=10

Frequency=2GHz

Gat

e R

esis

tanc

e (O

hm)

Ldrawn

(µm)

(Yuhua Cheng et al., “High frequency characterization of gate resistance in RF MOSFETs”, IEEE Electron Device Letters , Vol. 22, pp. 98-100, 2001.)

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________________________________HF Behavior: NQS Effects (1)• Effective Gm, normalized:

• Short L, Gm is “constant” over f.

• Longer L, Gm becomes frequency dependent;

• The longer the L, the stronger the frequency dependence.

)Re()Re(

)0(21

21,

fnormalizedm

YYG =

0 2 4 6 8 10 12 140.0

0.2

0.4

0.6

0.8

1.0

1.2

L=1.35 µm

L=0.85µm

L=0.35 µm

WF=15 µm

NF =10

VGS

=1.8V

VDS

=1.5V

VBS

=0V

Rea

l(Y21

)/Rea

l(Y21

)(f0)

Frequency (GHz)

(Yuhua Cheng et al., “Frequency-dependent resistive and capacitive components in RF MOSFETs ,” IEEE Electron Device Letters , Vol. 22, pp. 333 –335, July 2001.)

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________________________________HF Behavior: NQS Effects (2)• Effective Gate Capacitance

Cgg,eff:

• Short L, Cgg,eff is “constant”over f.

• Longer L, Cgg,eff becomes frequency dependent.

• The longer the L, the stronger the frequency dependence.

ω=

}Im{ 11,

YC effGG

• (Yuhua Cheng et al., “Frequency-dependent resistive and capacitive components in RF MOSFETs ,” IEEE Electron Device Letters , Vol. 22, pp. 333 –335, July 2001.)

0 2 4 6 8 10 120.002

0.003

0.004

0.005

L=1.35 µm

L=0.85 µm

L=0.35µm

WF=15µmNF=10

VGS=1.8VVDS=1.5VVBS=0V

CG

G (F

/m2 )

Frequency (GHz)

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________________________________HF Behavior: Substrate Coupling

trench trench trenchtrench

SB DB

Rsb Rdb

Rdsb

G

Dsb Ddb

P-sub

Signal at the drain coupling to the nearby source diffusions and to the substrate terminal through the junction capacitance and substrate resistance

• At HF, signal is coupled to substrate through junction capacitance.

• This effect impact mainly the output impedance.

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________________________________HF Behavior: Bias and f Dependence of Rsub

0 2 4 6 8 10 120

50

100

150

VGS

=0.0V, 0.2V, 0.4V, 0.6V

Wdrawn

=15µm

Ldrawn

=0.35µm

VDS

=0V

VBS

=0V

Rsu

b (Ohm

)

Frequency (GHz)0 2 4 6 8 10 12

0

50

100

150

VDS

=0.0V, 0.5V, 1.0V, 1.5V, 2.0V

Wdrawn

=15µm

Ldrawn

=0.35µm

VGS

=0V

VBS

=0V

Rsu

b (O

hm)

Frequency (GHz)

• Substrate resistance is a very weak function of biases at the gate and drain.

• Up to 10GHz, substrate resistance is not sensitive to frequency.

(Yuhua Cheng et al., “On the high-frequency characteristics of substrate resistance in RF MOSFETs ” IEEE Electron Device Letters , Vol. 21, Page(s): 604 –606, 2000 )

21 Yuhua Cheng

________________________________HF Behavior: Thermal Noise

• HF noise reduces as the technology advances (and shorter L).

• Higher Gm, lower HF noise.• Low Nf (<1dB) can be obtained at normal gate biases.

(Jamal Deen, Chih-Hung Chen; Yuhua Cheng; “MOSFET modeling for low noise, RF circuit design” Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, pp. 201 – 208, May 2002. )

22 Yuhua Cheng

________________________________HF Behavior: Induced Gate Noise

• Channel noise is frequency independent and induced gate noise is frequency dependent.

• Induced gate noise is not negligible in devices with long L or devices with short L but at very high frequency.

(Jamal Deen, Chih-Hung Chen; Yuhua Cheng; “MOSFET modeling for low noise, RF circuit design” Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, pp. 201 – 208, May 2002. )

23 Yuhua Cheng

________________________________HF Behavior: High “Low Frequency Limit”

(Tzung-Yin Lee, and Yuhua Cheng, “High-Frequency Characterization and Modeling of Distortion Behavior of MOSFETs for RF IC Design”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, pp. 1407 – 1414, 2004.)

0.0001 0.001 0.01 0.1-100

-80

-60

-40

-20

0

W=12µmL=0.36µmFinger=10

P3

P2

P1V

DS=0.5V

Pin=-10dBm

Solid lines: fin=50MHz

Dashed lines: fin=100MHz

Square : fin=900MHz

+: fin=1.8GHz

Pou

t (dB

)

IDS

(A)

• MOSFET has much higher “low frequency limit” (LFL)• HF distortion characteristics (<fLFL) can be described

by its low-frequency behavior

24 Yuhua Cheng

________________________________Device Modeling for RF Applications

• Device Modeling at HF should at least include the modeling for:– MOSFET– Passive devices (R, C, inductor,varactors)– Special devices (LDMOS and PNP BJTs)– Interconnect– Substrate– Circuit blocks (behavior modeling)

• Today, we will mainly talk about MOSFET modeling.

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________________________________MOSFET Modeling Challenges• Core model with good continuity, accuracy and scalability over

wide biases, temperatures and geometries.

• Modeling of classic well-known short channel and narrow width effects and recent advanced physical effects such as velocity overshoot, self-heating, channel charge quantization, tunneling, layout dependent behavior, …

• Scalable parasitic capacitance and resistance models.

• Predicts accurately the small signal AC and noise and the distortion behavior.

• Non-quasi static (NQS) effects.

• Statistical modeling

26 Yuhua Cheng

________________________________Modeling Challenges – Gm & Gm/ID

• Gm, the most important parameters in analog design.• Gm/ID, a universal characteristic of MOSFETs to evaluate the

transconductance efficiency.• Inversion Coefficient (IC), ratio of ID/IS, is proposed as a

measure of MOS inversion level.

10-2 10-1 100 101 102 103-5

0

5

10

15

20

25Weak Inversion

Moderate Inversion

Strong Inversion

W=10µm

GM

(mS)

L=0.35µm

L=0.13µm

IC

-5

0

5

10

15

20

25

GM

/ID (1

/V)

(Yuhua Cheng, "A study of figures of merit for the high frequency behavior of MOSFETs in RF IC applications", Eighth International Conference on modeling and Simulation of Microsystems, Anaheim, May 8-12, 2005)

27 Yuhua Cheng

________________________________Modeling Challenges - Capacitance

• Gate Capacitance is not constant in strong inversion. • Bias dependence is caused by Poly-depletion effect.• Both poly-depletion (PD) and channel quantization

(CQ) effects will impact Cgg.

-3 -2 -1 0 1 2 30.0

0.1

0.2

0.3

0.4

0.5

0.6

Lines: Simulated resultsSymbols: Measured data

With PD and CQ EffectsWith PD Effect No PD and CQ Effects

Gat

e C

apac

itanc

e (p

F)

Gate Voltage (V)(Yuhua Cheng et al.,” ICM-an analytical inversion charge model for accurate modeling of thin gate oxide MOSFETs,”

Simulation of semiconductor Processes and Devices,Page(s) 109 –112, 1997.)

28 Yuhua Cheng

________________________________Modeling Challenges – Scalable Rsub

Signal at the drain coupling to the nearby source diffusions and to the substrate terminal through the junction capacitance and substrate resistance

B B

Rsb Rdb

Csb Cdb

Si Di

Rdsb

(Intrinsic source) (Intrinsic source)

• Rsub should be scalable in terms of channel width, length and fingers.

• All parameters should be extracted easily.

(Yuhua Cheng, “An Overview of Device Modeling in Bridging Manufacturing and Design for RF applications”, International Conference on Solid-state Integrated Circuits and Technologies, D4.3-1 – D4.3-6, Beijing, China, Oct 2004 )

29 Yuhua Cheng

________________________________Modeling Challenges - NQS Effects• NQS will significantly

impact Y11 and Y21behavior.

• Many approaches are proposed to model this effect:– Multi-segment

approach– Relaxation time – Rg/Ri equivalent

circuit approach• Efficient built-in

NQS effect in intrinsic core model is preferred.

0.0 4.0x109 8.0x109 1.2x1010-0.02

-0.01

0.00

0.01

WF=10x15µm

LF=1.35µm

VGS

=VDS

=1V

VBS

=0VIm{(Y

21)}

Re{Y21

}

Symbols: DataSolid lines: Model W/ NQSDotted lines: Model W/O NQSR

e{Y 21

} and

Im{Y

21} (

A/V

))

Frequency (Hz)(Yuhua Cheng et al. , “Frequency-dependent resistive and capacitive components in RF MOSFETs ,” IEEE Electron Device Letters , Vol. 22, pp. 333 –335, July 2001. )

30 Yuhua Cheng

________________________________Modeling of Flicker noise

• Downscaling may degrade flicker noise behavior.• Modeling of flicker noise in nano-scale devices becomes

more challenging.• Accurate prediction of corner frequency, Fcorner, is

critical for circuit design.

100 101 102 103 104 10510-19

10-18

10-17

10-16

10-15

10-14

Lines: ModelSymbols: Data

L=0.13µmVGS

=0.75V

VGS

=0.45V

VDS

=0.8V

Sid

(A2 /H

z)

Frequency (Hz)(Yuhua Cheng, "A study of figures of merit for the high frequency behavior of MOSFETs in RF IC applications", Eighth International Conference on modeling and Simulation of Microsystems, Anaheim, May 8-12, 2005)

31 Yuhua Cheng

________________________________Modeling Challenges – HF Noise

• Parasitic resistance at gate, source, drain and substrate generate thermal noise

• Channel thermal noise is the dominant noise source at HF.• Understanding of noise sources is important.• Modeling of channel thermal noise and induced gate noise is the most

challenging job.

2Gi

GR

2gi

GBC

GSC

GDC

SBC

DBC

GSImVG BSImbVG

SRSUBR

DR

DSR

2Si

2di

2Di

2SUBi

D

B

G

S

iG iD

iSiB

32 Yuhua Cheng

________________________________Statistical Modeling• Process variation (even within a wafer) in today’s

advanced technologies becomes more significant.

• Need physical statistical models to predict process variation and local mismatch to optimize analog/RF circuits with high yield.

• Correlations between statistical modeling with considerations of both frontend and backend process variations and yield modeling/prediction should be developed.

• In nano-scale technologies, statistical model is more meaningful than traditional corner models.

33 Yuhua Cheng

________________________________RF Modeling in Nano-scale Era

Modeling of Small Signal, Noises, Large Signal Distortion

For RF Applications

Continuity Scalability Accuracy

ComputationEfficiency

New Physical Effects

34 Yuhua Cheng

________________________________Gm/ID: Measured vs. Fitted

• Gm/ID has been proposed a FoM for model validation for analog applications.

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50

10

20

30

VDS

=50mV

Symbols: Measured dataLines: BSIM3v3 Model

VBS

=-3.3V

VBS

=-0.7V

VBS

=0VGm

/I D (1/V

)

VGS

(V)(Yuhua Cheng, "A study of figures of merit for the high frequency behavior of MOSFETs in RF IC applications", Eighth International Conference on modeling and Simulation of Microsystems, Anaheim, May 8-12, 2005)

35 Yuhua Cheng

________________________________fT: Measured vs. Fitted

• A standard device parameter for model validation.• However, only fT is not enough to describe HF behavior of

MOSFETs, especially at technology nodes such as 0.13um and below.

10-7 10-6 10-5 10-4 10-3 10-20

20

40

60

80

100

120Lines: BSIM3v3 ModelSymbols: Data

L=0.13µm

L=0.18µm

L=0.35µm

f T (G

Hz)

ID/width (A/µm)(Yuhua Cheng, C. H. Chen, M. Matloubian, and M. J. Deen, “High frequency small signal AC and noise modeling ofMOSFETs for RF IC design,” IEEE Transactions on Electron Devices, Vol. 49, pp. 400 – 408, March 2002.)

36 Yuhua Cheng

________________________________Gmax and fmax: Measured vs. Fitted

• fmax contains the impacts from parasitics such as gate and substrate resistance and is a better FoMthan fT

10-7 10-6 10-5 10-4 10-30

5

10

15

20

25

VD=0.5V

VD=2.5VVD=2VVD=1.5VVD=1V

L=0.35µm

Lines: BSIM3v3 ModelSymbols: Data

Gm

ax (d

B)

ID/Width (A/µm)10-8 10-7 10-6 10-5 10-4 10-3 10-20

10

20

30

VD=1.5V

VD=2.5VVD=2V

VD=0.5V

VD=1VL=0.35µm

Lines: BSIM3v3 ModelSymbols: Data

fmax

(GHz

)

ID/Width (A/µm)

(Yuhua Cheng, "A study of figures of merit for the high frequency behavior of MOSFETs in RF IC applications", Eighth International Conference on modeling and Simulation of Microsystems, Anaheim, May 8-12, 2005)

37 Yuhua Cheng

________________________________C-parameters: Modeled vs. Fitted

• C-parameters are more sensitive to the bias dependence of gate resistance and capacitance.

• Useful FoMs for model validation.

10-3 10-2 10-1100

101

102

103

104

L=0.35µm

Lines: ModelSymbols: Data

Rin

Rfb

Rout

R (O

hm)

ID (A)10-5 10-4 10-3 10-2 10-1

50

100

150

200L=0.35µm

Lines: ModelSymbols: Data

Cfb

Cout

Cin

Capa

cita

nce

(fF)

ID (A)(Yuhua Cheng, "A study of figures of merit for the high frequency behavior of MOSFETs in RF IC applications", Eighth International Conference on modeling and Simulation of Microsystems, Anaheim, May 8-12, 2005)

38 Yuhua Cheng

________________________________Large Signal Behavior: Measured vs. Fitted

• Below certain (the “LFL”) frequency, the distortion behavior of MOSFETs is primarily determined by transconductance and capacitances.

• With careful parameter extraction at DC and HF small signal, a model can well predict the large signal distortion behavior.

-50 -40 -30 -20 -10 0 10-100

-80

-60

-40

-20

0

20Lines: ModelSymbols: Data

P3

P1

P2

VDS=1VVGS=0.83V

Freq=1.8GHz

W=10x12µmL=0.36µm

Pou

t (dB

m)

Pin (dBm)10-3 10-2 10-1

-60

-50

-40

-30

-20

-10

0

10

Lines: ModelSymbols: Data

VDS=1V

Pin=0dBmFreq=1.8GHz

Wf=12µmLf=0.36µmFinger=10

Pou

t (dB

m)

IDS (A)(Tzung-Yin Lee, and Yuhua Cheng, “High-Frequency Characterization and Modeling of Distortion Behavior of MOSFETs for RF IC Design,” IEEE Journal Of Solid-State Circuits, VOL. 39, NO. 9, pp. 1407 – 1414, September 2004)

39 Yuhua Cheng

________________________________

Validate Models Based On Meaningful

Figures-of-Merit

Something worth mentioning in RF Modeling

40 Yuhua Cheng

________________________________Summary

• While all the requirements for continuity, scalability, accuracy and computation efficiency need to be met for device models for circuit simulation, the new physical effects in nano-scale devices make compact model development very challenging.

• A lot of additional modeling efforts to predict HF noise and large signal distortion behavior are needed for RF circuit design.

• It would be desirable in the future the modelers use certain FoMs at HF to qualify the device models targeted for analog/RF applications.

• Device modeling has become very critical component in the technology platform for RF SOC design in nano-scale technologies.

Thank you for your attention