October 11, 20001. 2 Platform Design Considerations Jim Choate Intel Corporation.
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Transcript of October 11, 20001. 2 Platform Design Considerations Jim Choate Intel Corporation.
October 11, 2000 1
October 11, 2000 2
Platform Design ConsiderationsPlatform Design Considerations
Jim ChoateJim ChoateIntel CorporationIntel Corporation
October 11, 2000 3
AgendaAgenda
GuidelinesGuidelines Measurement TechniquesMeasurement Techniques Testing ResultsTesting Results SummarySummary
October 11, 2000 4
GuidelinesGuidelines
USB 2.0 guidelines are more systematic, detailed USB 2.0 guidelines are more systematic, detailed than 1.x whitepapersthan 1.x whitepapers
The USB 2.0 Platform Design Guideline, Revision The USB 2.0 Platform Design Guideline, Revision 0.9 is available now0.9 is available now– http://developer.intel.com/technology/usb/techlit.htmhttp://developer.intel.com/technology/usb/techlit.htm
Guideline areas:Guideline areas:– Board routing, placement and layout guidelinesBoard routing, placement and layout guidelines– EMI/EMC solutions EMI/EMC solutions – Front panel USB design guidelinesFront panel USB design guidelines
October 11, 2000 5
Proposed GuidelinesProposed Guidelines
USB 2.0 Peripheral Design GuidelineUSB 2.0 Peripheral Design Guideline Other Proposed Guideline Areas:Other Proposed Guideline Areas:
– TDR TestingTDR Testing– Oscilloscope SetupsOscilloscope Setups
CHIRP TestingCHIRP Testing Device Signal Quality TestingDevice Signal Quality Testing Host Signal Quality TestingHost Signal Quality Testing
– Test Fixture Design And UsageTest Fixture Design And Usage– Hub Repeater TestingHub Repeater Testing
October 11, 2000 6
Board DesignBoard Design
4 layer sufficient; trace impedance matching4 layer sufficient; trace impedance matchingis keyis key
3 ns + 26 ns + 1 ns3 ns + 26 ns + 1 ns Maximum Motherboard Trace Length Of 18 InchesMaximum Motherboard Trace Length Of 18 Inches
– Cable + Traces Cable + Traces 18 Inches For Front Panel Solutions 18 Inches For Front Panel Solutions Do not cross plane splitsDo not cross plane splits Minimize viasMinimize vias Maximize distance to other tracesMaximize distance to other traces
Motherboard Is theToughest Environment
Motherboard Is theToughest Environment
October 11, 2000 7
Board Design GuidelinesBoard Design Guidelines
Board Stack-up:Board Stack-up:– 4 layer, impedance controlled boards required4 layer, impedance controlled boards required– Impedance targets must be specifiedImpedance targets must be specified– Ask your board vendor what they can achieveAsk your board vendor what they can achieve
Classic four-layer stackClassic four-layer stackSignal 1Signal 1
PrepregPrepreg
VCCVCCCoreCoreGroundGround
PrepregPrepreg
Signal 2Signal 2
Example target impedance:Example target impedance:0.005 in trace at 60+/-15%0.005 in trace at 60+/-15%7.5mil traces with 7.5mil7.5mil traces with 7.5milspacing Zdiffspacing Zdiff 90 90
October 11, 2000 8May 17, 2000 7
Routing GuidelinesRouting Guidelines
Control trace widths to obtain target impedanceControl trace widths to obtain target impedance– Ask your board vendor what they can achieveAsk your board vendor what they can achieve– As always, cost is a considerationAs always, cost is a consideration
Maintain strict trace spacing controlMaintain strict trace spacing control Minimize stubsMinimize stubs
D-D-D-D-
D+D+D+D+
15k15k
15k15kCorrect way to connect to resistorsCorrect way to connect to resistors
October 11, 2000 9
Routing GuidelinesRouting Guidelines
Routing over plane splitsRouting over plane splits Creating stubs with test pointsCreating stubs with test points Violating trace spacing guidelinesViolating trace spacing guidelines
Common Routing MistakesCommon Routing Mistakes
Ground or power planeGround or power plane
tptpDon’t cross plane splitsDon’t cross plane splits
Proper routing technique Proper routing technique maintains spacing guidelinesmaintains spacing guidelines
October 11, 2000 10
MotherboardMotherboard Front PanelDaughter Card
Front PanelDaughter Card
Board DesignBoard Design
Daughtercard at front/side panelDaughtercard at front/side panel– Bypass caps, EMI control components, strain reliefBypass caps, EMI control components, strain relief
Header and cableHeader and cable– Keyed header, cable of limited length andKeyed header, cable of limited length and
matched impedance matched impedance
Front/Side Panel ConnectorsFront/Side Panel Connectors
October 11, 2000 11May 17, 2000 9
Measurement TechniquesMeasurement Techniques
Selecting Appropriate Test EquipmentSelecting Appropriate Test Equipment– Accurate measurement of signal quality requires an Accurate measurement of signal quality requires an
oscope and probes with adequate BW and sample rateoscope and probes with adequate BW and sample rate
– Proper test fixtures are also importantProper test fixtures are also important
Equipment that will workEquipment that will workScope: TDS 694C - 10GS/s, 3GhzScope: TDS 694C - 10GS/s, 3GhzProbe: P6247 Fet Probe - 4Ghz, .4pF typProbe: P6247 Fet Probe - 4Ghz, .4pF typ
9090
Differential ProbeDifferential Probe
October 11, 2000 12
Board TestingBoard Testing
Use TDRs To Verify Adherence To BudgetUse TDRs To Verify Adherence To Budget– Typical TDR measurementTypical TDR measurement
Refer to section 7.1.6.2 of the specification for detailsRefer to section 7.1.6.2 of the specification for details
October 11, 2000 13
Board TestingBoard Testing
USB 2.0 test mode software will be USB 2.0 test mode software will be used to enable device and host used to enable device and host controller testscontroller tests
USB 2.0 test fixture will be used to USB 2.0 test fixture will be used to provide ideal termination for signal provide ideal termination for signal quality measurementquality measurement
Differential signaling requires the use Differential signaling requires the use of a differential probeof a differential probe
HS RelayHS Relay
Differential ProbeDifferential Probe
Test Mode SW
USB 2.0 test fixtureUSB 2.0 test fixture HS DeviceHS Device
OscilloscopeOscilloscope
October 11, 2000 14
EMIEMI
USB1.X EMI solutions don’t work for USB2USB1.X EMI solutions don’t work for USB2– Low pass filters damage USB 2.0 HS signal qualityLow pass filters damage USB 2.0 HS signal quality
D+
D -
Vcc
USB AConnector
Typical USB 1.1 Termination SchemeTypical USB 1.1 Termination Scheme
October 11, 2000 15
VCC
USB 'A' Connector
D-
D+
Common ModeChoke
EMIEMI
Common mode chokes are a proven USB 2.0Common mode chokes are a proven USB 2.0EMI solutionEMI solution– Refer to the USB 2.0 Design Guideline for solutions Refer to the USB 2.0 Design Guideline for solutions
that work for USB 2.0 FS & HS signal quality that work for USB 2.0 FS & HS signal quality requirementsrequirements
October 11, 2000 16
EMIEMI
Proper grounding of chassis is crucialProper grounding of chassis is crucial– Connector shell must connect to green wireConnector shell must connect to green wire
ground early and wellground early and well– IO shield must connect securely to chassisIO shield must connect securely to chassis
and receptacleand receptacle 2 wire common mode choke is preferred2 wire common mode choke is preferred
– Blocks common mode EMI from leaving chassisBlocks common mode EMI from leaving chassis– Common mode impedance @ 100 Mhz should beCommon mode impedance @ 100 Mhz should be
< 300 Ohms< 300 Ohms– Differential Impedance @ 100 Mhz should be < 8 OhmsDifferential Impedance @ 100 Mhz should be < 8 Ohms
October 11, 2000 17
ESD, EMCESD, EMC
ESD strikes spread out in time by inductanceESD strikes spread out in time by inductanceof cables and hubs in seriesof cables and hubs in series– Bypass/flyback caps on Vbus near connector helpBypass/flyback caps on Vbus near connector help
Hardware ProtectionHardware Protection– Well-grounded shield Well-grounded shield – Common mode chokeCommon mode choke– Spark gap arrestorsSpark gap arrestors– Shielded cablesShielded cables
October 11, 2000 18
DP1DP1
DM1DM1
1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9
x 10-5
0
0.5
1
1.5
2
2.5
3
3.5
s
V
keyboard glitchkeyboard glitchkeyboard glitchkeyboard glitch
ESD, EMCESD, EMC
Differential squelch/disconnectDifferential squelch/disconnect Pattern matching before connectivityPattern matching before connectivity Sampling over extended times e.g. ChirpSampling over extended times e.g. Chirp Low speed requires cables with at least a foil shieldLow speed requires cables with at least a foil shield
Noise Immunity Built IntoLow-Level Protocol
Noise Immunity Built IntoLow-Level Protocol
October 11, 2000 19
USB2 Validation Motherboard USB2 Validation Motherboard
FrontFrontPanelPanel
Test ChipBack PanelBack Panel
Test ChipTest Chip
Early Testing ResultsEarly Testing Results
October 11, 2000 20
Routing Paths Tested Routing Paths Tested
USB ConnectorUSB Connector
MotherboardMotherboard
PCI SLOTPCI SLOT
LANLAN
PCI SLOTPCI SLOT PCI SLOTPCI SLOTPCI SLOTPCI SLOT
South BridgeSouth Bridge
NEC NEC testtest chipchip
Long RouteLong Route
Front Panel HeaderFront Panel Header
Early Testing ResultsEarly Testing Results
MotherboardMotherboard
PCI SLOTPCI SLOT
LANLAN
PCI SLOTPCI SLOT PCI SLOTPCI SLOTPCI SLOTPCI SLOT
South BridgeSouth Bridge
USB ConnectorUSB Connector
Short RouteShort Route
NEC test chipNEC test chip
October 11, 2000 21
TP2 TP3
Early Testing ResultsEarly Testing Results
Back Panel Eye Pattern ResultsBack Panel Eye Pattern Results– EMI/ESD componentsEMI/ESD components– Both at A-connector (TP2) and at end of USB cable (TP3)Both at A-connector (TP2) and at end of USB cable (TP3)– Three-stack connector on MBThree-stack connector on MB
October 11, 2000 22
18” Shielded, twisted pair
18” ribbon cable
Early Testing ResultsEarly Testing Results
Front Panel Header Cable Options TestedFront Panel Header Cable Options Tested
October 11, 2000 23
Shielded Front Panel CableShielded Front Panel Cable Ribbon Front Panel CableRibbon Front Panel Cable
Early Testing ResultsEarly Testing Results
Front-panel Cable Implementation Eye Pattern ResultsFront-panel Cable Implementation Eye Pattern Results– 18 inch, twisted pair, shielded front panel cable18 inch, twisted pair, shielded front panel cable– 18 inch unshielded front panel “ribbon” cable18 inch unshielded front panel “ribbon” cable
October 11, 2000 24
Early Testing ResultsEarly Testing Results
Front-panel Cable Implementation Eye Pattern ResultsFront-panel Cable Implementation Eye Pattern Results– 18 inch, twisted pair, shielded front panel cable18 inch, twisted pair, shielded front panel cable– 18 inch unshielded front panel “ribbon” cable18 inch unshielded front panel “ribbon” cable
Connector referenceConnector reference
80
72
110
1.4 nsexception window
Shielded, Twisted PairShielded, Twisted PairFront Panel CableFront Panel Cable
114
145
114
RibbonRibbonFront Panel CableFront Panel Cable
Connector referenceConnector reference
October 11, 2000 25
Recent Testing ResultsRecent Testing Results
Back Panel Eye Pattern ResultsBack Panel Eye Pattern Results– EMI/ESD componentsEMI/ESD components– At the A-connector (TP2)At the A-connector (TP2)
October 11, 2000 26May 17, 2000 17
Host turns onHS termination
Reset
Recent Testing ResultsRecent Testing Results
CHIRP TestingCHIRP Testing– Measured with single ended probesMeasured with single ended probes– At the A-connector (TP2)At the A-connector (TP2)
Important ParametersImportant Parameters– Reset durationReset duration– CHIRP K amplitudeCHIRP K amplitude– CHIRP K durationCHIRP K duration– HS termination timingHS termination timing– Host CHIRP amplitudeHost CHIRP amplitude
October 11, 2000 27May 17, 2000 22
SummarySummary
USB 2.0 Design Presents New ChallengesUSB 2.0 Design Presents New Challenges– Board layoutBoard layout– Common mode chokesCommon mode chokes– Front Panel SolutionsFront Panel Solutions– Signal Quality MeasurementSignal Quality Measurement– Compliance TestingCompliance Testing
USBIF Is Providing Design GuidesUSBIF Is Providing Design GuidesIn Such AreasIn Such Areas