More Than Moore’s - 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC...
Transcript of More Than Moore’s - 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC...
Brandon Wang, Director, 3D-IC Solution 07/23/2014
More Than Moore’s - 3D-IC Economics and Design Enablement
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• Semiconductor Challenges – More Moore or beyond Moore?
• 3D/2.5D Advantages and Challenges • Design enablement for 2.5D/3D realization • Conclusion
Outline
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• System Requirements : Bandwidth, Power, functionality, COMPLEXITY • Obvious Solution : Jump to next process node:20nm/14nm/10nm , BUT
– NOT really shrinking!! (Analog Circuit? Variability, Leakage? And Utilization%?) – Expense of IP re-built and validation! Verification cost? Risk? T2M? – And what about COST ? – What about CIS, MEMS, Silicon Photonics, RF, Non-volatile, PMIC NOT always in
a single die!
It’s not always about process scaling
“We know how to get to smaller size nodes, but we see economic indicators slowing and we are worried about it — we can see the end from here. If we can’t make cheaper transistors, we’ll look to other things like 3D.”
Paul Jacobs, CEO, Qualcomm 8/22/13
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3D-IC Benefits and Challenges
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Various 3D Die Stacking •1 logic die and 2 memory dies
• All Dies are face down
•Die 1 and Die 2 face each other • Connected through uBump • TSV for C4Bump
Die3, TC2 –Logic Die. Die 1,2: Memory Dies;
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Why 3D?
Source: Samsung Electronics 2012 Source: Chipworks
3D-IC Brings PPA-T benefit simultaneously
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What Are The Markets For 3D-IC’s?
Source: Yole Développement, July 2012
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Short-, medium-, and long-term path to 3D-IC
Si Partitioning
with TSV Interposer
• Market : FPGA
• Xilinx in 2010
• 2011-2013
Memory Cube
with TSVs
• MARKET : Server and computing
• IBM and Micron
• 2012-2014
Logic + memory
w/ 2.5D TSV Interposer
• MARKET : Server
Network , gaming console
• 2013-2014
Memory + Logic
with TSVs
•MARKET : Mobile, tablet, gaming
processors, HPC
• 2015-2016
Heterogeneous Integration w/o
TSV
MARKET : IoT devices,
Automobile
• ~ 2015
Standards, ecosystem, cost
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Other 2.5D/3D-IC Advantages
De-Risk SOC implementation and better T2M Re-use of silicon proven Analog/MS/PHY Only port the digital to advanced process nodes
Reduce power through Light I/O, with minimized distributed ESD
Much improved SI/PI compared to discrete/POP
Improve yield for larger die at advanced nodes
Reduce Form factor
Secure against supply chain attack while using
hybrid foundries ( Trusted + Un-trusted )
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Thermal Challenges in Mobile Application
Source: ST-Ericson
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3D DFT Challenges
• Pre-bond test – Focus on die-internal circuitry – Original thick or thinned-down wafer – Probe access at DUT – Probe on micro-bumps or dedicated pads
die
• Mid-bond / post-bond / final tests – Focus on interconnects and die-internal circuitry – Test access (probe or socket) at bottom die – Require DFT to propagate test
stimuli / responses up / down through stack bottom die
middle die
top die
• Architecture Impact – Enhance Memory Redundancy Repair – Yield Focused Digital Design – Product Test as part of 3D architecture – BIST Coverage
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• Prices drive business – 3D-IC currently not as cost effective – TSV is still an expensive process – Silicon Interposer is an additional cost – Wafer thinning has yield impact
• Eventually, overall system level cost advantages will drive 3DIC adoption, but for now, 3DIC is driven by performance, power, and form factor.
• 2.5D-IC may provide more than a transition – Wider Applications – Lesser dependent on standardization – Lesser technical challenges ( Yield, Thermal, Stress, etc)
3D-IC Business Challenges Cost
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• While not necessary for market adoption, standards will be important to volume production at all levels of 3D
• How will those standards be established? • KGD, and Who owns what? Who is responsible for total
yield?
3D-IC Business Challenges Standardization and Supply Chain
Source: GSAGlobal.org
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3D/2.5D Design Enablement and Methodology
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So what changes with 3D-IC in EDA world? Revamped EDA requirements
New layout layer (e.g. Back-side RDL)
Thermal analysis and mechanical constraints
New extraction features (e.g. TSV)
Inter-processes DRC/LVS
Courtesy : Qualcomm
Package silicon co-design
Cross-die, power and signal integrity
Cross-die timing closure
Manufacture test
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Example: 2.5D Silicon Interposer and 3-D stacking Die3, TC2 –Logic Die. Die 1,2: Memory Dies; 1 logic die and 2 memory dies
stacking
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Example Design and implementation flow
Interposer design and implementation
3rd party memory modification
Logic die implementation
Logic die design for test
Die-interposer-package co-design
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Example Analysis and signoff flow
Thermal Analysis
SSO/SSN Analysis for PI/SI signoff
Timing/Power Analysis and signoff
Extraction
Inter-die DRC/LVS
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Cadence 3D-IC Integrated Solution
Complete Implementation Platforms for flexible Entry Point and Seamless Co-design
Using OpenAccess, EDI, Virtuoso™ each has dedicated 3DIC functions that work together, plus co-design with Cadence SiP tools for complete End to End implementation including early stage system exploration and feasibility
Full Spectrum Analysis Capability
RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool
Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based Extraction, SI, and PI System/Package Analysis
PowerDC Thermal Analysis
Ecosystem partnership and Real Experiences/Proof Points Cadence has been working with ecosystem partners since 2007 on 3DIC
8 test chips completed and 1 production chip done Several projects ongoing, with one tapeout Q2, 2014
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• 3D/2.5D presents an effective system scaling, as alternative to silicon
process scaling; • IoT could be a new dimension of application for heterogeneous 3D
integration • 3D/2.5D realization involves entire cycles with multiple 3D featured tools
working together on the following phases: – Planning, – Implementation, – Physical Verification ( LVS, DRC, ERC) – Electrical and Thermal Analysis, and Digital Signoff – Manufacture Test;
• Silicon Designers needs to be package driven while package designers may need to leverage sophisticated silicon tools to deal massive inter-die connectivity;
• 3D-IC is more than stacking exiting dies together in a package, it requires die and system level re-architecture to bring 3D-IC to production;
Summary