Q-A's on Atpg & Scan

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    Interview Question Bank on ATPG & SCAN

    Questions

    1- What is ATPG?

    2- What is Scan Insertion and Scan Chain?

    3-What is Full and Partial Scan?

     4-What is Combbinational ATPG and

    Seuential ATPG?

    Which has less !atterns? Wh"?

    #- Wh" $e use Combo% ATPG &or &ull scan ?

    '- What is Fault Co(era)e and Test Co(era)e?

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    *- +,!lain dierent Fault .odels?

    Stuc/ at &ault0 Transition &ault0 I &ault0Path dela" Fault% rid)un) &ault And e,!lain

    the dierence bet$een stuc/ at and transition

    &aults%

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    - 5o$ "ou started anal"sin) co(era)e?

    6-What is hierachical re!ort?

    17- Wh" some 8o!s le&t non-scanned?

    11-5o$ did "ou )et co(era)e on non-scanned-

     !aths?

    12-What is 9no-&aults9 ?

    5o$ "ou can sa" that "ou can 9no-&ault9

    somethin)? What about the co(era)e o& that 

    area?

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    13- 5o$ "ou co(ered com!le, 9combo-lo)ic9

    bloc/s? :; ho$ "ou )ot &ull controlabilt" and 

    :bser(anilit" on com!le, combo%

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    1- What do "ou do $hile !er&ormin) 8o!-

    stichin) there are some ne)ati(e ed)e and

    some !oseti(e ed)e based 8o!s? 5o$ "ou $il 

    handle this situation?

    16% +,!lain $hat is &ault colla!sin) ?

    +,!lain in terms o& &ault dominance and Fault eui(alence%

    27% I& scan $as &ailin) and "ou slo$ do$n the

    cloc/ and it starts to !ass $hat $as the cause

    o& the &ailure in the be)innin)? Setu! or 5old

    time?

    21%Gi(e three im!ortant Cloc/ drc rules and ho$ to =, them?

    22%What is STI< !rocedure =le? What does it 

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    contains?

    23% What is scannabilit" chec/in) or Scan inte-

    )rit"? 5o$ "ou chec/ it?

    24% 5o$ im!ortant is scan chain balancin) in

    FT? 5o$ it eects in desi)ns i& the chains ar 

    not balanced?

    2#%

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    2'% Which 8o!s to a(oid &or scan?

     2*%5o$ do $e ma/e sure that each 8o! is

    )ettin) cloc/ and reset? Is a se!arate test clo

    used or it is the &unctional cloc/?

    2% 5o$ to decide the number o& chains?

    26% ierence bet$een normal 8o! and 

    scan 8o!?

    37% What is To! o& ATPG?

    31% Wh" don9t $e add buer instead o&

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    33%What is the dierence bet$een de&ect0

    &ault and &ailure?

    34%5o$ $e a!!l" i>!9s durin) simulation time

    and durin) AT+ time?

    OR

    What is serial loadin) and !arallel loadin)?

    3#%5o$ reset aected in co(era)e?

    OR

    Wh" did $e a!!lied reset &ro to! le(el?

    3'% What is bloc/ le(el ATPG?

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    3*% +,!lain about Fault Classes?.ention the Fault Class 5ierarch"%

    3% What is Controlabilit" and :bser(abilit"?

    36%What is

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    co(era)e0less !atterns and better controlabil-

    it"?

    Why we go for MBIST?

     41%Wh" in com!are to

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    what are wrapper chains?

    what is asi! "atterns # si$u%ate "atterns?

    How technology impacts '(%?

    'ow to get !overage on reset "in?

    what is the difference between pre drc check and post drc check in '(% compiler ?

    Why there is difference in the pattern count and test coverage between the two methods) *+$ and *+??

    'ow to !over the fau%ts on inter !%o!k o$ain !rossing?

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    Answers

    ATPG is a automatic test pattern generation process which takes a gate-

    level netlist along with some i/o constraints, clock defnitions, scan def-

    nitions and generates a test patterns which can be used to fnd manuact-

    uring deects in a real silocon!

    "t also produces a ault coverage report that tells #ou how good #our test

    is and which are covered and non covered nets b# test patterns!

     The process o replacing ordinar# se$uential element into a scan se$uen-

    tial element or the sake o better controlabilit# and observabilit# b#

     adding scan signals %&',&(",&(O) and mu* and making it into scannable

     element is called &can "nsertion! And the series o scannable se$uential

    elements stitched together is called &can +hain!

    elements then the test architecture is know as ull-scan

    due to some reasons then the test architecture is known as partial-scan!

    the se$uential elements in the ull scan design , so we can see the combo

    ! ogic between the se$uential elements, &o the ATPG tool take this

    combo logic into consideration and generates combo patterns !

     This is also a reason wh# no! o patterns are less in +ombo! ATPG!

    the two scan .s there are non-scan .s along with the combo logic!

    &o onl# combo patterns are not enough or them we re$uired se$uential

    patterns or them! This is the reason ATPG tool has to generate patterns

    with multiple clock pulses!

    &o pattern count and runtime is much more than combo ATPG!

    " all the se$uential elements are converted into scannable se$uential

    elements into the design then the design is eectivel# reduced to a

    combo! Onl# sets o circuits surrounded b# primar# i/o.s!

     This simplifcation allows the combo! ATPG tool to be used in more

    eective wa#!

    ault +overage- A test pattern should target ever# possible aults in the

    design but at times it might not to be possible to target ever# possible

    ault in the design!

     The ratio o aults targeted to the possible no! o aults is called as

    ull &can- " all the se$uential elements are converted into scannable

    Partial &can- " some non-scanned se$uential elements are let in design

    +ombinational ATPG- The idea is to control and observe the values in all

    &e$uential ATPG- 0e use this or partial scan design where between

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    ault coverage!

    either high1 or low2 is stucked on node!&o we want to detect that a particular node can toggle rom 2 to 1 and

    1 to 2!

    ensure that 2 to 1 and 1 to 2 happens but this time we have a time

    constraint to see toggeling is happening in that given time constraint!

    " it is not happening in certain amount o time then there is a transition-

    ault!

    &tuck at ault is what which is either connected to ground or vdd while in

    transition ault i a node is not toggeling in certain amount o time then we can sa# that node is slow to rise or slow to all!

    paths in our design

    "t e*ercise the critical paths at-speed %the ull operating speed o chip)

    to detect weather the path is too slow because o manuacturing deects

    or variations!

    "ncorrect feld o*cide thickness could lead to slower singal propagation,

    which could cause transition along a critical path to arrive too late!

    which causes two normall# unconnected singnal nets in a device to

    become electricall# connected due to incorrect etching !

    &uch deects can be detected i one o the nets causes the other net to

    take on a ault# value!

    this ault we need to measure the amount o current drawn b# a +3O& device in a $uiescent state!

    +3O& circuits almost draws no current in $uiescent state! 4uiescent

    means the i/o.s are stable and the circuit is inactive!

    " circuit has designed correctl# the amount o curent is e*treme small in

    $uiescent state and i signifcant amount o current is there then it

    indicates the presence o one or more deects!

    ault +overage5 aults detected/ Total no! o aults!

     Test +overage5 aults detected/ (etectable aults

    &tuck At ault- "t is a static check as the name suggests a particular value

     Transition ault- 6ere the node is same, toggle is same ! we have to

    Path (ela# ault- "s useul or testing and characterising critical timing

    7ridging ault - 7ridging%or short) is common deect in semiconductor

    "((4 ault- "t is a t#pe o ault which occurs in +3O& circuits! To detect

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    " started working on given ault list! " picked up the list o those classes,

    or e*ample A8%atpg untestable) so, A8 is the thing which bring down the

    coverage thus " picked up A8 list and started to improvisation o coverage

    and " observed one particular block so tried to reporting the hierachical-

    report or that block!

    &o rom the hierachical report " picked up