Microwave Characterization and Modeling of High Aspect Ratio Through-Wafer Interconnect Vias in...

2472 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 8, AUGUST 2005

Microwave Characterization and Modeling of HighAspect Ratio Through-Wafer Interconnect

Vias in Silicon SubstratesLydia Lap Wai Leung, Student Member, IEEE, and Kevin J. Chen, Member, IEEE

Abstract—In this paper, we present the detailed fabrica-tion process, high-frequency characterization, and modeling ofthrough-wafer copper-filled vias ranging from 50- to 70- m-indiameter on 400- m-thick silicon substrates. The high aspect ratiovia-holes were fabricated by carefully optimizing the inductivelycoupled plasma deep reactive ion etching process. The high aspectratio via-holes are completely filled with copper using a bottom-upelectroplating approach. The fabricated vias were characterizedusing different resonating structures based on which the induc-tance and resistance of the filled via-holes are extracted. For asingle 70- m via, the inductance and resistance are measured tobe 254 pH and 0.1 , respectively. In addition, the effect of thephysical arrangement and distribution in multiple-via configu-rations on the resulting inductance is also evaluated with doublestraightly aligned quadruple and diagonally aligned quadruplevias. Physical mechanisms of the dependence was depicted by elec-tromagnetic simulation. An equivalent-circuit model is proposedand model parameters are extracted to provide good agreement.

Index Terms—Microelectromechanical systems (MEMS), RFpackaging, silicon substrate, through-wafer interconnects (TWIs),via-holes.

I. INTRODUCTION

AS THE demand for high-performance low-cost RF/mi-crowave systems increases, there is a strong interest in

pursuing low-cost interconnect and packaging solutions thatcan deliver low resistance, low inductance, and low capaci-tance. Through-wafer interconnect (TWI) vias have recentlyattracted a great deal of interest owing to their high densityand versatile applications. Small-size TWI vias, which canbe closely packed, are needed for high density, reliable pack-aging, and testing of current and future systems includingRF microelectromechanical systems (MEMS) [1]. From thehigh-frequency circuit point-of-view, the TWI vias can be usedto replace bond wires that add parasitics to the overall circuitryoperating at RF. The wire bonding process is not a batchprocess and counts for a significant portion of the back-endproduction cost. The development of the TWI technology haspicked up speed lately with the advancement of the deep dryetching techniques for silicon substrates [2]. Via-holes with an

Manuscript received May 28, 2004; revised February 7, 2005. This workwas supported in part by the Institute of Integrated Micro-Systems and bythe Research Grant Council of Hong Kong Government under Grant HKUSTI2MS01/02.EG05 and Grant HKUST6173/02E.

The authors are with the Department of Electrical and Electronic Engineering,Hong Kong University of Science and Technology, Hong Kong (e-mail:[email protected]).

Digital Object Identifier 10.1109/TMTT.2005.852782

aspect ratio as high as 50 have been demonstrated on siliconsubstrates. The most challenging task in TWI fabrication isto fill up the high aspect ratio via-holes with void-free highlyconductive materials. Recent reports on TWI via-holes includeattempts to fill the via-holes partially by a metal coating layer[3] or fill the via-holes by polysilicon [4], [5], both of whichdeliver moderate electrical conductivity. Another recent studyattempted to fill the via-holes with Au–Sn solder using amolten metal suction method [6]. By thinning down the siliconsubstrate, before or after the etching of the high aspect ratiovia-holes, the difficulty in metal filling of the vias can be eased[7]–[9] and vias filled with copper with an aspect ratio of 14has been achieved on a 100- m-thick wafer [8]. Moreover,sacrificial wafers have to be used to facilitate the electroplatingprocess [7], [10].

In this paper, we report the first successful demonstration ofcopper-filled via-holes in a 400- m-thick (standard for CMOStechnology) silicon substrate using bottom-up electroplating[11]. Our motivation of fabricating TWI via-holes in a thicksilicon substrate are twofold. First, thicker substrate favorscertain microwave components, e.g., patch antennas for widerbandwidth and microstrip lines for wider linewidth that pro-duces lower resistance. The vias here are used to provide signalfeeding or shorting paths. Second, wafer thinning is normallythe final step before wafer dicing and the thinned wafers arenormally too fragile to be allowed back to the standard fabrica-tion line. A thicker wafer allows additional processes after thevia-hole formation. Furthermore, via-holes may be blocked bythe particles generated during the thinning process and, hence,the overall yield of the process will be lowered. TWI via-holeswith a diameter ranging from 50 to 70 m filled with copperwere fabricated. Different resonant structures are designedto characterize the resistance and inductance of the vias atmicrowave frequencies. The effect of the physical arrangementand distribution of multiple vias on the shorting efficiency isdiscussed. Moreover, an equivalent-circuit model, which cansimply be incorporated into circuit simulation, is presented forthe TWI vias.

II. FABRICATION OF THROUGH-WAFER VIA-HOLES

The complete fabrication process of the TWI vias is shown inFig. 1. The formation of TWI via-holes requires the complete re-moval of silicon in the via-hole region. This can be achieved bythe inductively coupled plasma deep reactive ion etching (ICPDRIE). A 3- m low-temperature oxide (LTO) layer was formed

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LEUNG AND CHEN: MICROWAVE CHARACTERIZATION AND MODELING OF HIGH ASPECT RATIO TWI VIAS 2473

Fig. 1. Fabrication process of the TWI vias.

on the front side of 4-in-high resistivity (3000 cm) siliconwafers with thickness of 400 m as the etching mask for ICPDRIE. To avoid the etching of the chuck that was exposed inthe through holes, a thin layer of oxide was deposited on thebackside of the wafers for protection and a dummy wafer wasplaced between the processed wafer and chuck. The thin oxidecan also be utilized to alleviate the notching effect at the end ofthe etch-through process. The ICP process comprises alterna-tive etching SF and passivation C F steps. The LTO hasa good selectivity of 1 : 300 with the silicon during the etchingprocess. Via-holes with diameters of 40, 50, 60, and 70 m havesuccessfully been etched through on the 400- m-thick wafer bycarefully controlling and performing the alternative processesfor 300 min. For the purpose of examining the etching and elec-troplating process, via-hole arrays with different diameters werebuilt as one of the testing structures, as shown in Fig. 2(a).

Fig. 3 shows the scanning electron microscope (SEM) imageof the cross section of the 50- m via-holes array that has beenetched through the wafer. It should be noted that the “notches”were formed at the bottom of the larger via-holes where theetching rate was faster. Table I summarizes the etching rate forvia-holes with different diameter size. The larger the exposedarea, the faster the etch rate. When via-holes with different di-ameters are etched at the same time, the larger holes are etchedthrough first and continuation of the etching process introducesthe “notches” at the bottom of the via-holes. Hence, it is sug-gested that via-holes with the same diameter size are designedfor the same etching run to minimize the notching effect at the

Fig. 2. Testing structures. (a) Via-hole array. (b) Simple short. (c) T-resonator.

Fig. 3. SEM image of the 50-�m-diameter via-holes through a 400-�m-thicksilicon substrate after 300-min ICP etching.

TABLE IETCHING RATE OF THE VIA-HOLES WITH DIFFERENT DIMENSION

bottom of the larger via-holes. After the ICP etching, the oxideat the backside of the wafer was removed using buffer oxide etch(BOE) to ensure complete opening of the via-holes. To avoidthe diffusion of copper into the silicon substrate, a thin layerof PECVD silicon nitride, which has good conformity, was de-posited. Before filling the via-holes by electroplating, the back-side of the wafer was sputtered with a thin layer of TiW (300 )and copper (3000 ) seed. During the early stage of the electro-plating process, the copper electroplating started from the back-side of the wafer. The bottom of the via-holes was blocked bythe electroplated copper, after which the holes got filled up fromthe bottom to the top. The side and top views of the half-filled50- m via-holes array are shown in Fig. 4(a) and (b), respec-tively. Agitation is needed to ensure uniform plating and to re-plenish the high aspect ratio via-holes with Cu ions. A dc currentdensity of 15 mA/cm was used throughout the process. Fig. 5shows an SEM image of the completely filled 70- m via-holesafter 3 h of electroplating. The image clearly shows that there isno void inside the via-holes and the copper inside the via-holeswas uniformly formed.

To characterize the impedance of the vias at microwave fre-quencies, testing structures incorporating transmission lines andvias shown in Fig. 2(b) and (c) were designed and fabricated.The microstrip transmission lines using thick copper were built



Fig. 4. (a) Side and (b) top views of the 50-�m via-holes with the bottomblocked and the holes half filled.

(a) (b)

Fig. 5. SEM image of the 70-�m via array fully filled with copper after 3-helectroplating. (a) Top view. (b) Side view.

Fig. 6. (a) Illustration of the current path from the testing via to the ground.(b) Equivalent circuit model of the simple short structure before deembedding.

on the front side of the wafer. A planarization step must be doneon the front side of the wafer to remove any metal overfills ofthe via-holes, which adversely affect the photolithography pat-terning. A TiW/Cu seed layer with the same thickness as that

Fig. 7. Structures used for the deembedding. (a) Open pad. (b) Simple shortwith a 50- �m testing via.

Fig. 8. Via arrangement under test. (a) Single via. (b) Double vias.(c) Quadruple vias (diagonally). (d) Quadruple vias (straightly).

sputtered on the backside was deposited on the front side andwas patterned using thick photoresist (12 m). Deep slots withthe shape of the microstrip lines were formed on the thick pho-toresist. In these slots [12], 4- m copper was deposited in aself-aligned fashion using electroplating, and its thickness canbe controlled by the electroplating time. Finally, the photoresistand TiW/Cu seed layers were removed by chemical strippingand etching.

III. MICROWAVE CHARACTERIZATION OF THE TWI VIAS

Microstrip lines with a linewidth of 343 m were fabri-cated. On-wafer -parameters were measured from 100 MHzto 20 GHz using an Agilent 8722ES network analyzer andCascade microwave ground–signal–ground (GSG) probes.

A. Deembedding Method

The signal path and corresponding equivalent-circuit modelof the simple short structure used for the characterization of thethrough-wafer via over a wide frequency range are shown inFig. 6(a) and (b) respectively. The signal-to-ground path con-sists of the probing pad, the vias under test, the ground plane,and the vias on the pads that connect the ground plane to theground pads. In order to accurately extract the impedance ofthe through-wafer vias under testing, the coupling capacitancebetween the signal and ground pads ( ) and the parasitics of



TABLE IISUMMARY OF THE MEASURED INDUCTANCE AND RESISTANCE

OF THE VIAS WITH DIFFERENT DIAMETERS AT 2 GHz

Fig. 9. Measured inductance of the one-port test structure with: (a) one viaand (b) four vias straightly aligned on the 400-�m high-resistivity silicon withdifferent diameter.

the through-wafer vias in the ground pads ( ) must beremoved. The coupling capacitance ( ) can be deembeddedby subtracting the -parameters of an open pad, as shown inFig. 7(a), from the measured admittance

, where is the measured -parameter of the testingstructure and is the measured -parameter of the openpad. To estimate the parasitic impedance of the ground pad vias,a simple short structure, as shown in Fig. 7(b) with a 50- m

Fig. 10. Measured resistance of the one-port test structure with: (a) one viaand (b) four vias straightly aligned on the 400-�m HRS with different diameter.

testing via, which is the same as that in the ground pads, isused. The parasitics of the pad via is estimated as

. A single 50- m via is used to provide a signal re-turn path from the ground plane (backside of the wafer) to theground pads for all the testing structures in this study. Hence,the complete deembedding procedures are as follows.

• Open-pad deembedding

• Ground pad vias deembedding

B. TWI Vias Impedance

The vias impedance was characterized [13] using the simpleshorts and half-wavelength T-resonator structures, as shown inFig. 2(b) and (c), respectively. In the simple short configura-tion, the real and imaginary parts of are taken as the



Fig. 11. Simulated charge density in the vias at resonant frequency of theT-resonator. (a) Single via. (b) Double vias. (c) Quadruple vias (diagonally).(d) Quadruple vias (straightly).

resistance and reactance of the vias, respectively, after deem-bedding. The configuration shown in Fig. 2(c) occupies a largerchip area, but delivers higher accuracy, and is used to investi-gate the effect of via arrangement, as shown in Fig. 8. Single viaand closely coupled multiple (double and quadruple) vias werefabricated and tested. The measured resistance and inductanceof the single via and quadruple vias at 2 GHz are summarizedin Table II. The frequency dependences of the inductance andresistance from 0.5 to 20 GHz are shown in Figs. 9 and 10, re-spectively. As the diameter becomes larger, both the inductanceand resistance are reduced. Furthermore, the inductance and re-sistance of the large vias are less dependent on the frequency,as the parasitic effect is relatively smaller. The inductance andresistance of the quadruple vias are reduced compared to thesingle via, but not as much as four times smaller. This is a di-rect result of mutual coupling and the proximity effect, whichis further proven by examining the charge density at the vias atthe resonant frequency of the T-resonator.

The charge distribution in the vias with different configura-tions was calculated using the full-wave simulation tool Sonnetbased on the method of moments (MoM) and is plotted inFig. 11. It can be clearly observed that at the coupling sides ofthe vias, the charge density is the minimum as a result of theproximity effect. In addition, at high frequencies, the current isconcentrated along the sidewalls of the vias due to skin effect.Hence, the resistance of the vias increases with frequency upto 20 GHz, after which the resistance starts decreasing as thesubstrate coupling effect starts to offer additional current paths.

C. Effect of Vias Distribution

Normally, multiple parallel vias are required to providelow-resistance interconnects. However, they are different fromdc and low-frequency cases, where the total resistance issimply scaled by the number of vias. The microwave frequency

Fig. 12. Measured: (a) inductance and (b) resistance of the 70-�m vias withdifferent arrangement.

characteristics of multiple parallel vias strongly depend on thephysical distribution or arrangement of these vias [14].

The measured inductance and resistance of the 70- m viaswith arrangement, as shown in Fig. 8, are compared in Fig. 12(a)and (b), respectively. It is obvious that, as the number of vias in-creases, the resultant inductance and resistance decrease. Also,the inductance of the straightly aligned quadruple vias is smallerthan that of the diagonally aligned quadruple vias. This is dueto the nonuniform current distribution in the microstrip-via tran-sition. The current is concentrated near the leading edge of thevias. As a result, the two leading vias in the diagonally alignedquadruple configuration contribute most to the current conduc-tion. The straightly aligned quadruple configuration favors theefficient usage of the four vias and exhibits the smallest resis-tance and inductance.

The full-wave simulation tool Sonnet is used to evaluate thecurrent distribution in different vias. It can be recognized fromFig. 13 that the more the number of vias along the edge, thesmaller the amount of current flows along the shorting edge,which is a good indicator of the shorting efficiency. Also, the



Fig. 13. Simulated current distribution along the shorting edge of theT-resonator at resonant frequency. (a) Single via. (b) Double vias. (c) Quadruplevias (diagonally). (d) Quadruple vias (straightly) (dashed circle in (c) and (d)are added to outline the boundaries of the via-holes for clarity).

current density at the shorting edges of the straightly alignedquadruple vias is the minimum among the four configurationsshown in Fig. 8. It can be concluded that arranging the viasin a straight line perpendicular to the current flow is the mosteffective way of shorting RF/microwave signals to the ground,which coincides with the results that we observed in the resonantfrequency of the T-resonator. Moreover, the two leading vias inthe diagonally aligned quadruple configuration contribute mostto the current conduction.

The measured input impedance of the simple short structuresis compared with the simulation results from the full-wave sim-ulator Sonnet, as shown in Fig. 14. The real part of the mea-sured input impedance is much higher than the simulated oneat high frequency. This is due to the fact that, at high frequency( 5 GHz), the skin depth becomes less than 1 m. However,the mesh used in the simulation is larger than 1 m in order tosave memory and time. Hence, the increase in resistance cannotbe captured at very high frequency. Also, the effect of the semi-conducting Si substrate at high frequency is not fully reflectedin electromagnetic (EM) simulation. The imaginary part of themeasured input impedance agrees well with the simulated oneup to 10 GHz, as the imaginary part is less dependent on the skineffect and substrate conductivity.

The T-resonator structure shown in Fig. 2(c) was used to pro-vide accurate characterization on the distribution effect of thevias. In this structure, both ends of the half-wavelength trans-mission lines are connected to the ground through TWI vias. Ashort-circuited resonator will resonate when the electrical lengthof each microstrip arm is . The resonant frequency is the fre-quency at which the magnitude of the reflection coefficientis minimized. If vias are used to short the resonator, the via in-ductance will lengthen the apparent length of the resonatorby [13] and can be estimated as

Fig. 14. Comparison of the simulated and measured input impedanceZ of the simple short structure (solid line: model, symbol:measurement).

where is the characteristics impedance of the line (50 ) andis the propagation velocity. The vertical microstrip shown

in Fig. 2(c) serves as the signal feeding line and the signal iscoupled to the resonator arms through the capacitive gap at themidpoint of the horizontal microstrip. The resonant frequencyof a perfectly shorted T-resonator is 10 GHz. The simulatedand measured return loss of the T-resonator with a differentvia shorting arrangement are shown in Figs. 15 and 16. Thereis a good agreement between the simulated and measured res-onate frequency, which depends on the parasitic inductance in-troduced by the TWI vias. In the presence of the inductance ofthe vias, the resonant frequency of the structure is lowered. Itcan be observed that the straightly aligned quadruple configura-tion exhibits the lowest inductance and introduces the smallestshift in resonant frequency, whereas the single via provides thehighest inductance and largest frequency shift.

D. Modeling of the TWI Vias

As frequency increases, the parasitic effect introduced bythe TWI vias becomes more prominent and the effect must



Fig. 15. Simulated return loss of the 10-GHz T-resonator with different viaarrangement as a function of frequency from EM simulator IE3D.

Fig. 16. Measured return loss of the 10-GHz T-resonator with different viaarrangement as a function of frequency.

Fig. 17. Equivalent-circuit model for the TWI via.

be taken into consideration during the design process. Whilethe full-wave EM simulations can give guidelines on fielddistribution, it is still a challenging task to incorporate themto circuit simulations due to long computing time, which isa stringent requirement for the setup of boundary conditions.As a result, a compact equivalent-circuit model, which canbe easily incorporated into circuit simulation, as shown inFig. 17, has been derived for the TWI vias. The TWI via ismodeled by the frequency-dependent inductance andthe frequency-dependent resistance (representing thefinite conductivity of the metal) and (representing themagnetic coupling).

TABLE IIIEXTRACTED LUMPED ELEMENT FOR THE TWI VIAS

Fig. 18. Comparison between the: (a) real and (b) imaginary parts of the70-�m TWI vias deduced from the measurement and equivalent-circuit model(solid line: model, symbol: measurement).

Due to skin effect, the current penetration into the conduc-tors varies with frequency. When the frequency is high enoughsuch that the skin depth is smaller than the radius of the circularvia-holes, the current starts to distribute unevenly and becomescrowded at the surface of the conductor. Hence, the resistanceincreases with frequency and is approximated as [15]

where is the resistance of the via(s) at 500 MHz.



The inductance decreases with frequency [16], [17] as a resultof skin effect and is approximated as

where is the inductance at 500 MHz and and areobtained by fitting the measured m .

As frequency increases, the current induced in the substrateincreases with frequency and is modeled by , which, inturn, decreases with frequency and is modeled as

where is obtained by fitting the measured . Allextracted parameters are summarized in Table III. A goodagreement between both the real and imaginary parts deducedfrom the measurement results and the equivalent-circuit modelis shown in Fig. 18.

IV. CONCLUSION

In this paper, we have demonstrated the use of ICP etchingand copper electroplating technology to achieve high aspectratio TWI via-holes on a silicon wafer with standard CMOSsubstrate thickness. A method for wide-band microwave char-acterization of the TWIs is developed. A 70- m through-wafervia with inductance of 254 pH and resistance of 0.1 hasbeen achieved. In addition, the effect of via arrangement hasbeen investigated. Low-parasitic shorting can be obtained byplacing multiple vias along the edge of the microstrip. Owingto the small size and low parasitics, the vias can be widely usedfor high-density packaging for MEMS device testing and RFapplications. In consideration of the parasitic effect of the TWIvias at higher frequency, an equivalent-circuit model, whichcan be simply incorporated into common circuit simulation,has been presented.

REFERENCES

[1] R. Ramesham and R. Ghaffarian, “Challenges in interconnect and pack-aging of microelectromechanical systems (MEMS),” in Proc. 50th Elec-tronic Components Technology Conf., Piscataway, NJ, May 2000, pp.666–675.

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Lydia Lap Wai Leung (S’01) received the B.Eng.(with first-class honor), M.Phil., and Ph.D. degreesin electrical and electronic engineering from theHong Kong University of Science and Technology(HKUST), Hong Kong, in 1998, 2000, and 2005,respectively.

From 2000 to 2001, she was a Project Engineerwith a digital audio research and development com-pany, where she was engaged in protocol design andimplementation of a 2.4-GHz wireless audio broad-casting system. She is currently a Research Associate

with the Wireless Communication Laboratory, Department of Electrical andElectronic Engineering, HKUST, where she is involved with the realization ofon-chip metamaterials and the investigation of the response of biomaterials tomicrowaves. Her research interests include design, fabrication, characterizationand modeling of on-chip and board-level microwave/RF components, realiza-tion of high-performance and novel on-chip passives and metamaterials usingthe state-of-the-art micromachining technology, RF packaging and MEMS tech-nologies.



Kevin J. Chen (M’96) received the B.S. degree inelectronics from Peking University, Beijing, China,in 1988, and the Ph.D. degree from the University ofMaryland at College Park, in 1993.

From January 1994 to December 1995, he was aResearch Fellow with National Telephone and Tele-graph (NTT) LSI Laboratories, Atsugi, Japan, wherehe was engaged in the research and development offunctional quantum effect devices and heterojunctionfield-effect transistors (HFETs). In particular, he de-veloped the device technology for monolithic inte-

gration of resonant tunneling diodes and HFETs [metal–semiconductor field-effect transistor (MISFET) and high electron-mobility transistor (HEMT)] onboth GaAs and InP substrates for applications in ultrahigh-speed signal pro-cessing and communication systems. He also developed the Pt-based buriedgate technology that is widely used in enhancement-mode HEMT devices. From1996 to 1998, he was an Assistant Professor with the Department of ElectronicEngineering, City University of Hong Kong, where he performed research onhigh-speed device and circuit simulations. In 1999, he joined the Wireless Semi-conductor Division, Agilent Technologies Inc. (formerly the Hewlett-PackardCompany), Santa Clara, CA, where he was involved with enhancement-modepseudomorphic high electron-mobility transistor (pHEMT) RF power amplifiersused in dual-band global system for mobile communications (GSM)/digital cel-lular system (DCS) wireless handsets. His research with Agilent TechnologiesInc. has covered RF characterization and modeling of microwave transistors, RFintegrated circuits (ICs), and package design. In November 2000, he joined theDepartment of Electrical and Electronic Engineering, Hong Kong Universityof Science and Technology, Hong Kong. His research interests include fabrica-tion, characterization, and modeling techniques of novel RF/microwave devices,RF/microwave power amplifiers, RF packaging technologies and MEMS.


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