MAP Notes_ CHapter 2 Part 1

7/25/2019 MAP Notes_ CHapter 2 Part 1

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MAP notes

Chapter 2: 16 Bit Microprocessor: 8086 Part 1

Q1. List the features of 8086 microprocessor.

It requires +5V power supply

It is a 40 pin IC

Available in three clock rates: 5! an" #0 M$%

It is a #& bit 'icroprocessor

(i%e o) "ata bus is #& bits

(i%e o) a""ress bus is *0 bits

irect 'e'ory access upto #Mb , 220

Note:(i%e o) the 'e'ory always "epen"s on the nu'ber o) a""ress lines-

.wo separate units: /us Inter)ace nit an" 12ecution nit

12ternal Co processor 3!0! supporte"

& byte instruction queue present to help spee" up instruction e2ecution

$as 'ultiple2e" a""ress an" "ata bus

It consist two 'e'ory banks vi%- odd memory bank and even memory bank

Q2. Draw the interna architecture of 8086.


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Q!. "#pain the re$ister or$ani%ation of 8086

General purpose registers:

.here are in all 4 6eneral purpose re6isters vi%- A7 /7 C7 7 each o) #& bits i-e- * bytes

i-e- # wor"- .hese 4 re6isters are actually are pairs o) ! re6isters vi%- A$ A8 /$ /8 C$

C8 $ 8 each o) ! bits i-e- # byte- .he letter 7 speci)y co'plete #& bit re6ister- .he

letters 8 an" $ speci)y lower an" hi6her bytes o) a re6ister-

Segment registers:

.here are 4 se6'ent re6isters in theBus interface unit si%e o) each se6'ent re6ister is #&

bits-

Co"e (e6'ent 9e6ister 3C( re6ister

ata (e6'ent 9e6ister 3( re6ister

12tra (e6'ent 9e6ister 31( re6ister

(tack (e6'ent 9e6ister 3(( re6ister


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(e6'ent re6isters 6ive the base address (segment address)to select any 'e'ory se6'ent-

Operand register or Temporary register:

It is a #& bit re6ister which can store #& bit "ata- .his re6ister cannot be use" by the

pro6ra''eruser- It is use" by the ;p to store inter'e"iate "ata or results there)ore it is

calle" as te'porary re6ister-

Pointers and nde! "egisters:

.he #& bit re6ister )ro' where the ;p will take #& bit e))ective a""ress is calle" memory

pointer#

.here are three pointer re6isters as )ollows:

< Instruction pointer 3IP

< (tack Pointer 3(P

< /ase Pointer 3/P

Also there are * in"e2 re6isters which have 'ultiple purposes such as:

< Can be use" )or pointer a""ressin6 o) "ata

< se" as source in so'e strin6 processin6 instructions

< se" to store =))set a""ress

Note:.he in"e2 re6isters are also a type o) 'e'ory pointers but havin6 'ultiple purpose

.here are two in"e2 re6isters as )ollows:

< (ource In"e2 re6ister 3(I < estination In"e2 9e6ister 3I

Q&. "#pain the specia uses of $enera purpose re$isters.

#- $%&$' ($ccumulator): It is inter'e"iate re6ister between the A8 an" the

'e'ory- Mostly but not always the results o) arith'etic an" lo6ical operations are

store" in the accu'ulator an" then )ro' there it is trans)erre" to wherever require"-

It is the 'ost i'portant 6eneral purpose re6ister o) the ;p-

g: >hen the instruction * B% is e2ecute" what the ;p "oes is that it "ivi"econtent o) A7 re6ister with the content o) /8 re6ister by "e)ault an" a)ter "ivi"in6 the


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quotient is by "e)ault store" in the A8 re6ister an" re'ain"er is store" in the A$

re6ister-

*- B' (Base "egister): .o select any 'e'ory location particularly in the "ata

se6'ent we require two a""resses : base a""ress 3store" in the se6'ent re6ister an"

o))set a""ress which can be store" in the base re6ister in certain a""ressin6 'o"es-

?- +%&+' (+ounter "egister):It is use" as a "e)ault counter re6ister "urin6 loop

shi)t rotate repeat instructions- It can be use" as ! bit counter as well as #& bit

counter-

4-' (ata register):urin6 'ultiplication an" "ivision operations when the result

6oes beyon" #& bits i-e- ?*bits then the upper #& bits are store" in the 7 re6ister-

Q'. Draw the fa$ re$ister of 8086. "#pain the status fa$s.

+arry ,lag:

urin6 an a""ition operation i) a carry is 6enerate" )ro' the M(/ or "urin6 a subtraction

operation a borrow is 6enerate" carry )la6 sets in"icatin6 a carry or borrow respectively-

.here)ore when

C@ , # carry is 6enerate"

C@ , 0 carry not 6enerate"

$u!iliary carry flag:

urin6 an a""ition operation i) a carry is 6enerate" )ro' the lower nibble to the hi6her nibble

then AC )la6 sets-

Parity flag:

>hen an a""ition subtraction 'ultiplication "ivision or any lo6ical operation takes place

then "epen"in6 on the result the parity )la6 6ets a))ecte"-

;p checks the ! 8(/Bs o) the result:


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I) the nu'ber o) oneBs in the ! 8(/Bs are 0*4&! then the parity )la6 sets i-e- P@ , #

in"icatin6 even parity

I) the nu'ber o) oneBs in the ! 8(/Bs are #?5 then the parity )la6 resets i-e- P@ , 0

in"icatin6 o"" parity

-ero flag:

>henever any arith'etic or lo6ical operation takes place an" the result is 0 then %ero )la6 sets

to in"icate that the result is 0 i-e- @ , #-

g:8et A , !0$

/ , !0$

(/ / instruction is e2ecute"- .he result obtaine" is 00$ in A re6ister- >hen ;p checks this

it has to re)lect it so'ewhere that the result is %ero so it re)lects in bit which is reserve" )or

%ero )la6 by settin6 its value to # i-e- @ , #

Sign flag :

>henever the result o) any arith'etic operation is ne6ative the si6n )la6 sets i-e- (@ , # else

re'ain in the reset state i-e- (@ , 0-

Overflo. flag (Bit /0):

Q6. Draw the fa$ re$ister of 8086 an( e#pain the contro fa$s.

nterrupt flag (Bit /1):

Interrupt )la6 is use" to control the 'askable interrupts o) the ;p !0!& which arrive at the

ID.9 pin- 8etBs see how it controls the interrupts-

(hown above is the internal circuitry to control the 'askable interrupts- >hen /it #0 o) @la6re6ister is 0 i-e-


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I@ , 0 input to the AD 6ate is 0 there)ore op o) AD 6ate 6oes low- .here)ore any input to

the AD 6ate wonBt be reco6ni%e" hence any interrupt occurrin6 on the ID.9 pin wonBt be

acknowle"6e" as it is not reco6ni%e"-

>hen I@ , # an" interrupt on the ID.9 pin occurs it is reco6ni%e" an" 6iven to the internal

ID.9 circuitry throu6h AD 6ate an" then acknowle"6e"-

Trap ,lag (Bit 2):

.his )la6 is use" to "etect any error in the pro6ra' 3"ebu66in6 by e2ecutin6 the pro6ra' in

sin6le steppin6 'o"e-

< I) lo6ic 0 is store" in .@ then the ;p will e2ecute all the instructions o) a pro6ra' in one

operation 3)ree run operation

g:>hen we e2ecute the pro6ra' an" press key @E the entire pro6ra' 6ets e2ecute" in one

stroke- .he i'p- Point to un"erstan" is that when we press the key @E value 0 6ets place" bit

E o) the )la6 re6ister there)ore .rap )la6 resets i-e- .@ , 0-

< I) lo6ic # is store" in .@ then the ;p will e2ecute one instruction o) the pro6ra' at a ti'e

a)ter e2ecutin6 each instruction ;p will e2ecute ID.# 3so)tware interrupt so ;p will branch

)ro' 'ain pro6ra' to subroutine-

.he subroutine has a pro6ra' which "isplays the result in "i))erent re6isters o) ;p on the

screen so a)ter each instruction the pro6ra''er can veri)y the result-

g:>e use @! )unction key to e2ecute the pro6ra' in sin6le steppin6 'o"e- >hen we press

key @! value # 6ets place" into bit E o) )la6 re6ister hence trap )la6 sets i-e- .@ , #-

irection ,lag (Bit //):

In the above e2a'ple we see two 'e'ory blocks- .he o))set a""ress o) )irst 'e'ory block is

place" in the (I re6ister an" o))set a""ress o) the secon" 'e'ory block is place" in the I

re6ister-

Dow we nee" to 'anually incre'ent (I an" I a)ter each byte trans)er )ro' "ata se6'ent to

e2tra se6'ent-

.o avoi" all this what we "o is a)ter 'ovin6 one byte )ro' Data se$ment to e#tra se$ment

we clear the "irection )la6 3C8 instruction is use" to clear the "irection )la6 which puts (I

an" I in auto incre'ent 'o"e-

In other wor"s whenever @ , 0 (I an" I incre'ent auto'atically-


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I) we are copyin6 the "ata )ro' the last location we set the "irection )la6 3(. instruction is

use" to set the "irection )la6 which puts the (I an" I in auto "ecre'ent 'o"e-

In other wor"s whenever @ , # (I an" I "ecre'ent auto'atically-

Q). "#pain how *ueuin$ spee(s up the processin$ of 8086 operations.

.his queue is base" on +,+- first in first out/basis which 'eans that the byte which

co'es )irst also 6oes out )irst )ro' this re6ister-

;p !0!& has create" * lo6ical units within its architecture one is the bus inter)ace unit 3/I

an" the other is the e2ecution unit 31-

>hile the 1 is "eco"in6 an instruction or e2ecutin6 an instruction which "oes not requirethe use o) buses the /I )etches upto si2 bytes )ro' the 'e'ory-

.he /I stores these pre)etch bytes in +,+- re$istercalle" as *ueue re$ister.

>hen the 1 is rea"y )or the ne2t instruction it si'ply takes 3)etches the ne2t byte )ro' the

instruction queue in the /I-

.his is 'uch )aster than sen"in6 out a""ress to the syste' 'e'ory an" waitin6 )or 'e'ory

to sen" back the ne2t instruction bytes-

.his is a si'ple e2a'ple o) a car manufacturerwhich "e)ines a person to 'ake a car- Dow

that person starts 'akin6 the en6ine then on its co'pletion he starts preparin6 the outerbo"y an" continues-

>e nee" to un"erstan" is that the person is co'pletin6 one task an" then startin6 another

hence to 'anu)acture one car will take a lot o) ti'e-

.he 'anu)acturer ca'e up with an i"ea that why not increase 'y sta))- Instea" o) one sta))

IBll 'ake it 5-

@irst : 1n6ine 'anu)acture

(econ" : /o"y 'anu)acture

.hir" : (eat 'anu)acture


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@ourth : Paintin6

@i)th : .yre 'anu)acture

Dow what happens that the work 6ot "ivi"e" an" each person is busy- A)ter co'pletion o)

)irst 'o"ule it 6oes to secon" an" so on till the )i)th-

(o every 'o"ule is continuously busy an" the work 6ot "ivi"e"-

# person can "o the work in # sec now the work 6ot "ivi"e" but )irst ti'e all the 'o"ules

are in wait state an" waitin6 )or the previous one to co'plete i-e- M* is waitin6 )or M# to

co'plete- (o ti'e taken is sa'e i-e- #s- /ut a)ter the entire cycle is co'plete once now the

ti'e taken is only 0-* sec-

Q8. List the steps in phsica a((ress $eneration in 8086 microprocessor. Cacuate the

phsica a((ress for the $ien C 3 2!&045 ,P 3 )674.

(ince a""ress bus is o) *0 bits , Physical a""ress is o) *0 bits

.he calculation is as )ollows:

Physical a""ress 3PA , /A + 1A

/ut a""ition is a little "i))erent letBs un"erstan" with an e2a'ple:

8et /A , #000$ , 000# 0000 0000 0000 , #& bit

1A , ?4&$ , 00## 0#00 0##0 0### , #& bit

Dow base a""ress is always appendedwith 04i-e- 0000Bat the en" internally by the

;p-

.here)ore /A now beco'es , 000# 0000 0000 0000 0000, #00004

Dow

PA , 000# 0000 0000 0000 0000 , #00004

+ 00## 0#00 0##0 0### , ?4&$


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000# 00## 0#00 0##0 0### , #?4&$


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ebugger:

It enables the pro6ra' to be loa"e" into the syste' 'e'ory e2ecute it an" then

"ebu6 it- It also enables to insert breakpoints at any "esire" locations chan6e the

content o) re6ister 'e'ory location an" rerun the pro6ra'-

Q10. "#pain memor se$mentation.

.he ;p !0!& has *0 a""ress lines there)ore the nu'ber o) 'e'ory locations it can

access is 220

, #04!5& , # Mb-

A""ress varies )ro' 0000 0000 0000 0000 0000

#### #### #### #### ####

$ence our 'ain ai' is to access a 'e'ory location an" )ro' there access "ata-

.he 'ain point to un"erstan" is that the si%e o) the re6isters is #& bit an" a""ress is o)

*0 bits-

.here)ore !0!& uses the 'e'ory se6'entation sche'e to access # Mb o) 'e'ory or

#M locations-

.he 'e'ory is "ivi"e" into segments or blocks#.he lengt4o) the se6'ent is 56 7b-

.wo re6isters are use" one to access a se6'ent an" one to 'ove within the se6'ent

3select any location within the se6'ent-

Consi"er the 'e'ory 6iven on ne2t sli"e:

.wo steps to access any location within a 'e'ory:

(elect the se6'ent with the help o) base address or segment address (starting

address (indicating start of any segment)#It 'eans that the se6'ent re6ister contains

the base a""ress with the help o) which we are able to select any se6'ent-

Dow to 'ove within the se6'ent or in other wor"s to select any location within the

se6'ent we use offset address or effective addresswhich we 6et )ro' any pointer or

in"e2 re6ister or any 6eneral purpose re6ister-


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Dow these se6'ents are lo6ical se6'ents it 'eans that there is no physical "ivision within

the 'e'ory-.he se6'ents can either be Co"e (e6'ent ata (e6'ent 12tra (e6'ent (tack se6'ent-

Co"e se6'ent : when a se6'ent is assi6ne" as co"e se6'ent it is use" to store the co"es or

instructions

ata (e6'ent : when a se6'ent is assi6ne" as "ata se6'ent it is use" to store "ata use" in

the pro6ra's

12tra (e6'ent : it is also another se6'ent use" to store "ata

(tack (e6'ent : it is use" to store stack o) "ata an" a""ress o) 'ain pro6ra' "urin6

subroutine call

Q11. "#pain the concept of pipeinin$ in 8086

>hen one instruction is 6ettin6 "eco"e" an" e2ecute" an" si'ultaneously ne2t

instruction is bein6 )etche" )ro' the 'e'ory is calle" as pipeinin$ process.

In !0!& with the help o) queue re6ister & instruction bytes are pre)etche" in the queue

re6ister whenever the 1 requires bytes )or "eco"in6 an" e2ecution purpose it Fust

has to )etch )ro' the queue re6ister instea" o) 6oin6 to the 'ain 'e'ory an" waist itsti'e-

/y the ti'e it is "eco"in6 an" e2ecutin6 the byte )etche" )ro' the queue ;p "oes not

allow the buses to re'ain i"le the e2ternal bus 6oes to the 'e'ory an" )etches the

ne2t bytes an" places in the queue-

.his is actually parallel processin6 an" si'ilar to a water pipe where the water

continues to re'ain in 'otion- (i'ilar way the instruction bytes are in continuous

'otion i-e- )ro' the 'e'ory to the /I then into the queue then to the e2ecution unit

)or e2ecution-


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In other wor"s the 'otion o) bytes "oes not stop anywhere i"eally unless an" until a

branch instruction arises in the queue-

Note:.he ;p "oes not per)or' the ne2t )etch operation till at least two bytes o) the

instruction queue are e'ptie"-

.his is a si'ple e2a'ple o) a car manufacturerwhich "e)ines a person to 'ake a car- Dow

that person starts 'akin6 the en6ine then on its co'pletion he starts preparin6 the outer

bo"y an" continues-

>e nee" to un"erstan" is that the person is co'pletin6 one task an" then startin6 another

hence to 'anu)acture one car will take a lot o) ti'e-

# person can "o the work in # sec now the work 6ot "ivi"e" but )irst ti'e all the 'o"ulesare in wait state an" waitin6 )or the previous one to co'plete i-e- M* is waitin6 )or M# to

co'plete- (o ti'e taken is sa'e i-e- #s- /ut a)ter the entire cycle is co'plete once now the

ti'e taken is only 0-* sec-

Q12. Draw the pin (ia$ram of 8086.


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Q1!. tate the functions for the foowin$ pins of 8086

AD0AD

15 (Pin 16 - 2) - Mutipe#e( ((ress Data Bus

@ro' pin nu'ber #& G * are use" by the 'ultiple2e" a""ress "ata bus-

Multiple2in6 a""ress an" "ata lines 'eans that the sa'e lines are use" )or a""ress an" "ata-

.here)ore the sa'e lines are use" to carry a""ress in)or'ation as well as "ata-

urin6 .# state o) every 'achine cycle A81 si6nal 6oes hi6h an" enables the latches "urin6

this .# state a""ress which is 6enerate" by the ;p is available on this 'ultiple2e" bus-

A)ter .# state 6ets over A81 si6nal 6oes low which "isables the latches an" 1D si6nal also

6oes low which enables the .ransrecievers- Dow "ata is available on the 'ultiple2e" bus-

A16

/S3 A19/S6 Pin !8 !'/ Mutipe#e( a((ress status us

.hese lines work as A""ress /us 3A#& G A#E "urin6 .# state o) every 'achine cycle i-e-

when A81 si6nal 6oes hi6h-

.* onwar"s these work as status si6nals (? to (&

(? an" (4 6ives the status o) the 'e'ory se6'ent currently accesse"-

(5 6ives the status o) Interrupt @la6-

(& re'ains low in 6eneral-


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,;hen the instruction C8I is e2ecute" I@ )la6 6ets cleare" an" interrupts arrivin6 on this pin

are 'aske" 3they "onBt 6et any response-

;M, Pin 1)/:

.his is an input pin to the ;p -

It is a positive e"6e tri66ere" input-

It is a non 'askable interrupt-

@or any interrupt to be reco6ni%e" the ip at this pin shoul" be hi6h )or at least * clock cycles

>henever there is a power )ailure this pin co'es into use-

,;henever the ;p per)or's 'e'ory rea" or io rea" operation this pin

6oes low to in"icate rea" operation- .his pin is always use" alon6 with MI= to in"icate

'e'ory rea" or I= rea"-


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="D> Pin 22/:

.his is an input acknowle"6e'ent si6nal )ro' the slow peripheral "evices to the

'icroprocessor to in"icate that "ata trans)er is co'plete-

16- Printer connecte" to 'icroprocessor-

.he 'ain use o) this pin is to insert wait states into the ti'in6 o) the 'icroprocessor-

I) the 91AH pin is at lo6ic 0 level the ;p enters wait states into its ti'in6 cycle an"

re'ains i"le-

.he nee" )or this is because the spee" o) the ;p is very )ast it operates in M$% an" spee" o)

peripheral "evice like printer is slow as co'pare" to that o) the ;p- $ence ;p sen"s "ata at a

)aster rate continuously to the peripheral which 'ay cause loss o) "ata hence the peripheral

sen"s a low si6nal on the 91AH input to sen" the "ata at a slower rate by a""in6 wait states

to its ti'in6 cycle-

=nce one slot o) "ata is receive" by the peripheral then it sen"s an acknowle"6e'ent hi6h

si6nal on its input to in"icate that "ata trans)er is co'plete an" sen" the ne2t slot o) "ata-

CL? Pin 17/ Coc9:

Clock pin provi"es the basic ti'in6 si6nal to the 'icroprocessor-


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@cc Pin &0/ A ;D Pin 1 an( 20/:

Vcc i-e- +5V is applie" at pin 40 an" is use" as power supply

.here are two layers o) !0!& hence two separate D pins )or two layers o) !0!& chip are

use"- .his helps in i'prove noise reFection-

=""< Pin 21/:

It causes the processor to i''e"iately ter'inate its present activity -

.he !*!4 clock 6enerator provi"es this si6nal

.his si6nal 'ust be active 4ig4 for at least 6 clock cycles

It clears all the )la6 re6ister the instruction queue ((( 1( an" IP re6ister an" sets the bits

o) the C( re6ister$ence whenever the processor boots the reset vector a""ress o) !0!& is @@@@0$ 3as C( ,

@@@@$ an" IP , 0000$

Note:The reset vector is the default location a central processing unit will go to find the first

instruction it will execute after a reset. That is to say, the reset vector is a pointer or address

where the CPU should always begin as soon as it is able to execute instructions.

L" Pin 2'/:

A81 stan"s )or A""ress 8atch 1nable-

As we stu"ie" in the previous sli"es about latch- 8atch has an input pin (./ which is

connecte" to the op pin o) the ;p i-e- A81

As the na'e su66ests it is use" to enable the latch by 6eneratin6 a hi6h si6nal "urin6 .# state

o) every 'achine cycle-

As soon as A81 pin 6oes hi6h latches 6ets enable" a""ress which is available on the a""ress

bus 6oes to the input o) the latches where it is latche" 3it hol"s the a""ress at its op-

Dow A81 6oes low a)ter .# state 6ets over hence "isablin6 the latches 3as (./ also 6oes

low-

Dow "ata is available on the 'ultiple2e" A bus-

(ince latches are "isable" hence "ata which arrives at latches 6et no response-

hen this pin is hi6h in the 'a2i'u' 'o"e it in"icates to the 'icroprocessor that it is busy-


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>henever those instructions arrive in the pro6ra' which are "e"icate" to the co G processor

then they are sent to the co G processor )or e2ecution-

>hile the co G processor is busy e2ecutin6 those instructions it sen"s a hi6h si6nal on the

.1(. pin o) the ;p in"icatin6 that it is busy e2ecutin6 those instructions till then the ;p

re'ains in i"le state-

M;M Pin !!/:

.his is an input pin to the ;p which will in"icate the processor will work in which 'o"e-

I) input to this pin is hi6h i-e- i) the pin is connecte" to Vcc 3+5V then ;p will enter in

'ini'u' 'o"e

I) input to this pin is low i-e- i) the pin is connecte" to D 30V then ;p will enter in

'a2i'u' 'o"e

B4" S7 Pin !&/:

S7 is use" )or )uture "evelop'ent-

/$1 is active low op si6nal an" stan"s )or /us $i6h 1nable-

.his op pin is use" to activate the o"" 'e'ory bank when the op o) this pin is low it

activates the o"" 'e'ory bank an" "ata is available on the hi6her or"er "ata bus 3! G #5

I) this pin 6oes hi6h then o"" 'e'ory bank 6ets "isable" an" any type o) "ata trans)er )ro'

the hi6her or"er "ata bus is "isable"-

E= Erite Pin 27/:

.his is an op pin is use" in 'ini'u' 'o"e i-e- MDM7 , #

It is connecte" to the 'e'ory or I= "evice- >hen this pin 6oes low it in"icates write

operation-


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It is use" alon6 with MI= pin to in"icate whether 'e'ory write or io write operation-

M,- Pin 28/:

.his is an op pin use" in 'ini'u' 'o"e to "istin6uish between a 'e'ory operation an" io

operation-

>hen this pin is low it in"icates io operation an" is use" with 9 an" >9-

@or 16- MI= is hi6h an" 9 is also low whereas >9 is hi6h then 'e'ory rea" operation

takes place-

@or 16- MI= is hi6h an" >9 is also low whereas 9 is hi6h then 'e'ory write operation

takes place-

In si'ilar 'anner I= rea" an" I= write operation takes place only MI= is low-

4-LD Pin !1/:

It is input pin use" in the 'ini'u' 'o"e- .he ip co'es )ro' the MA controller which is

actin6 another bus 'aster 3as it also has "ata an" a""ress lines requestin6 the ;p to release

the syste' bus-

In response !0!& co'pletes the current 'achine cycle an" releases the syste' bus-

In other wor"s it tristates its e2ternal syste' bus-

4LD Pin !0/:

It is acknowle"6e si6nal 6enerate" by the ;p to the MA controller a)ter releasin6 the syste'

bus in"icatin6 that it has release" the syste' bus-

A)ter which MA operation takes place-

D"; Pin 26/ Data "nae:

.his pin is use" to activate the octal bus .ransreciever IC !*!& - It is connecte" to the =1 pin

o) the .ransreciever which consist o) ! bi"irectional bu))ers- Actually when 1D 6oes low=1 6oes low an" all the internal bu))ers 6et activate"-


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Dhen this pin 6oes low i-e- when .9 , 0 which in"icates receive i-e- ;p receives "ata

)ro' 'e'ory or io "evice-

In other wor"s whenever rea" operation takes place .9 6oes low hence )low o) "ata is

towar(s theFp.

S2, S

1, S

0 Pin 28 26/ tatus ines:

.hese are the active low status lines use" in 'a2i'u' 'o"e which re)lect the type o)

operation bein6 carrie" out by the processor- It in"icates which 'achine cycle is currently in

operation-

9e)er table below:


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L-C? Pin 27/:

.his pin is use" in the 'a2i'u' 'o"e-

>hen a pro6ra''er is e2ecutin6 so'e i'portant instructions "urin6 which no interrupt can

be tolerate" 3such as when we restart our co'puter an" there are so'e up"ates which the

win"ows is takin6 at that ti'e i) any other co''an" is 6iven to the PC it will not react to it

at that ti'e what the pro6ra''er "oes it writes a 8=CJ pre)i2 alon6si"e the instruction "ue

to which this pin 6oes low in"icatin6 to the e2ternal bus 'asters such as MA that it cannot

take control over the syste' bus-

>hen the ne2t instruction arrives without the 8=CJ pre)i2 then this pin 6oes hi6h an" allows

other bus 'asters to access 6ain over the syste' bus-

QS1,QS

0 Pin 2& 2'/:

K( stan"s )or queue status- It 'eans that outsi"e the chip we co'e to know what is the status

o) the queue re6ister insi"e the 'icroprocessor-

8etBs un"erstan" )ro' the table below:

RQ0 0 ,RQ1 1:

.his si6nal works in the 'a2i'u' 'o"e when 'ore than one processor is connecte" in the

syste'-

9K stan"s )or bus request- . stan"s )or bus 6rant-

0 has the hi6her priority than #- It 'eans that when two processors si'ultaneously asks the

!0!& to release the syste' bus the processor which is connecte" at pin ?# will 6et bus 6rant

)irst then the one which is connecte" at pin ?0-

.he e2ternal processor will sen" a low si6nal as a request to the ;p to release the syste' bus

the ;p will co'plete its current 'achine cycle an" release the bus i-e- it will 6rant the bus to

the bus 'aster by sen"in6 a low si6nal-

A)ter usin6 the syste' bus a6ain the e2ternal bus 'aster will sen" a low si6nal therebyreleasin6 back the syste' bus to the ;p-


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Q1&. Draw the phsica a((ress cacuation unit to $enerate 20 it phsica a((ress.

MAP Notes_ CHapter 2 Part 1

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