LN16_SeqCktDesign

1NTUEE C.M. LiLogic Design

Switching Circuits & Logic Design

Professor Chien-Mo James LiGraduate Institute of Electronics Engineering

National Taiwan University

Sequential Circuit Design


Objective of this Chapter Learn how to design a sequential circuit


Flow of Design a Sequential Ckt.

specification

State graphState Table

K-mapFF, Comb Logic

Ch 14

Ch 12Ch 13 Ch 16

Ch 15


Outline Summary of Design Procedure for Sequential Circuits. Design Example-Code Converter. Design of Iterative Circuits. Design of Sequential Circuits Using ROMs and PLAs.


Design Procedure for Seq. Ckt. 1. Determine state graph and state table 2. Reduce state table 3. State Assignment 4. Transition table 5. Next-state map input Map, output map 6. Equations and circuits


Design Example Code Converter Convert BCD code to Excess-3 code

Table 1-2 Add 3 to input sequence


Step 1. State tableX Z

Input Output(BCD) (excess-3)

t3 t2 t1 t0 t3 t2 t1 t00 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 0

Tab 16.1


Step 1. State table State graph

LSB first, MSB last

Fig. 16-1


Step 2. Reduce states

-1-AN110-1-AP111

-1-AM101-0-AL100-0-AK011-0-AJ01010AAI00110AAH000t301PKG1101NJF1001MIE0110LHD00t210GEC101FDB0t101CBAresett0X=1X=0X=1X=0

Present output(Z)

Next statePresent state

Input sequence received

timeTable 16-2


Step 2. Reduce states

-1-AM

10AAHt3

01MHE

10HHDt2

10EEC

01EDBt1

01CBAt0X=1

Present output(Z)X=0X=1

Next stat

X=0

Presentstate

Time

Table 16-3


Step 3. Assign states Figure 16-2 Adjacent states

(B,C) (D,E) (H,M) (A,B,E,M) (C,D,H)

Fig. 16-2


Step 4. Transition Table Figure 16-2 (b)

100 0 00 0 0110H

010 1 00 1 1011E

xxx x xx x x100-

x1x x x0 0 0010M

100 1 10 1 1111D

101 1 01 1 0101C

011 1 01 1 1001B

011 0 11 0 0000A

X=1X=0X=1X=0Q3Q2Q1

ZQ3+Q1+Q2+


Step 5. 6. Maps and Equations Figure 16-3

Fig. 16-3


Done! Figure 16-4


Question! Q: Why output Z is not delayed? A: Because excess-3 code = BCD code + 3

Not delay is needed from LSB to MSB


Food for Thought Q: what happens if we input MSB first?

Q: what should we do if we want to design a BCD to 6-3-1-1 converter? Table 1-2


Outline Summary of Design Procedure for Sequential Circuits. Design Example-Code Converter. Design of Iterative Circuits. Design of Sequential Circuits Using ROMs and PLAs.


Iterative Circuits Definition

An iterative circuit consist of a number of identical cells interconnected in a regular manner

Example A parallel adder consists of many full adders


Unilateral Iterative Circuit Linear array of combinational cells with signals between traveling in

only one direction Figure 16-5

X = inputs Z = outputs a = states

Fig. 16-5


Seq. Ckt. v.s. Iterative Circuits Sequential circuits

Serial input, serial output

Iterative Circuits Parallel input. Parallel output

Design of iterative circuits is very similar to design of sequential circuits Comparison

Iterative circuits receives inputs sequence in SPACE Sequential circuits receives input sequence in TIME


Design Example Comparator Specification

Input two n-bit numbers X and Y Determine if X=Y or X>Y or X


State Table for Comparator TABLE 16-4

S0 : X=Y S1: X>Y S2 :X


Next-State Map Although there is not real next state

Think of ai+1 as next state of ai

Fig. 16-7


Next-State Circuit one Cell i only

Think of ai+1 as next state of ai

Fig. 16-7


Output CircuitFig. 16-8


Whole Iterative Comparator Many next-state cells connected together

Followed by one output cell


Sequential Design Use 2FF to store states

Fig. 16-9


Food for Thought Which comparator is better?

Sequential circuit or Iterative circuit?


Outline Summary of Design Procedure for Sequential Circuits. Design Example-Code Converter. Design of Iterative Circuits. Design of Sequential Circuits Using ROMs and PLAs


Design Seq. Ckt. Using ROM Use ROM to implement comb. logic If m inputs, k state variables (using D-FF), and n outputs

Need m+k input, n+K output ROM Why?


Design Example Same BCD to excess-3 Code converter State table

Table 16-6(a) Transition table

Table 16-6(b)

Truth Table Table 16-6 (c)


-1-AM10AAH01MHE10HHD10EEC01EDB01CBAX=1

output (Z)

X=0X=1

Next stateX=0

Presentstate

Design ExampleTable 16-6 (a)


ZQ1+Q2+Q3+

1010011

X=0

--0 0 01 1 0M10 0 00 0 01 0 1H01 1 01 0 11 0 0E11 0 1 1 0 10 1 1D11 0 01 0 00 1 0C01 0 00 1 10 0 1B00 1 00 0 10 0 0A

X=1X=1X=0Q1 Q2 Q3

Design ExampleTable 16-6 (b)


Design ExampleTable 16-6 (c)

XXXX1111XXXX0111001110110100001110111101001101010000100101000001XXXX111000010110000010101011001010101100001001001101100010010000D3D2D1ZQ3Q2Q1X


Implementation Using ROM

Fig 16-10


Final Notice on ROM-based Design Use D-FF is preferable to JK FFs

Because JK-FF has two inputs that require a larger ROM

Use straight state assignment is ok, no optimal assignment needed Because area of ROM is the same regardless of the complexity of

logic e.g. If you memorize the whole 9x9 multiplication table, you do

not need any computation


Design Using PLA Same code converter Equations:

16-1

Table 16-7

Notice: state assignment does mater Straight assignment: 13 product terms Better assignment: 7 product terms

00011--100010--01000-00110000-101000111-0100--1-0010-0--D3D2D1ZQ3Q2Q1X


PAL with feedback Q+ = D = ABQ+ABQ Useful for sequential ckt.

Fig 16-11


Food for Thought Which comparator is better?

Sequential circuit or Iterative circuit?


Next Time

ch 9 Multiplexers Decoders and PLDch 11 Latches and FFch 12 Registers and Countersch 13 Analysis of Clock Sequential Cktsch 14 Derivation of State Graphs and Tablesch 16 Sequential Ckt Design ch 18 Ckts for Arith. Operations

final exam

LN16_SeqCktDesign

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