Layout-based Modeling Methodology for Millimeter-Wave MOSFETs
Transcript of Layout-based Modeling Methodology for Millimeter-Wave MOSFETs
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Layout-based Modeling Methodologyfor Millimeter-Wave MOSFETs
Yan WangInstitute of Microelectronics, Tsinghua University,Beijing, P. R. China, [email protected]
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MotivationProposed MethodologyResults and DiscussionsSummary
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Outline of Presentation
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MotivationProposed MethodologyResults and DiscussionsSummary
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Outline of Presentation
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High performance CMOS millimeter-wave applications are emerging inendless stream 5G mobile Communication full-HD video streaming, and high
speed wireless links at 60GHz 77-GHz Radar for automatic
cruising Millimeter-wave imaging system
for fine resolution using 94-GHzband
Motivation
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5G mobile Communication
THz imaging system
Radar for automatic cruising
Sync & Go
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A versatile model for mm-wave device is stillnot available in many situations, so accuratedevice models for efficient CAD simulation isneeded.
The RF model provided by PDK usuallytargets at low gigahertz applications anddoes not account for the complex highfrequency effects and parasitic effects.
CMOS circuits are fabricated on a resistivelossy substrate, and parameters associatedwith substrate parasitics must be added toconventional models.
Motivation
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mm-wave transistors usually adopt a complexmulti-finger layout.
The challenge for modeling of mm-wave FETsmainly arises from that the model is limited tointerpolated geometry range set by the largest andsmallest measured devices due to unpredictedaccuracy of extrapolation.
It's extremely difficult to build a set of equationsprecisely covering all the parasitic capacitance,resistance of local metal wires, vias and contactswhich connect a row of gate fingers, as well asfrom substrate loss over wide geometry range.
Motivation
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8TSMC65nm RF NMOS 0.1~30.1GHz, the mean-square error of Y-parameters between simulation results and measurement.
Motivation We made the assessment of NMOS multifinger
transistors by TSMC 65nm, the mean-square errorof Y-parameters between simulation andmeasurement results are shown.
The error is a little bit striking.
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Motivation
9Emami S., et al. Large-signal millimeter-wave CMOS modeling with BSIM3. RFIC-Symposium, 2004:163-166.
Most of previous models focused on a fixed model,which is usually based on the BSIM enhanced byparasitic sub-circuit.Designers in many situations have to build a model oftheir own before diving into the design of integratedmm-wave circuit. Only those
who specialize inmodeling or whohave very deepinsight in devicephysics canhandle suchthings
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In this work, a novel modeling methodology formillimeter-wave MOSFETs based on standarddigital core model is proposed and investigated.
This modeling methodology takes into accountthe layout effect and NQS effect.
The proposed modeling methodology iscompared with the measured data and goodaccuracy is achieved for a standard 90nm and65nm CMOS technology.
This proposed model has been successfullyapplied in 60GHz LNA design.
Motivation
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MotivationProposed MethodologyResults and DiscussionsSummary
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Outline of Presentation
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Digital Core Model
Layout Parasitic
Extraction
NQS Effect
3D EM Simulation
Passive Device
Circuit Simulation
Active Device
Thick Metal Layer
Flow chart of the proposed modeling methodology
Proposed Modeling Methodology
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The standard core model aiming for digital circuitanalysis is adopted directly. The core nonlinearelements such as gate drain capacitance, gate-source capacitance, output conductance, outputtransconductance, etc. can be described byBSIM.
Extrinsic parasitic linear components introducedby device interconnections and related vias canbe extracted by using Calibre xRC.
NQS effect related nonlinear MOSFETcharacteristics are far more difficult to bedetermined for mm-wave multi-finger MOSFETs.
Proposed Modeling Methodology
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……
Source Drain
Gate
Source Drain
Gate
Source Drain
Gate
Source Drain
Gate
Gate
Source Drain
QS Approximate NQS
Proposed Modeling Methodology
It is first necessary to take into account the distributed nature of the devicestructure along both its channel length and channel width.
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For a one-fingered device, the intrinsic gateresistance Rg,i is given by
,, 3
g sqg i
R WRL
=
Where Rg,sq is the DC sheet resistance of the gatematerial, W is the width of the device, and L is thelength of the channel region[1]. The factor 3 accountsfor the distributed nature of the intrinsic gateregion[2]. Rg,i increases in HF regime, in this work, it can be
determined by Calibre extraction for simpliness.[1] Andrey V. Grebennikov, and Fujiang Lin, An efficient CAD-oriented large-signal MOSFET model, VOL. 48, NO. 10, P1732(2000)[2] E. Abou-Allam and T. Manku, “A small signal MOSFET model for radio frequency IC applications,” IEEE Trans. Computer-Aided Design, pp. 437–447, May 1997
Proposed Modeling Methodology
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Rgs accounts for the fact that channel chargecannot instantaneously respond to changes in thegate-source voltage.
The signal applied to the gate suffers anadditional equivalent gate resistance from thedistributed channel resistance.
Since the channel conductance seen by thesource is related to gm, we would expect that thechannel resistance (Rgs) is proportional to 1/gm.
Rg consists of two parts: the Rg,i, contributed bythe gate resistance and the Rg,nqs due tochannel charging resistance.
1gs
m
Rg
∝
Proposed Modeling Methodology
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The transconductance delay τ is modeled by twoways: included by multiplying gm by exp(jωτ). The transconductance delay can also be
represented by the transcapacitance Cm. It has been known that BSIM model includes an
NQS option and has been verified withmeasurements for devices.
The NQS effect will equivalently introduce atranscapacitance between the drain and gate as thedisplacement current from Cgd can cancel partiallythe output current, which is equivalent to anincreased delay to the signal.
Proposed Modeling Methodology
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Parasitic network between gate and
drain
Parasitic network between gate and
source
Parasitic network between drain and
source
Gate
Source Drain
Rnqs
Cnqs
Core Model
typical equivalent circuit model for mm-wave transistorproposed in this work, after the extraction, we achieve:the Rnqs=1/5gm, Cnqs=1/10Cgg .
Proposed Modeling Methodology
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MotivationProposed MethodologyResults and DiscussionsSummary
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Outline of Presentation
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0 20 40 60-0.01
0
0.01
0.02
0.03
Frequency (GHz)
Y11
0 20 40 60
-10
-5
0
5x 10-3
Frequency (GHz)
Y12
0 20 40 60-0.04
-0.02
0
0.02
0.04
Frequency (GHz)
Y21
0 20 40 60-5
0
5
10
15
x 10-3
Frequency (GHz)
Y22
Real, MeasurementImag, MeasurementReal, ModelImag, Model
L=150nm Wf =1u Nf =32
Measured and modeled Y-parameters for MOSFETs with L=150nm, Wf=1u and Nf=32 (TSMC 90nm).
Results and Discussion
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Results and Discussion
0 20 40 60
0
10
20
x 10-3
Frequency (GHz)
Y11
0 20 40 60-10
-5
0
x 10-3
Frequency (GHz)
Y12
0 20 40 60-0.04
-0.02
0
0.02
0.04
Frequency (GHz)
Y21
0 20 40 60-5
0
5
10
15
x 10-3
Frequency (GHz)
Y22
Real, MeasurementImag, MeasurementReal, ModelImag, Model
L=100nm Wf =1u Nf =32
Measured and modeled Y-parameters for MOSFETs with L=100nm, Wf=1u and Nf=32 (TSMC 90nm)
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0 10 20 30 40
-5
0
5
10
15 x 10-3
Frequency (GHz)
Y11
0 10 20 30 40
-4
-2
0
2
x 10-3
Frequency (GHz)
Y12
0 10 20 30 40
-0.02
0
0.02
0.04
0.06
Frequency (GHz)
Y21
0 10 20 30 40
0
5
10
15 x 10-3
Frequency (GHz)
Y22
Real, MeasurementImag, MeasurementReal, ModelImag, Model
L=60nm Wf =1u Nf =32
Measured and modeled Y-parameters for MOSFETs with L=60nm, Wf=1u and Nf=32 (SMIC 65nm).
Results and Discussion
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0 10 20 30 40-0.01
0
0.01
0.02
0.03
Frequency (GHz)
Y11
0 10 20 30 40-8
-6-4-2
024 x 10-3
Frequency (GHz)
Y12
0 10 20 30 40-0.05
0
0.05
0.1
Frequency (GHz)
Y21
0 10 20 30 40-5
0
5
10
15
20x 10-3
Frequency (GHz)
Y22
Real, MeasurementImag, MeasurementReal, ModelImag, Model
L=60nm Wf =1u Nf =64
Measured and modeled Y-parameters for MOSFETs with L=60nm, Wf=1u and Nf=64 (SMIC 65nm).
Results and Discussion
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Inp
Outn Outp
stage1Outpoutn
InpInn NVDD stage2Outp
outnInpInn NVDD stage3Outp
outnInpInn
VIN Vout
InnNeu_cap
No balun here when used in the receiver
VB VB
The proposed modeling methodology is also used to design a 60GHz low noise amplifier (LNA).
Results and Discussion
three stage differential structure, transformer are used for interstage match
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50 55 60 65
-30-20-10
010
20
Frequency, f [GHz]
Spar
/NF,
[dB
]
MeasurementPDK ModelProposed Model
Blue: S21
Black: S11
Red: S22
Green: NF
50 55 60 65
-30-20-10
010
20
Frequency, f [GHz]
Spar
/NF,
[dB
]
PDK ModelProposed Model
Blue: S21
Green: NF
Red: S22
Black: S11
Measured and modeled S-parameters and NF for LNA.
Results and Discussion
The measurements is ina good agreement withthe modeled results witha 0.5 GHz of frequencymismatch. The noisefigure (NF) is also well-predicted by the model.
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-30 -25 -20 -15 -10 -5-60
-40
-20
0
20
input power (dBm)
Out
put t
one
pow
er (d
B)
Main toneIM3 toneExtend for IIP3
Line: Model
Two-tone intermodulation distortion for LNA.
Results and Discussion
The measured and modeled IIP3 is -7dBm and -8dBmrespectively. The input and output power is shown and themeasured 1-dB compression point is -16dBm which matchesthe predicted value based on the proposed modelingmethodology. Again we got the satisfied results.
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MotivationProposed MethodologyResults and DiscussionsSummary
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Outline of Presentation
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Summary A novel modeling methodology for millimeter-wave
MOSFETs based on standard digital core model isproposed and investigated.
This methods takes into account the layout effectand NQS effect, which play a significant role in themillimeter-wave scope.
The proposed method is compared with themeasured data and good accuracy is achieved fora standard 90nm and 65nm CMOS technology.
This proposed model has been successfullyapplied in 60G LNA design.
When you have trouble in choosing HF transistormodel, you can try this method. 28
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Thanks for attention!