I/O and ESD Device Optimization for Nanometer Node CMOS ...

I/O and ESD Device Optimization for Nanometer Node CMOS TechnologiesIRCC IIT-Bombay industry impact award 2008

IRCC IITB Industry Impact Award 2August 4, 2010

Team members Mayank Shrivastava (Ph.D. from IIT-Bombay, Graduated in 2010)

Faculty Members V. Ramgopal Rao, M. Shojaei BaghiniAcknowledging Dinesh K. SharmaEE Department, IIT-Bombay

Industry CollaboratorsHarald Gossner, Jens Schneider, Christian Russ Infinion Germany


Few Facts Related to the Context Understanding physical phenomena

is a requirement in many physical systems.

To verify the understanding and make a unified model well-calibrated models matching measurement results are needed.

Industry is interested in increasing yield, improving productivity and novel cost-effective solutions.


Few Facts Related to the Context (cont’d) Many phenomenas though look simple

but they can be explained in many ways out of which majority may not be correct.

Industry is interested in understanding and analysis, increasing yield, improving productivity and novel cost-effective solutions.


Content Introduction and MotivationI/O and ESD (Electro Static Discharge) Issues in

Nanometer CMOS Technology

Experimental Techniques Research and Outcomes of the Project

HV I/O Devices in CMOS Technology (Proposed Novel DeMOS Device)

Unified Failure Model of DeMOS DevicesDevice Design Guidelines

Conclusions


Introduction and Motivation

I/O and ESD (Electro Static Discharge)

Issues in Nanometer CMOS Technology


Introduction and MotivationESD: Electro Static Discharge

Lightning: A natural ESD Phenomena (source: Wikipedia)

ESD Through IC Pins in Electronic Boards (Photo source: DAU)


Introduction and Motivation (cont’d)

Source: H. Gieser, PhD thesis, Technical University of Munich, 1999.

Discharge Models



4-core processor with 8MB-L3-cache die having 731M transistors in 45nm high-κ metal-gate CMOS technology by Intel

Source: R.Kumar, G. Hinton, ISSCC 2009



Source: H. Gossner VLSI Design Conf. 2009

Challenge: ESD reliability trades with performance as CMOS technology scales down.



• Multi-supply Chips• Susceptibility to ESD which leads to Electrical stress and reliability issues. • Signal Transitions on I/O Interfaces• Limited flexibility of I/O devices• Shrinking ESD window by technology scaling

Source: Ming-Dou Ker, Kun-Hsien Lin, IEEE Trans. On CAS I, 2006.

I/O Performance Challenges


Experimental Techniques


ESD Protection Concept in advanced CMOS ICs


Transmission Line Pulsing Technique

For IIT-Bombay project, TLP experiments were performed in Infinion Germany.

Source: ECN, Nov. 2007


Transmission Line Pulsing Technique (cont’d)

Source: ECN, Nov. 2007


Research and Outcomes of the ProjectHV I/O Devices in CMOS Technology (Proposed Novel DeMOS Devices)

Unified Failure Model of DeMOS DevicesDevice Design GuidelinesNovel Devices for Robust ESD Protection


Simulation of HV devices

TCAD-based platform 130nm technology node Calibration of process simulation deck

based on measurements Tox=2.2nm, STI depth=350nm Optimization for maximum ION/IOFF and

break down voltage


HV Devices in Planar CMOS Technology

- M. Shrivastava, M. S. Baghini, H. Gossner, V. R. Rao, Part I and Part II, IEEE Trans. On ED, Feb. 2010.

- M. Shrivastava, H. Gossner, V.R. Rao, M.S. Baghini, United States Patent , Application No: 12/408,839, 2008P51967US

Proposed device

LDDMOS

Non-STI DeMOS

USTI DeMOS

STI DeMOS


Optimized HV Devices

M. Shrivastava, M. S. Baghini, H. Gossner, V. R. Rao, Part I, IEEE Trans. On ED, Feb. 2010.


Performance of Optimized HV Devices


Comparison of Analog/Digital Performance of Reported HV Devices

Non-STI DeMOS Best performance

M. Shrivastava, M. S. Baghini, H. Gossner, V. R. Rao, Part I, IEEE Trans. On ED, Feb. 2010.


Analog/Digital Performance of Proposed USTI Device

USTI DeMOS Improved mixed-signal performance compared to STI DeMOS

STI Depth = 350nm at source side

M. Shrivastava, M. S. Baghini, H. Gossner, V. R. Rao, Part II, IEEE Trans. On ED, Feb. 2010.


Variability Performance of USTI

M. Shrivastava, M. S. Baghini, H. Gossner, V. R. Rao, Part I and II, IEEE Trans. On ED, Feb. 2010.

STI USTIIncorporating STI leads to variability issues.USTI DeMOS relaxes variability issues.


Test Structure of STI DeMOS Devicefor ESD Experiments

Gate Gate

ST

I

ST

I

ST

I

ST

I

N-Well

P-Well P-Well

Triple-Well Triple-Well

Body

Sourc

eSub

strat

e Source

SubstrateDrain

DL

xz

y

Folded/two-finger structure of DeNMOS device, fabricated in standard 65nm CMOS process


Operation of Protection DeviceSimple Behavior


W=50µ m

Fails in the range of 1.3-1.7 mA/µ m

Reversibility:

Up to 90% of IT2

Gate and substrate bias lead to no considerable change.

Experimental TLP Characteristics of STI DeMOS Device

M. Shrivastava, J. Schneider, M. S. Baghini, H. Gossner, V. R. Rao, IRPS 2009.


SEM Image


SEM Image of failed device


TLP Measurements

Setup for device stressing

Measured TLP characteristics at RL=1KΩ

M. Shrivastava, S. Bychikhin, D. Pogany, J. Schneider, M. S. Baghini, H. Gossner, E. Gornik, V. R. RaoIEEE IEDM 2009.


Next Step: Explaining Experimental/Measured Characteristics Using TCAD Simulations

Prior Work: ESD Reliability & Modeling

LDMOS/DeMOS Failure at the onset of parasitic bipolar triggering.

[V. A. Vashchenko, Springer 2008][P. Hower, IEDM 99]

[Gianluca Boselli, IRPS 2007] [A. Chatterjee, IEDM 2005, IRPS 2008]


Junction Breakdown



Bipolar Triggering

Parasitic Biploar is turned on at moderate currents.Drop in carrier mobility and increase in the base length ⇒Reduction in the slope of TLP characteristics at higher current.



Space Charge Formation and Shift


TLP current ↑ ⇒Significant space charge build up underneath the drain diffusion. ⇒ significant high electric fields underneath the drain diffusion because of carrier modulation i.e. base push-out.


Base Push-Out


Impact Ionization contours (1/(cm3.s))Devices with smaller DL suffer from high current densities which drives them into early base push-out causing a thermal failure.


Mode A: Physics

One finger triggering Higher current density at the well junction Higher impact ionization Efficient bipolar triggering

Snapback state: Mode AM. Shrivastava, S. Bychikhin, D. Pogany, J. Schneider, M. S. Baghini, H. Gossner, E. Gornik, V. R. RaoIEEE IEDM 2009.


Mode B: Physics

• Two finger triggering

• Relaxed current density at the well junction

• Fewer impact ionization carriers

• Inefficient bipolar triggering • High resistance state: Mode B



Behavior at Moderate Currents• Higher ITLP

• Higher current density at the well junction

• Significant no. of impact ionization carriers

• Both the finger triggers efficiently • Both the modes get merge into one single state



ESD Stress: Transient Behavior During Failure

M. Shrivastava, H. Gossner, M. S. Baghini, E. Gornik, V. R. Rao, IEEE Trans. On ED, Part I, Accepted, 2010.


ESD Stress: Transient Behavior During Failure (cont’d)



A New Insight to ESD Failure of DeMOS Devices

Significant Space charge Buildup

Discharge and Power dissipation



A New Insight to ESD Failure of DeMOS Devices (cont’d)

Capacitance and instantaneous power before and after Base push-out.



Differences Between 2D and 3D Modeling


DeMOS suffers from heavy charge modulation at early currents and hence cannot be always modeled using 2D device simulations.


Next step: Modeling of Failure Using 3D Simulation


Filament Behavior, Current Density

DL=0.2µ mCurrent density (A/cm2)

• High heating Filament shrink at drain side

• Regenerative NPN Filament shrink at source side

M. Shrivastava, H. Gossner, M. S. Baghini, E. Gornik, V. R. Rao, IEEE Trans. On ED, Part II, Accepted, 2010.


“Unified Model” for Current Filamentation and Device Failure

Space charge localization in the 3D plane (near N+ drain, inside filament) i.e. Localized carrier modulation

Localized "space charge" in the 2D plane (near N+ drain)

Onset of Base Push-out

Localized "space charge" in the 2D plane (near N+ drain)

Electric Field in 2D plane

Carrier mobilityin 2D plane

Uniform bipolar conduction, device servived

Localized Base push-out in 3D plane further increses the electric field in the localized region or degrades mobility

Leads ElectricalImbalance ?

Electrical imbalance causes non-uniform flow of current across the device width.

Filamentation

Was Filament width saturated ?

Excess temperature & Device Failure

No Yes

Yes

No


Device Design Guidelines


Conclusions USTI DeMOS has mixed signal performance similar

to non-STI DeMOS and hot carrier reliability equivalent to STI DeMOS.

Bipolar triggering does not lead to an ESD failure in DeMOS devices.

Pulse-to-pulse instability is not a simulation or measurement artifact.

Space charge modulation causes very high local electric fields, which eventually leads to current filamentation and failure.


Conclusions (cont’d) Failure model for all the DeMOS devices is unified

Design guidelines for ESD robust drain extended devices Survive charge modulation i.e. base push out at early currents Improvement by ~5-6X.

Highly-resistive body helps to achieve moving filaments, which improves ESD failure threshold of DeNMOS devices.

Highly resistive body and floating N-Well improves triggering property of SCR Can be now used efficiently for CDM protection.


Fulfilling industry requirements Awards including IRCC IIT-Bombay

Industry Impact Award 1 Indian patent application 6 US patent applications 6 Journal papers 7 conference papers

I/O and ESD Device Optimization for Nanometer Node CMOS ...

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