I/O: A Detailed Example - Computer Action Teamweb.cecs.pdx.edu/~zeshan/ece585_lec4.pdf ·...
Transcript of I/O: A Detailed Example - Computer Action Teamweb.cecs.pdx.edu/~zeshan/ece585_lec4.pdf ·...
ECE 485/585Microprocessor System Design
Lecture 4: SRAM Basics
Memory Organization
Zeshan Chishti
Electrical and Computer Engineering Dept
Maseeh College of Engineering and Computer Science
Source: Lecture based on materials provided by Mark F.
ECE 485/585
Outline
Taxonomy of Memories
Memory Hierarchy
Register Files
SRAM
◼ Basic Cell, Devices, Timing
Memory Organization
◼ Multiple banks, interleaving
DRAM
◼ Basic cell, Timing
DRAM Evolution
DRAM modules
Error Correction
Memory Controllers
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Static RAMs (SRAM)
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SRAM Technology
Write◼ Write bit and bit onto bit lines
◼ Select desired word (“row”)
◼ Turns on pass transistors
◼ Writes new value to cell
◼ [One inverter input will be low, turning its output high]
Read◼ Select desired word (“row”)
◼ One bit line will be pulled low
◼ Other will remain high
word line
bit line bit line
addr
data
SRAM Cell
6 transistors
For density and low power, want tiny transistorsbut they can’t drive long bit lines
Sol’n: Pre-charge bit lines (Vdd/2) before readSense differential between bit and bit
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Dual-ported Memory Internals
Add decoder, another set of read/write logic, bits lines, word lines
Example cell: SRAM
Repeat everything but cross-coupled inverters.
This scheme extends up to a couple more ports, then need to add additional transistors.
deca decbcell
array
r/w logic
r/w logic
data portsaddress
ports
b2 b2b1 b1
WL2
WL1
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Basic SRAM
Size in bits (organization)
◼ 1Mb (256K x 4) → 256K words of 4 bits
◼ 1Mb (128K x 8) → 128K words of 8 bits
Most control signals are active Low
◼ Chip Select (/CS) effectively an enable
◼ Write Enable (/WE) controls read/write
To perform a write
◼ /WE is asserted (Low)
◼ /CS is asserted (Low)
To perform a read
◼ /WE is de-asserted (High)
◼ /CS is asserted (Low)
2n x b RAM
A0
A1
An-1
DIN0
DIN1
WE
CS
DINb-1 DOUTb-1
DOUT1
DOUT0
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SRAM Variations
Din & Dout often combined to save pins ($)
2n x b RAM
A0
A1
An-1
DIN0
DIN1
WE
CS
DINb-1 DOUTb-1
DOUT1
DOUT0
• A new control signal, Output Enable (/OE)
2n x b RAM
A0
A1
An-1
WEOECS
D0
D1
Db-1
❑ Dedicated Din & Dout
• Trade pin count ($) for higher performance
• No bidirectional “turnaround” time required
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Simplified SRAM timing diagram
Read: Valid address, then /CS (Chip Select) asserted
Access Time: Address good to data valid
Cycle Time: Minimum time between subsequent memory operations
Write: Valid address and data with /WE asserted, then /CS asserted
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Internal SRAM Organization (16x4)
SRAMCell
SRAMCell
SRAMCell
SRAMCell
SRAMCell
SRAMCell
SRAMCell
SRAMCell
SRAMCell
SRAMCell
SRAMCell
SRAMCell
- +Sense Amp - +Sense Amp - +Sense Amp - +Sense Amp
: : : :
Word 0
Word 1
Word 15
Dout 0Dout 1Dout 2Dout 3
- +Wr Driver
- +Wr Driver
- +Wr Driver
- +Wr Driver
Addre
ss Decod
er
WriteEnableDin 0Din 1Din 2Din 3
A0
A1
A2
A3
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Example: Cypress SRAM
• Key SRAM timing parameters
– tAA – Address access time: time between a valid address being applied and valid data available on data outputs
– tRC – Read cycle time: Minimum time that one address must be held on the address lines before a second address can be presented
• tAA represents latency
• tRC represents bandwidth (throughput)
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What happens as number of bits increases?
Decoder gets larger and slower
Bit lines increase in length
◼ Large distributed RC load
◼ Compensate with larger, slower transistors
Remember
◼ Treat output as differential signal
◼ Pre-charge both bit lines high
◼ Memory cell pulls only one low
◼ Sense bit value by comparing sense lines
→ Option: Make array shorter andwider!
n b
its
Log2 n bit
address
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n = k x m bits
Log2 k bit
“row” address
Sense amps
Log2 m bit
“column” address 1 data bit
mux
Inside a Tall Thin RAM is…
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Log2 k bit
“row” address
Log2 m bit
“column” address 4 data bits
n = k x m bits
Sense amps
mux
Replicate for Desired Width
1 data bit x 4
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Physical SRAM Array Should Be Square
DO
Example: 16 x 1 SRAM → 4 x 4 Array DI
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
IN
SEL
WR
OUT
2-to-4
Decoder
/WE/CS
/OE
0
1
2
3
10
A1A0
4-to-1 MuxES
2-to-4Decoder
A3-A2
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Synchronous SRAM
So far we’ve been talking about SRAMs w/ asynchronous reads but there are fully synchronous SRAMs
◼ Faster than asynchronous SRAMs but need to be clocked
◼ Microprocessor manufacturers implement synchronous SRAMs for internal caches
◼ FPGA manufacturers embed dedicated synchronous SRAM blocks in their FPGAs
Provides Kb’s to Mb’s of RAM w/o using flip-flops in FPGA fabric
Highly configurable (bit width, memory depth, parity/no parity, input/output latches, pipeline registers, etc.)
Single cycle access up to speeds near max for FPGA depending on FGPA family
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Memory Subsystems
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Memory Organization
How do we build memory subsystems out of memory devices?
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256K x 8 Memory System:Use four 64K x 8 RAM chips256K → 18 address lines◼ 16 shared address
lines to array◼ 2 address lines
decoded to provide /CS(one per chip)
◼ common R/W and tri-statedata outputs
Making the Memory Deeper
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64K x 16 Memory System:Use two 64K x 8 RAM chips
◼ 16 shared addresslines
◼ shared control signals
Making the Memory Wider
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Access Pattern without Interleaving: CPU Memory
Start Access for D1 Start Access for D2
D1 available
Access Pattern with 4-way Interleaving:
Access B
an
k 0
Access Bank 1
Access Bank 2
Access Bank 3
We can Access Bank 0 again
CPU
MemoryBank 1
MemoryBank 0
MemoryBank 3
MemoryBank 2
Memory Interleaving
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address
Bank 0
048
12
address
Bank 1
159
13
address
Bank 2
26
1014
address
Bank 3
37
1115
Memory Interleaving (cont’d)
read 00000
read 00001
read 00002
read 00003
read 00004
for (i = 0; i <16; i++)
A[i] = A[i] * c + d;
(assume A[0] at address 0)
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Memory Interleaving (cont’d)
Low Order Address Interleaving
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Memory Interleaving (cont’d)
Low Order Address Interleaving w/ Byte Select
Byte SelectBank Select
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Memory Interleaving (cont’d)
High Order Address Interleaving
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256K x 8 Memory System:Use four 64K x 8 RAM chips256K → 18 address lines◼ 16 shared address
lines to array◼ 2 address lines
decoded to provide /CS(one per chip)
◼ common R/W and tri-statedata outputs
High Order Interleaving at Work…
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Memory Interleaving (cont’d)
Byte SelectBank Select
High Order Address Interleaving