Chapter 2 – Transistors – Part 2Chapter 2 – Transistors – Part 2

Field Effect Transistors (Unipolar Transistors)(Charge carriers: either electrons or holes)

Bipolar Transistor Bipolar Transistor

Electrons and holes are crossing Electrons and holes are crossing emitter junctionemitter junction

1) Field-effect transistors were invented by Julius Edgar Lilienfeld (Jewish Austro-Hungarian physicist) in 1925 and by Oskar Heil (German electrical engineer and inventor) in 1934.

2) Practical devices were not able to be made until 1952 (the JFET).

3) Commonly used for weak-signal amplification.

4) Two types of FETs are : n-channel and p-channel FET.

Field Effect transistor (FET) (or Unipolar transistors Field Effect transistor (FET) (or Unipolar transistors ))

5) The FET is a three terminal device i.e. the source (S), drain (D), and gate (G).

6)6) SourceSource : Provides the source of charge carriers (electrons/holes) for the channel current ( equivalent to Emitter in Transistor).

7) DrainDrain : The place where the charge carriers are removed ( or “drained”) from the device ( equivalent to Collector in Transistor). .

8)8) Gate Gate : Controls the current flow in the channel ( equivalent to Base in Transistor).

9) In both n-channel and p-channel, the charge carriers always flow from the source connection to the drain connection.

10) In n-channel, charge carriers are electrons.

11) In p-channel, charge carriers are holes.

n-channel FET

nD ep le tio nregio n s

n -ch an n e l

M eta l e lec tro d e

In su la tio n(S iO 2 )

p

S DGp+

(b )

DS

G

C ircu it sy m b o lfo r n -ch an n e l F E T

p-channel FET

Major Application – Display Driving CircuitMajor Application – Display Driving Circuit

FET – Fabrication and Operation FET – Fabrication and Operation

(reverse-biased)

n-channel FET n-channel FET

1) Only one carrier type is involved in charge flow.

2) The charge flow is due to drift (as diffusion current small).

3) The voltage applied to the gate (reverse-biased) controls the current flowing in the source-drain channel.

4) No current flows through the gate electrode. Thus the gate is essentially insulated from the source-drain channel.

6) Near the Drain end of the Gate : (i) Width of channel narrowest and (ii) junction width is widest.

7) Because here the reserve bias is the sum of Gate potential (Vgs) and the Drain potential (Vds).

8) Nonuniform voltage drop along the channel and nonlinear variation in channel width make the exact analysis complicated.

Drain Current , Drain Current , IIdd

voltage pinch off is actually for a given –VGS any increase in VDS will notcause further increases in drain current. If drain current stops this is VGS OFF which is of the same magnitude as pinch off but opposite polarity voltage e.g. VGS off = - 5 pinch off voltage = +5 V on the transfer characteristiccurve.

(pinch off voltage)

(pinch of)

pinch off = 핀치 끄기Pinch = 핀치

Expression for drain current in saturation region.Vgs > Vp and Vds = Vgs – VpDrain current in the active region

Vds ≥ Vgs - Vp

activ

e re

gion

Drain current saturation occurs when the Vds equals the Vgs minus the Vp (pinch off voltage). The value of the saturated drain current, ID is then given by the above equation.

n-channel FET n-channel FET

1. Reverse Bias voltage near the drain end of the gate terminal - No drain current

Reverse Potential = Vgs (Gate potential) + Vds

(Drain potential) If -3V (Vgs ) and (10) (Vds ), then Reverse Potental = -13V or magnitude ofReverse Bias between p- and n-types is 13V Drain current Id = ?Case 1: If reverse voltage at the bottle neck

= -14V, Drain current Id = ?Case 2: If reverse voltage at the bottle neck

= -12V, Drain current Id = ?

Bottle neck Reverse Bias pn junction diode(fixed)

(varied)

2. Drain current IIdd is proportional to is proportional to Vgs - - Vp due to pinchoff.

Vp = -3V for n-channel FETCase 1: Vgs = -4 V, the Vgs - - Vp = -4 V – (-3V) = - 1.0VCase 2: Vgs = -3 V, the Vgs - - Vp = -3 V – (-3V) = 0VCase 3: Vgs = -2 V, the Vgs - - Vp = -2 V – (-3V) = +1.0VCase 4: Vgs = -1 V, the Vgs - - Vp = -1 V – (-3V) = +2.0VCase 5: Vgs = 0 V, the Vgs - - Vp = -0 V – (-3V) = + 3.0VCase 5: Vgs = 1 V, the Vgs - - Vp = 1 V – (-3V) = + 4.0V

(fixed)

(varied)Drain current Id

Increases

3. Additional reserve voltage, - Vds / 2

Reverse Bias voltage

Reverse Bias voltage

Reverse Bias voltage

Reverse Bias voltage

Exercise : 1 For n-channel FET

Id = Idss (1 – Vgs / Vp )2, Vp = - 3.0 V Find Id (i)Vgs = -2 , -1, and 1V(ii)Vgs = 0 V

If Id = 0 mA , Vgs = ?

N-channel FET – Biasing N-channel FET – Biasing

n-channel FET n-channel FET

1) The input impedance of the FET is extremely large (in the range of 1010–1015 Ω).

2) With a positive voltage on the drain, with respect to the source, electron current flows from source to drain through the CHANNEL.

3) If the gate is made negative with respect to the source, an electrostatic field is created, which squeezes the channel (i.e. channel width is reduced) and reduces the current.

4) Signal voltages applied to the gate result in corresponding variations in drain current.

n-channel FET n-channel FET

The physical meaning of this term (Idss) leads to one definition of pinch-off voltage, VP , which is the value of Vds (drain-source voltage) at which the maximum Idss flows.

Another definition of pinch-off voltage

Current-voltage characteristics Current-voltage characteristics ( or collector characteristics) p-channel ( or collector characteristics) p-channel

FETFET

Vds

(V)Id (mA)

Vds

(V)Id

(mA)

Vds

(V)Id (mA)

Vds

(V)Id (mA)

0 ---- 0 ---- 0 ---- 0 ----

5 ---- 5 ---- 5 ---- 5 ----

10 ---- 10 ---- 10 ---- 10 ----

15 ---- 15 ---- 15 ---- 15 ----

20 ---- 20 ---- 20 ---- 20 ----

Vgs = - 0.5V Vgs = 0 V Vgs = 0.5V Vgs = 1.0 V

Gate is reversed biased.

Operation : Current – voltage characteristics of Operation : Current – voltage characteristics of p-channel FET p-channel FET

-- --

The Transfer Characteristics The Transfer Characteristics

The transfer characteristic for a JFET can be determined experimentally,

(i)keep drain-source voltage, Vds constant, and

(ii) determine drain current, Id for various values of gate-source voltage, Vgs.

For p-channel FET For p-channel FET

When Vgs= VP with Vds= 0 (we get using Vp = Vgs + Vds ),the two depletion layers touch over the entire channellength and the whole channel is closed.

i)Characteristcs shows the variation of Id with Vgs.

ii) Idss denote the drain current with shorted gate.

iii) The curve extends on both sides i.e. Vgs can be negative as well as positive.

iv) Since Vgs can be positive also Idss is not maximum value of drain current.

v) Characteristics shows square law dependence (Id

V2gs).

vi) Transfer characteristics is an alternative way of describing the nonlinear electrical properties of the FET.

For n-channel FET For n-channel FET