VLSI TestingA 32 bit adder
A 32 bit counter
A 32Mb cache memory
Design for testability
Built-in self test
Synthesis for testability
design
Reliability: To tell whether a good system will work
correctly or not after some time.
Debug: To find the faulty site and try to eliminate the fault
VDD
0/1
0
0
0
0
0
*
Automatic test equipment (ATE) is extremely expensive
Shorten time-to-market
Defects detected in
Testing typically consists of
Applying set of test stimuli (input patterns, test vectors) to inputs of circuit under test (CUT), and
Analyzing output responses
The quality of the tested circuits will depend upon the thoroughness of the test vectors
Circuit
under
Test
(CUT)
-1011
11-00
-0-1-
01--0
0-101
1-001
0011-
-1101
1001-
01-11
Comparator
Stored
Correct
Response
p = prob. (a transistor is faulty)
Pf = prob. (the chip is faulty)
Pf = 1- (1- p) N
If p = 10-6
NCKUEE-KJLEE
Introduction.*
Introduction
Integrated Circuits (ICs) have grown in size and complexity since the late 1950’s
Small Scale Integration (SSI)
Medium Scale Integration (MSI)
Large Scale Integration (LSI)
Moore’s Law: scale of ICs doubles every 18 months
Growing size and complexity poses many and new testing challenges
VLSI
LSI
M
S
I
S
S
I
Chart1
1960s
1960s
1960s
1970s
1970s
1970s
1980s
1980s
1980s
1990s
1990s
1990s
2000s
2000s
2000s
Moore’s Law results from decreasing feature size (dimensions)
from 10s of m to 10s of nm for transistors and interconnecting wires
Operating frequencies have increased from 100KHz to several GHz
Decreasing feature size increases probability of defects during manufacturing process
A single faulty transistor or wire results in faulty IC
Testing required to guarantee fault-free products
VLSI Testing
VLSI circuit are large
I/O access is limited
*
• Functional model--- logic function
Most commonly used fault model: Single stuck-at
fault
A
B
C
D
E
F
G
Transistor stuck-on faults, Delay faults
A s-a-1
A s-a-0
E s-a-1
E s-a-0
D s-a-1
D s-a-0
C s-a-1
C s-a-0
B s-a-1
B s-a-0
F s-a-1
F s-a-0
G s-a-1
G s-a-0
14 faults
Wafer yield = 12/22 = 0.55
Wafer yield = 17/22 = 0.77
Testing and Quality
Quality of shipped parts is a function of yield Y and the test (fault) coverage T
Defect level (DL, reject rate in textbook): fraction of shipped parts that are defective
IC
Fabrication
Testing
Yield:
*
Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.
VLSI Testing
DPM (DL)
*
Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.
VLSI Testing
Given input vectors, determine the normal
circuit response
*
Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.
VLSI Testing
are detected by this test vector.
Example:
A
B
C
{ a0, b0, c1}
F
D
B
C
G
1
A
1
0
0
1
1
0
1/0
1/0
1
1
*
Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.
VLSI Testing
To detect D s-a-0, D must be set to 1.
Thus A=B=1.
E must be 1. Thus C must be 0.
Test vector: A=1, B=1, C=0
Given a fault, identify a test to detect this fault
Example:
A
D
B
E
C
F
0
1/0
1
1
1
0
1/0
*
Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.
VLSI Testing
ATPG: Given a circuit, identify a set of test vectors
to detect all faults under consideration.
Input circuit
*
Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.
VLSI Testing
2. Sequential test generation
*
Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.
VLSI Testing
Insert test points
D
Q
CK
DI
D
Q
Q,SO
SI
MUX
CK
N/T
(SE)
TMS: Test mode select
Places the job of device testing inside the device itself
Generates its own stimulus and analyzes its own response
circuit
shift register
1111
0111
0011
1
2
3
4
5
Z
Remainder
Quotient
0
1
5
6
7
8
1 0 1 0 1 1 1 1 0 0 0 0 0 Initial state
. .
. .
+
+
+
*
Probability of aliasing error = 1/2n (n: # of FFs)
VLSI Testing
A 32MB Cache memory --- BIST
A 107-transistor CPU --- All test techniques
An SOC
VLSI Testing
Testing is becoming a major factor in design optimization
Conventionally, the designer often optimize one of the three attributes: speed, area, and power.
At present, a fourth attribute is considered: Testability.
Two major fields in testing
ATPG