4366 Chapter7 testing of vlsi circuits

8/19/2019 4366 Chapter7 testing of vlsi circuits

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Chapter 7.

Testing of a digital circuit


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Failure: any departure of a system or module from its specified correct operation.

A failure is a malfunction.

Fault: a condition existing in a hardware or software module that may lead to the failure ofthe module

Hardware fault : external disturbances, manufacturing defects.

oftware fault : design mista!e.

"rror : an incorrect response from a hardware or software module. An error is the

manifestation of a fault. The occurrence of an error indicates that a fault is present inthe module.

Testing: fault detection# fault location.

Test

pattern

source

Circuit

under test

$C.%.T&Compare 'ood#bad

(eference )alue


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Fault model

stuc!*at fault

bridging fault

o stuc! at fault

+ open collector or open base

→ is stuc! at logic )alue - regardlessof x $ s*a*- or x s*a*&

+ short between collector and emitter→ is stuc! at regardless of x $ s*a*&

o bridging fault

/ost case: assume single stuc!*at fault

o Test generation

x 0 1 x2

3pp

C

"

4x

x-x5

x-x5

bridging

⇒

x-

x5

A 4

C

6"

F

x-x5

xn

exhausting test

5n → $n-& test


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-

-

-

-

-

-

-

-

-

- -

A#- 4# +++ +++ +++ too muchA#x- x5

Test )ector $-,&

Test generation

-. Algebraic algorithm: 4oolean difference ⇒ difficult to ma!e computer program5. tandard algorithm: 6*algorithm

o 4oolean difference: to determine the complete set of test to detect a stuc!*at fault.

The 4oolean difference of F$x& with respect to the input xi

&-$&.$

&,,,-,,,,$&,,,.,,,,$&$

--5---5-

ii

niinii

i

F F

x x x x x F x x x x x F dx

xdF

⊕=

⊕=+−+−

, let α be the fault where the input xi is s*a*

&.$&,,,.,,,,$&,,,$ --5-5- iniin F x x x x x F x x x F == +− α

The test pattern that detects the fault α$xi s*a*&

→ -&.$&$ =⊕α

F x F

Fault free )alue


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%sing hannon2s expression theorem

&.$&-$&.$8&.$&&-$&.$8$iiiiiiiiii

F F x F x F F x F x ⊕⊕=⊕+

&.$&.$8&-$&.$8

&.$&8$&-$&.$8

iiiiiiii

iiiiiii

F x F x F x F x

F x x F x F x

⊕⊕⊕=

⊕⊕⊕=

-&$

&.$&-$$ =⋅=⊕=i

iiii

dx

xdF x F F x

The test pattern

to detect xi s*a*

The test pattern to detect xi s*a*-

-

&$

8 =⋅→i

idx

xdF

x

9f F$x& is dependent on xi $i.e. the fault on xi is detectable&.

Fi$& will be different from Fi$-&

i

ii

dx

xdF F F

&$-&-$&.$ ==⊕→

The test pattern that detects the fault x i s*a*

-&$

-&$

- =⇒==i

i

i

i

dx

xdF x

dx

xdF And x

The test pattern that detects the fault x i s*a*-

-&$

8-&$

. =⇒==i

i

i

i

dx

xdF x

dx

xdF And x


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Test set for x- s*a*→

F1x-x5x52x

8

&$8&$8,

8

&$&$

iiii dx

xdF

dx

xdF

dx

xdF

dx

xdF ==

x-x

5

x

'-

'5

F

s*a* -&$=

i

idx

xdF x

5:55:5:55:5

:55:5--

-

&8$&88$&88&$8$

&8$&8$&-$&.$&$

x x x x x x x x x x x

x x x x x F F dx

xdF

=+++=

+⊕=⊕=

-&$

5-

-

- ==∴ x xdx

xdF x Test )ector x-, x5, and x for x- s*a* is $-,-,& or $-,-,-&

x-x5

x

'-

'5

F

s*a*

h

Test set for h s*a* →

F1x-x5h

-&$=

dh

xdF h

-8888&88$&8$&$

88&8$-&-$&.$&$

:5:5:5-5-:5

5-5-5---

==+=+⋅=⋅⇒

+==⊕=⊕=

x x x x x x x x x x xdh

xdF h

x x x x x x F F dh

xdF Test )ector

x-1don2t care

x51, x1-

∴$,,-& or $-,,-&

h


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6isad). of 4oolean difference; -.

6ifficult to manipulate algebraic e6 gates in the path, and 2s to the ?( and >?( gates in the path&. .

6etermine the primary inputs that will produce all the necessary signal )alues → bac!ward tracing or line @ustification.

"xample& Find a test )ector

s*a*x-x5

x

xB


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"xample& Find a test )ector

x-

x5

xB

x

'-

'5

'

'B

'

'D

'7

'E

e can2t find a test )ector using a single*path sensiti0ation. 9s there no test )ectorG Ans& we

don2t !now. e can try to use multiple*path sensiti0ation 1 6 algorithms.

/ultiple path sensiti0ation

6*algorithm; -IDD (oth$94/& fi)e logic )alues used :

+ ingular cube: The singular co)er of a gate is a compact truth table representation in

terms of the J,-,KL )ariables. "ach row of the singular

co)er is called a singular cube.

$&,#$,,, 100110 D D X

s*a*-


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- - -

K

K

- 5

Compact

truth table

-

5

-5

B - - $#-&

- 5 B

D

+ A primiti)e 6*cube$=6C& of a fault: minimal specification of inputs to set 6 or

at the output of a faulty gate.

+ =ropagation 6*cube: minimal specification of inputs to the gate such that a 6 or

on an input $inputs& is propagated to its output as 6 or

D

D

D

s*a*-

-5

B6 - - 6

- 6 -

6

- - 6 6

6

6 - 6

6 - 6

6

- 6 6 6

6 6 6

6

- 5 B

D Must replace to 6

φ φ φ

φ - - φ φ

- K 6

φ φ 6 6 λ

φ φ λ

-

K

6

- K 6∩ D

D D D

Dφ : inconsistent

λ : may be possible with another choice of propagation 6*cube


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Consider the process of generating a test for line # in fig -.B.E. e start with the

following cube, which includes the primiti)e 6*cube of failure for this fault:

The next step is to propagate this 6 farther toward line --. (eferring to propagation 6*

cubes in table -.B.-, cube @ shows that the 6 in cube ! is automatically propagated to lines

D and 7. Consider now the propagation along the path D, I, --. Table -.B.- again shows

that the 6 on line D can be mo)ed to line I by using cube d. 9n other words, a new cube

can be obtained by combining cubes d and !. This process of combination is referred to as

6*cube intersection.

Nines 7 and I now contain the change, which can be propagated further into line --.


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The next step is determine a )alue for the primary input line B since that is the only line

that has not been assigned a )alue. To create a in line -, both lines 7 and E must be a -;

howe)er, in cube m, line 7 is a 6, indicating that cube m cannot result in a test )ector along

, D, I, --. tart again from cube ! to propagate along the path , 7, -, --. This leads to

the following cube:

The )alues of - and B are re


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+ 6*frontier: The set of all gates whose output )alues are unspecified, but whose input

has some signal 6 or D

-

5

B

'-

'5

'

'B

'

'D

'7

'Es*a*-

D

7

E

I

-

--

-5

'E,'D- - - x x x 6 x x x

- x -

'E,'D- - - x x x x 6 x x x

- -

','Dx - - x x x x x x x x

- 6

x x x x x x x x x x x x

- - -

6*frontier - 5 B D 7 E I - -- -5

D

D

D

D

D

?ut, 'D- - - - - 6 - -

- - -

?ut, 'D- - - x - 6 - -

- - -

?ut, 'D- - - x x - 6 - -

- x -

'E,'D- - - x x - 6 x x x

- - 6 - -

D

D

D D

D D

D D

conflict


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hen conflict occurs, we ha)e to go bac! to the pre)ious 6*frontier

'E,'D

?ut, 'D- - - x - 6 6 -

- - - -

?ut, 'D

- - - x x - 6 6 - -

x x

-

'E,'D- - - x x - 6 x x x

- - 6 6

-

6*frontier - 5 B D 7 E I - -- -5

D

D

D

D

D

D

D

D- - - - - 6 6 -

-Test )ector

6*algorithm will deri)e a test for any fault if such a test exists


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6etection of Faults in =NA

+ =NA characteristic

-. 9n a circuit structure, =NA essentially has only two le)els of gates.

5. A more general fault model is necessary because of the way =NA is fabricated.

Fault /odel: incorrect logical connections in the A>6 and ?( plane

+ 'rowth $'& fault: a connection in the A>6 plane is missing *O causing the

implicant to grow

+ 6isappearance $6& fault: a connection in the ?( plane is missing *O causing the

implicant to disappear

+ hrin!age $& fault: an intended connection in the A>6 plane is made *O causing

the implicant to shrin!

+ Apperance $A& fault: an intended connection in the ?( plane is made *O causingthe implicant to appear

ingle fault assumption: 9mportant calsses of multiple faults are detected by any

single fault test set.


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+ 'rowth fault: N2 1 $CPCi @ Qx, 6&

+ hrin!age fault: N2 1 $CR Ci

@ Q S, 6&, S1,-+ 6isappearnce fault: N2 1 $C, 6P6i @ Q&

+ Appearance fault: N2 1 $C, 6P6i @ Q-&

- 5 1 -P>?T$5&

1 the cube in - not in 5


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+ Classification of fault*tolerant techni


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. Fault mas!ing

* 3oting $triple modular redundancy& T/( >/(

* "rror correcting code

B. 6ynamic redundancy: reconfiguration

+++ +++ +++fault

9f one of 6(A/ is fault, → 6(A/ fault

%sing reconfiguration

+++ +++ +++

fault

+++ +++ +++ Add

(emo)e

(econfiguration


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Triple modular redundancy

f 1 ab2a2 b

a b

a b

f

a ba b

a b

ba

ba

b

a

3

3

3

Assuming that )oter V3W is fault*free

ithout Assumption

a b

a b

a b

ba

ba

ba

3

3

3

3

3

3

3

3

3

")en if the )oter may be faulty./ain disad)antage: Cost

e use the critical en)ironment$spaceship&


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"rror detecting code

Hamming distance$H6& between two binary n*tuple AX4 is the number of position in

which AX4 differ.

A code C is d error detecting iff the minimum H6 between any two code words is d-

ci

c @

++

dd

d-

R

e can detect, but we can2t !now whose

error is detected

A code C is d error correcting iff the minimum H6 between any two code words is at least

5d-

+ +

dd

5d-

ci c @

RR

R

R

R

RR

Hamming Code single error detecting Hamming code

5


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6etection of multiple faults

+ a circuit with r wires

single fault assumption : 5+r faults $s*a* or s*a*-&

multiple fault assumption : r *- faults

→ consider the transformation of a gi)en circuits due to some faults, rather thanfaults themsel)es

→ of transformation YY r *-

+ For 5*le)el A>6*?( circuitss*a*

s*a*

same effect∴ remo)e

∑=

=n

i

i P f

-

,where =i is the ith =.9.

"ach A>6 gate: one =.9.

The effects of s*a* faults on the function A s*a* fault at input or output of a A>6 gate

→ eliminate one =.9. from the function→ test one minterm which is co)ered by that =.9. and by other =.9.→ a complete set of tests for s*a* faults for a two*le)el A>6*?( circuits, consists

of n tests corresponding to n =.9.2s in f.

Test minterm for the @th =.9. : ∑≠

∈ ji

i j j P P a &8$


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The effects of a s*a*- fault at input of A>6 gate

→ ?utput of that gate is independent of the input )ariable→ "


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e


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Testing =rocedure in scan*path design N=

-&can in test )ector \@ using Kn and TCZ

5&Apply corresponding test )ector on Ki inputs

&After sufficient time for signals to propagate, chec! output .

B&Apply one cloc! pulse to CZ to enter new )alues of \@ into corresponding FFs.

&can out with TCZ and chec! \@ )alues.

Ne)el*ensiti)e Ne)el stays for a certain period.

"dge*ensiti)e Ne)el only at pulse change.

4366 Chapter7 testing of vlsi circuits

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