iNEMI 2015 Roadmap Workshop Board Assembly TWG
Transcript of iNEMI 2015 Roadmap Workshop Board Assembly TWG
iNEMI 2015 Roadmap WorkshopBoard Assembly TWG
Jasbir Beth-ReworkDennis Willie-Pressfit
Leigh William Gesick, MaterialMike Gerner-NPI
Brent Fischthal-Placement Paul Wang, Chair
May 27 2014
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2015 Board Assembly TWG Chair
•Mike Gerner (Ducommun Inc.)-New Product Introduction
•Brent Fischthal (Panasonic)-SMT Component Placement
•Leigh William Gesick (SMT International)-Assembly Material
• Jasbir Bath (Bath & Associates Consultancy)-Rework and Repair
•Dennis Willie (Flextronics)-Press-Fit
•Process Technology-open
•Wave and Selective Soldering-open
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Key Trends (2013 Roadmap)
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Key Trends (2013 Roadmap)
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Board Assembly of 3D IC Integration
System-in-Package (SiP) Challenges/Opportunities
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Miniaturization: Passive components size
reduction
• From 2012 onwards the ‘M0201’ package will be introduced
• Dimensions: 0.2 x 0.1 mm
• This is half the size of a ‘01005’ package!
Sources: Murata, Rohm
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Technology
Ma
turi
ty
Basic
R&D
Applied
R&D
Mass
Production
Commercia-
lization
Die
Stacking
with wire
bonds
Package
on
Package
Stacking
(PoP)
C2C, C2W,
W2W
Stacking
W2W
Stacking
Full swing production for memories.
Every 18 months one layer increase
Testing and yield challenges give
way for Package stacking
Active applied R&D is undertaken
by Research Institutes. System
level challenges are key. In the
phase of industrialization.
Still in Upstream research,
technological challenges such
as yield & device architecture
are key issues.
3D Integration Technology3D IC Packaging 3D IC Integration 3D Si Integration
3D Integration Technology
John H. Lau
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Board Assembly Gap Analysis
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Test, Inspection &
Measurement TWG
• Chair: Christopher
Cain, Keysight
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Test Inspection Measurement TWG Chapter Scope
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Test, Inspection & Measurement Critical Issues
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Test Inspection Measurement TWG Gap Analysis
Board 2012 2014 2016 2018 Comments
Lack of Test Access (bed of nails)Already no physical test access for mobile
products
Lack of Test Access (virtual).
How well will emerging standards solve access
issues?
For what products is analog boundary scan a
solution?
Material Impact on Test
Impact of emerging board substrate materials
(halogen free, non-FR4 for high speed
applications)
Faster signal speeds
Lack of test solutions for HDI Depends on adoption rate.
Board Layout & DFT Tools
Packaging Hierarchy 3-D ICs? Need input from mobile products
On-Board Power Regulation Have figured out ways to deal with issues.
Functional, System
Testing of Higher Speed Signals
Defect Coverage and Diagnostics
Design for Functional Test
Equipment/Tools/CapabilitiesNode count > tester capability
(mid to high PCAs)
Lower overall cost of test
Lack of ODM/CM test expertise
Imaging Technologies
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Test, Inspection & Measurement TWG - Test R&D Needs• Mfg. Processes
– Integration of design for test tools into board level and system level design tools
– Tools that map functional test faults to structural defects.
– Improvement in Imaging Technology (AOI, AXI) capability, capital and operating costs.
– Standard testing of memory modules using Boundary Scan.
• Environmental Sustainability
– Equipment and Process standards for energy saving “standby mode”
• Energy Management
– Testing on devices that are heavily power moded. More effort to get power management than in providing test access -another challenge for test access.
– Regenerative Loading (minimizing amount of energy dissipated as heat by test loads, particularly for Power Electronics Testing).
• Medical Standards & Technology
• Packaging/Miniaturization
– Better design for test for System on Chip and System in Package.
– Testing Package on Package Components
– Metrology and Test for Nanotechnology
• Enterprise Systems
– Product and Component Traceability to address quality, counterfeit parts and environmental compliance
• Materials
– Impact of emerging surface finishes on contact repeatability
– Impact of emerging lead free Level 1 materials for new electronic packages
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Test TWG Summary