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IEE5011 –Autumn 2013 Memory Systems Duty Cycle Correctors (DCC) In GDDR5 SDRAM
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Transcript of IEE5011 –Autumn 2013 Memory Systems Duty Cycle Correctors (DCC) In GDDR5 SDRAM
Kuang-Yu,Li 2013
IEE5011 –Autumn 2013Memory Systems
Duty Cycle Correctors (DCC) In GDDR5 SDRAM
Kuang-Yu, LiDepartment of Electronics Engineering
National Chiao Tung [email protected]
NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
Outline IntroductionBasics
DCC and GDDR5
Comparison Analog and Digital DCC
All-Digital DCCDCC in GDDR5 Conclusion
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IntroductionGDDR5
AMD first shipped in 2008Sony used in 2013
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Basic GDDR5 (1/4)
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Basic GDDR5 (2/4)Pre-fetch of 8Array Bank GroupingNew training and trackingNew Clocking
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NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
Basic GDDR5 (3/4)Data strobe signal (DQS)~>Write data clock(WCK)CK x 1, WCK x2 , Data x4
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Basic GDDR5 (4/4)
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[1]
NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
Basics DCC (1/3)Why do we need Duty-Cycle-Correctors ?
Improve valid data windowReduce duty cycle error
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Basic DCC (2/3)Corrects input to 50% duty-cycleTwo functions:
Detect define 50% boundary
Correct adjust edge until correct
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NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
Basic DCC (3/3)Design :
Location –on/off pathIntegration -embedded or notLocking timeOperating frequency rangeOffset -comes from detectorImplementation -analog or digitalOther (power, area…)
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NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
Analog DCCSimple negative feedback
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Analog DCC :Detector Integrating Error
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Analog DCC :CorrectorCross-coupled differential pair
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,m
Max cn pO cyc
g RCCorrect V
I t
NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
Digital DCCSimple negative feedback
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Digital DCC :DetectorDetection Loop
Time-mutiplexing between clocksIntegrated error and amplified
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NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
Digital DCC :CorrectorChargepump :offset adjusting
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Analog and Digital ComparisonDigital DCC is preferred!
Power ,range ,function ,supply, mismatch
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Analog Digital
DCC sharing X V
Common mode Variation
Insensitive Sensitive
Correction range Narrow Wide
Power Efficient X V
Manual override X V
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NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
All-Digital DCC(ADDCC)Wide-range, high resolutionCombined with DLL
Low jitter and fast lock timeOpen loop scheme
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DLL_out
[3]
NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
ADDCC: TimingRising of DLL_out and Hclk
Phase error ε,WSG delay α
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ADDCC: Cycle Detector
Dual delay line with WSGOvercoming trade-offsSmall Overhead
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Measured Result
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Process 0.18um CMOS
Operating frequency 440MHz~1.5GHz
Supply 1.8V
Duty cycle ratio 50±2%
Peak-to Peak jitter [email protected]
Maximum lock-in time ADDCC:5 cycles
Area 0.053mm2
Power [email protected]% --> 50.6% @440MHz
NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
GDDR5 Clock DistributionP:PLL ,G:Global DriverDQ Pad
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DCC in GDDR5 Wide-range, fast-lock, offset tolerant [5]
Anti-harmonic binary search(ABS)
CML and PLL in clock distribution
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NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
DCC in GDDR5 :AdjusterBetween Rx and Driver
Off clock-path –jitter free4 phase clock
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Step: 6psRange: ±100ps
NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
DCC in GDDR5 :DetectorSwitch ,ABS circuit, 2 latches, comparatorTo adder based counter -> Adjuster
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DCC in GDDR5 :Detection Methodology iclk vs. qclk and qclk vs. iclkb
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DCC in GDDR5 :ABS CircuitWeighted Delay Cell and range adjuster
Anti-harmonic and wide frequency range
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Measured Result Operating frequency and correction range
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Measured Result :Locking TimeFive input clock ranges
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Measured Result :Locking process
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Chip Microphotograph0.0017mm2
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DCC in GDDR5 Summary
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Process 54m CMOS triple-metal
Operating frequency 800MHz~3.5GHz(1.6 GHz~7 GHz)
Supply 1.5V
Correction range -100ps ~ +100ps
Step resolution 6ps
Lock-in time Min:64 cycles
Max:256 cycles
Area 0.017mm2
Power [email protected]
NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li
ConclusionDigital DCC in state of the art DRAM design is
necessary and importantDCC in GDDR5 with wide-range fast-lock duty-
cycle corrector with offset-tolerant capabilityWCK is up to 3.5GHz to sustain 7Gbps/pin
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Reference [1] Kho, R ,et.al, “A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement
Techniques”, IEEE Journal of Solid-State Circuits, vol.45,no.1 ,pp120 - 133, Jan. 2010 [2] L. Raghavan et.al, “Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link,”
VLSI Design, pp 270-275,Jan.2010 [3] Dongsuk Shin et.al, “A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital
DCC”, ISSCC,pp184-185, Feb. 2007 [4] Shao-Ku Kao et.al, “All-Digital Fast-Locked Synchronous Duty-Cycle Corrector” IEEE Transactions on Circuits and
Systems ,vol.53,pp 1363 - 1367, Dec. 2006 [5] Dongsuk Shin , Kwang-Jin Na et.al, “Wide-Range Fast-Lock Duty-Cycle Corrector with Offset-Tolerant Duty-Cycle
Detection Scheme for 54nm 7Gb/s GDDR5 DRAM Interface,” Symposium on VLSI Circuits Digest of Technical Papers,pp 138-139, June 2009
[6] Kyung Hoon Kim et.al, “A 5.2Gb/p/s GDDR5 SDRAM with CML Clock Distribution Network”, ESSCIRC ,pp194 - 197, Sept. 2008
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